Display panel

Abstract

Embodiments of the present application provide a display panel including a multiplexing circuit and a wrong-charge prevention circuit. The multiplexing circuit includes a multiplexing unit including a first selection transistor and a second selection transistor; the wrong-charge prevention circuit includes an inverse control unit; the inverse control unit includes a first inverse transistor and a second inverse transistor. The multiplexing unit is configured to sequentially connect a data input line with a first data line and a second data line in time response to the first selection signal and the second selection signal being at an effective level. The inverse control unit is configured to control the first inverse transistor to be turned on to pull or maintain the level of the control electrode of the second selection transistor at an ineffective level in response to the first selection signal being at the effective level; and control the second inverse transistor to be turned on to pull or maintain the level of the control electrode of the first selection transistor at the ineffective level in response to the second selection signal being at the effective level, so as to prevent display abnormalities caused by the wrong transmission of data signals due to selection signal delay.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel. Background Technology

[0002] In the field of display technology, mux multiplexing technology is commonly used to transmit data signals to corresponding pixel columns via time-division multiplexing using a single data input line through switching. This reduces the number of source driver chips (hereinafter referred to as Source) used, thereby reducing cost and power consumption. However, the RC load of signal transmission traces increases due to the design of large size, high resolution, and narrow bezels, which aggravates the delay of the selection signal transmitted by the traces. This can cause some data signals to be incorrectly provided to irrelevant pixel columns, resulting in abnormal display. Summary of the Invention

[0003] This application provides a display panel that, through the design of a multiplexing circuit and a fault-prevention charging circuit, effectively provides data signals for multiple pixel columns, avoids signal interference and mistransmission, and improves the display performance of the display panel.

[0004] On one hand, embodiments of this application provide a display panel, the display panel including a display area and a non-display area, the display area including multiple pixel columns; each pixel column is connected to at least one data line and includes multiple pixel units; the non-display area includes a multiplexing circuit and a fault-prevention charging circuit, wherein; the multiplexing circuit includes at least one multiplexing unit, the multiplexing unit including a first selection transistor and a second selection transistor, wherein; the source and drain of the first selection transistor are connected between a data input line and a first data line, and the control electrode of the first selection transistor is connected to a first selection control line; the source and drain of the second selection transistor are connected between the data input line and a second data line, and the control electrode of the second selection transistor is connected to a second selection control line; the fault-prevention charging circuit includes an inverting control unit corresponding to the multiplexing unit, the inverting control unit including: a first inverting control group and a second inverting control group, wherein the first inverting control group includes a first inverting transistor, the second inverting control group includes a second inverting transistor, wherein; the source and drain of the first inverting transistor are connected between a data input line and a first data line, and the control electrode of the second selection transistor is connected to a first ... source and drain of the first inverting transistor are connected between a data input line and a second data line, and the control electrode of the second selection transistor is connected to a second selection control line; the source and drain of the first inverting transistor are connected between a data input line and a second data line, and the control electrode of the second selection transistor is connected to a second selection control line; the source and Between the second selection control line and the low-level power supply line, the control electrode of the first inverting transistor is connected to the first selection control line; and the source and drain of the second inverting transistor are connected between the first selection control line and the low-level power supply line, with the control electrode of the second inverting transistor connected to the second selection control line; wherein, the multiplexing unit is used to respond to the first selection signal transmitted by the first selection control line and the second selection signal transmitted by the second selection control line being at an active level in sequence, causing the first selection transistor and the second selection transistor to be turned on respectively, so as to connect the data input line with the first data line and the second data line in a time-division manner, providing data signals to the corresponding pixel units; the inverting control unit is used to respond to the first selection signal being at an active level, controlling the first inverting transistor to be turned on, so as to pull the level of the control electrode of the second selection transistor back to or maintain it at an inactive level; and responding to the second selection signal being at an active level, controlling the second inverting transistor to be turned on, so as to pull the level of the control electrode of the first selection transistor back to or maintain it at an inactive level.

[0005] The display panel provided in this application embodiment firstly achieves time-division multiplexing of the selection signal by setting a multiplexing circuit, thus avoiding signal interference, reducing the number of source driver chips, lowering power consumption, and saving costs. Secondly, through the design of the error-proof charging circuit, when the second selection signal is at an active level, the level of the control electrode of the first selection transistor is pulled back to or maintained at an inactive level. This prevents display panel malfunctions caused by providing incorrect data signals to the pixel units in the pixel column corresponding to the first selection transistor, thereby improving the display panel's display performance. Attached Figure Description

[0006] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0007] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0008] Figure 1 This is an exemplary structural diagram illustrating the arrangement of pixel units in a display panel provided in an embodiment of this application.

[0009] Figure 2 A structural block diagram of a display panel in the related technology provided in the embodiments of this application.

[0010] Figure 3 for Figure 1 An exemplary schematic diagram of the ideal control timing of the display panel is shown.

[0011] Figure 4 for Figure 1 An exemplary schematic diagram of the actual control timing of the display panel shown.

[0012] Figure 5 An exemplary structural block diagram of the display panel of mux1:2 provided in the embodiments of this application.

[0013] Figure 6 for Figure 5 An exemplary schematic diagram of the control timing of the display panel shown.

[0014] Figure 7 An exemplary structural block diagram of a mux1:3 display panel provided in an embodiment of this application.

[0015] Figure 8 for Figure 7 An exemplary schematic diagram of the control timing of the display panel shown.

[0016] Figure 9 An exemplary structural block diagram of a mux1:4 display panel provided in an embodiment of this application.

[0017] Figure 10 for Figure 9 An exemplary schematic diagram of the control timing of the display panel shown.

[0018] Figure 11Another exemplary structural block diagram of a mux2:4 display panel provided in an embodiment of this application.

[0019] Figure 12 An exemplary structural block diagram of a mux2:6 display panel provided in an embodiment of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0021] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to these processes, methods, products, or devices.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] In the field of display technology, the display panel can be, for example, an organic light-emitting diode (OLED) display panel, a liquid crystal display panel, or, of course, a Mini-LED display panel or a Micro-LED display panel. For example, Figure 1 As shown, the display panel 100 may include a plurality of pixel units PX arranged in an array, a plurality of gate lines G1~Gn, and a plurality of data lines D1~Dm. Wherein, along the first direction (exemplarily as shown in...) Figure 1 Pixel units PX arranged in the horizontal direction (as shown) can be defined as pixel rows, along the second direction (e.g., as shown in the example). Figure 1A vertically arranged group of pixel units PX can be defined as a pixel column. The pixel unit PX may include red (R) pixel units, green (G) pixel units, and blue (B) pixel units. One exemplary arrangement of the red, green, and blue pixel units is as follows: pixel units PX in the same pixel row have the same color, pixel units in the same pixel column have different colors, and pixel units of different colors are arranged alternately along a second direction. Another exemplary arrangement of the red, green, and blue pixel units is as follows: pixel units PX in the same pixel column have the same color, pixel units in the same pixel row have different colors, and pixel units of different colors are arranged alternately along a first direction.

[0024] like Figure 1 As shown, the plurality of gate lines may exemplary include gate lines G1, G2, ..., Gn arranged along a second direction, and each gate line is connected to a pixel unit in a pixel row for transmitting a scan signal. The plurality of data lines may exemplary include data lines D1, D2, ..., Dm arranged along a first direction, and each data line is connected to the pixel unit in at least one pixel column for transmitting a data signal. The data signal and the scan signal can be used to activate the corresponding pixel unit.

[0025] Currently, in order to reduce the number of source driver chips used to provide data signals, mux multiplexing technology can effectively reduce the number of data signal input channels. For example, see... Figure 2 The display panel shown and Figure 3The ideal control timing is shown. The display panel 100 includes two multiplexing units, and each multiplexing unit uses mux1:2 multiplexing. The first multiplexing unit may include a first selection transistor K1 and a second selection transistor K2. These transistors are time-division controlled by the selection signals transmitted via selection control line Demux A and selection control line Demux B, which are sequentially active. This controls selection transistors K1 and K2 to be time-divisionally turned on, so that the data signal provided by Source1 is transmitted to each pixel unit in the corresponding pixel column via data line D1 and data line D3, respectively. The second multiplexing unit may include selection transistors K3 and K4. These transistors are also time-division controlled by the selection signals transmitted via selection control line Demux A and selection control line Demux B, which are sequentially active. This controls selection transistors K3 and K4 to be time-divisionally turned on, so that the data signal provided by Source2 is transmitted to each pixel unit in the corresponding pixel column via data line D4 and data line D2, respectively. It should be noted that... Figure 2 The symbols "+" and "-" represent the polarity of the pixel unit. Box R represents a red pixel unit; box G represents a green pixel unit; and box B represents a blue pixel unit. Source1 and Source2 represent two data input lines (or channels) that provide data signals, which can be contained in a single source driver chip (Source IC) or in different Source ICs. For example, Source1 and Source2 can be different pins in a single source driver chip (Source IC) or pins of different Source ICs. In this application, the drawing of pixel units in the remaining figures is consistent with... Figure 2 The meanings are the same, and will not be repeated hereafter.

[0026] Therefore, through the above design, data signals can be transmitted to pixel units in at least four pixel columns using two sources, reducing the number of source ICs used and saving power consumption and cost. However, in actual use, as display panels develop towards larger sizes, higher resolutions, and narrower bezels (such as in-vehicle central control screens, foldable phones, etc.), the RC load of the signal transmission traces increases, exacerbating the delay of the selection signal transmitted by the traces. This can lead to data signals being incorrectly provided to irrelevant pixel units, causing abnormalities in the displayed image. For example, as... Figure 4 As shown, the increased RC load on the trace transmitting the selection signal leads to a greater delay in the falling edge of the selection signal transmitted on the selection control line Demux A. Figure 4(As indicated by the number 1 shown), in this situation, when the selection signal transmitted by the selection control line Demux B changes from an invalid level to an active level, the selection signal transmitted by the selection control line Demux A does not drop to an invalid level. At this time, the selection transistor K1 is still in the on state. The data signal to be provided to the pixel unit connected to data line D3 is also provided to the pixel unit connected to data line D1. In this case, the data signal written to the pixel unit connected to data line D1 when the selection signal transmitted by the selection control line Demux A is at an active level is overwritten by the newly written data signal (the data signal transmitted when the selection signal transmitted by the selection control line Demux B is at an active level). This causes the data signal written to the pixel unit connected to data line D1 to differ from the original design, resulting in display abnormalities. The analysis of other selection signals and selection transistors can be referred to the above understanding and will not be repeated here. Figure 3 or Figure 4 As shown, the effective level can refer to the selection signal being at a high level. The ineffective level can refer to the selection signal being at a low level. It should be noted that the effective level and ineffective level are relative and related to the type of selection transistors K1~K4, and this application does not impose any limitations on them. It should be understood that... Figure 2 The data lines D1 to D4 shown are merely illustrative markings for ease of description and are not intended to limit this application. The same applies to the following figures, and will not be further stated thereafter.

[0027] Based on this, this application provides a display panel that, through the design of a multiplexing circuit and an error-proof charging circuit, can achieve inverted output of different splitting selection signals by adding a DC signal at an invalid level. This prevents data signals from being incorrectly provided to unrelated pixel units, which could cause abnormal display. In this way, it can effectively provide data signals to multiple pixel columns, avoid signal interference and mistransmission, and improve the display performance of the display panel.

[0028] Specifically, in order to understand this application, the following detailed description is provided in conjunction with the following embodiments.

[0029] Example 1 Mux1:2 like Figure 5As shown, the display panel 100 may include a display area 10 and a non-display area 20. The display area 10 includes multiple pixel columns; each pixel column is connected to at least one data line and includes multiple pixel units PX; the non-display area 20 includes a multiplexing circuit 101 and a fault-proof charging circuit 102. The multiplexing circuit 101 may include at least one multiplexing unit 1011, which includes a first selection transistor (e.g., K11 and K21) and a second selection transistor (e.g., K12 and K22). The source and drain of the first selection transistor (e.g., K11 and K21) are connected between a data input line (e.g., source1 or source2) and a first data line (e.g., D1 or D4), and the control electrode of the first selection transistor (e.g., K11 or K21) is connected to a first selection control line (e.g., DemuxR1). The source and drain of the second selection transistor (e.g., K12 or K22) are connected between the data input line and a second data line (e.g., D3 or D2), and the control electrode of the second selection transistor (e.g., K12 or K22) is connected to a second selection control line (e.g., DemuxG1).

[0030] The error-proof charging circuit 102 includes an inverting control unit 1021 corresponding to the multiplexing unit. The inverting control unit 1021 includes a first inverting control group and a second inverting control group. The first inverting control group includes a first inverting transistor (e.g., TR1), and the second inverting control group includes a second inverting transistor (e.g., TG1). The source and drain of the first inverting transistor (e.g., TR1) are connected between the second selection control line (e.g., DemuxG1) and the low-level power supply line VGL, and the control electrode of the first inverting transistor (e.g., TR1) is connected to the first selection control line (e.g., DemuxR1). The source and drain of the second inverting transistor (e.g., TG1) are connected between the first selection control line (e.g., DemuxR1) and the low-level power supply line VGL, and the control electrode of the second inverting transistor (e.g., TG1) is connected to the second selection control line (e.g., DemuxG1). The multiplexing unit 101 is used to respond to... The first selection signal transmitted by the first selection control line DemuxR1 and the second selection signal transmitted by the second selection control line (e.g., DemuxG1) are sequentially at an active level, causing the first selection transistor (e.g., K11 or K21) and the second selection transistor (e.g., K12 or K22) to be turned on respectively, so as to connect the data input line with the first data line (e.g., D1 or D4) and the second data line (e.g., D3 or D2) in a time-division multiplexing manner, thereby providing data signals to the corresponding pixel units; the inverting control unit 1021 is used to control the first inverting transistor (e.g., TR1) to be turned on in response to the first selection signal being at an active level, so as to pull the level of the control electrode of the second selection transistor (e.g., K12 and K22) back to or maintain it at an inactive level; and to control the second inverting transistor (e.g., TG1) to be turned on in response to the second selection signal being at an active level, so as to pull the level of the control electrode of the first selection transistor (e.g., K11 and K21) back to or maintain it at an inactive level.

[0031] It should be noted that, see Figure 5 This diagram illustrates an exemplary structural schematic of a mux1:2 display panel provided in an embodiment of this application. Figure 5 The diagram illustrates two sets of multiplexing units, each connected to a data input line (e.g., Source1 or Source2). Multiple data input lines are provided by one or more source driver chips. In other words, multiple data input lines are contained within one or more source driver chips. Because one multiplexing unit can provide data signals for at least two data lines, the number of source driver chips can be reduced in practical applications. Each multiplexing unit includes a first selection transistor and a second selection transistor, wherein, as shown... Figure 5As shown, selection transistors K11 and K21 are the first selection transistors in different multiplexing units, and selection transistors K12 and K22 are the second selection transistors in different multiplexing units.

[0032] in, Figure 5 The control timing of the display panel shown is as follows: Figure 6 As shown, regarding the working principle of the multiplexing unit, exemplarily, the multiplexing unit composed of selection transistors K11 and K12 responds to the first selection signal transmitted through selection control line Demux R1 (the first selection control line) and the second selection signal transmitted through selection control line Demux G1 (the second selection control line) being sequentially at an active level, causing selection transistors K11 (the first selection transistor) and K12 (the second selection transistor) to be turned on respectively, so as to connect the data input line Source1 with the first data line D1 and the second data line D3 in a time-division manner, thereby providing data signals to the corresponding pixel units. The working principle of the multiplexing unit composed of selection transistors K21 and K22 is similar, and will not be described again here.

[0033] Regarding the working principle of the error-proof charging circuit, such as Figure 6 As shown, in the inverting control unit 1021, the first inverting transistor (e.g., TR1) of the first inverting control group is turned on in response to the first selection signal being at an active level, so as to pull the level of the control electrode of the second selection transistor (e.g., K12 and K22) back to or maintain it at an inactive level. Figure 6 The position indicated by the number 2 in the middle is pulled back to the low-level power line VGL), so as to turn off the connection between the data input line (source1) corresponding to the second data line (D3 at this time), so as to stop providing data signals to the second data line (D3 at this time), and to turn off the connection between the data input line (source2) corresponding to the second data line (D2 at this time), so as to stop providing data signals to the second data line (D2 at this time). The second inverting transistor (e.g., TG1) of the second inverting control group in the inverting control unit 1021 is turned on in response to the second selection signal being at an active level, so as to pull the level of the control electrode of the first selection transistor (e.g., K11 and K21) back to or maintain it at an inactive level. Figure 6 The connection between the data input line (source1) corresponding to the first data line (D1) is turned off at the location indicated by the number 3 in the middle, thereby stopping the supply of data signals to the first data line (D1) and the connection between the data input line (source2) corresponding to the first data line (D4) is turned off, thereby stopping the supply of data signals to the first data line (D4). The power signal transmitted by the low-potential power line VGL can be a low-level DC signal.

[0034] In this embodiment, the transistors in the multiplexing unit 101 and the transistors in the inverting control unit can be the same type of transistor. For example, the transistors in the multiplexing unit 101 and the transistors in the inverting control unit can each be N-type thin-film transistors, and the N-type thin-film transistors can include high-mobility oxide semiconductor materials; the high-mobility oxide semiconductor materials can be indium gallium zinc oxide semiconductor materials, indium zinc oxide semiconductor materials, or indium gallium zinc tin oxide semiconductor materials. The transistors used in subsequent embodiments are the same as those in Embodiment 1, and will not be described again hereafter.

[0035] Example 2 Mux1:3 This application also provides a mux1:3 display panel, see details below. Figure 7 and Figure 8 As shown. In this second embodiment, as Figure 7As shown, the multiplexing unit 101 further includes a third selection transistor (e.g., K13 or K23), the source and drain of which are connected between the data input line and the third data line (e.g., D3 or D6), and the control electrode of which is connected to the third selection control line (e.g., DemuxB1); the first inverting control group further includes a third inverting transistor (e.g., TR2), the source and drain of which are connected to the third selection control line (e.g., DemuxB1). The second inverting control group further includes a fourth inverting transistor (e.g., TG2), whose source and drain are connected between the third selection control line (e.g., DemuxB1) and the low-level power line VGL. The control electrode of the third inverting transistor (e.g., TR2) is connected to the first selection control line (e.g., DemuxR1). The second inverting control group also includes a third inverting control group, which includes a fifth inverting transistor (e.g., TB1) and a sixth inverting transistor (e.g., TB2). The source and drain of the fifth inverting transistor (e.g., TB1) are connected between the first selection control line DemuxR1 and the low-level power line VGL. The control electrode of the fifth inverting transistor (e.g., TB1) is connected to the third selection control line (e.g., DemuxR1). B1) Connection; the source and drain of the sixth inverting transistor (e.g., TB2) are connected between the second selection control line (e.g., DemuxG1) and the low-level power supply line VGL, and the control electrode of the sixth inverting transistor (e.g., TB2) is connected to the third selection control line. Figure 7 The control timing of the display panel shown can be found in [reference]. Figure 8 As shown, the positions indicated by numbers 4, 5, and 6 represent the locations where the corresponding inverting control transistors in the error-proof charging circuit are activated, and the corresponding selection transistors are pulled back to or maintained at an inactive level. For a detailed analysis, please refer to the aforementioned [reference to...]. Figure 6 The analysis will not be repeated here.

[0036] Example 3 Mux1:4 This application also provides a mux1:4 display panel, see details below. Figure 9 and Figure 10As shown. In this third embodiment, the multiplexing unit 101 further includes a fourth selection transistor (e.g., K14), the source and drain of which are connected between the data input line (e.g., source1) and the fourth data line (D4 in this case), and the control electrode of which is connected to the fourth selection control line (e.g., DemuxD); the first inverting control group further includes a seventh inverting transistor (e.g., TR3), the source and drain of which are connected between the fourth selection control line (e.g., DemuxD) and the low-level power supply line VGL. Between these, the control electrode of the seventh inverting transistor (e.g., TR3) is connected to the first selection control line (e.g., DemuxR1); the second inverting control group also includes an eighth inverting transistor (e.g., TG3), the source and drain of which are connected between the fourth selection control line (e.g., DemuxD) and the low-level power supply line VGL, and the control electrode of which is connected to the second selection control line (e.g., DemuxG1); the third inverting control group also includes a ninth inverting transistor (e.g., TB3), the ninth inverting transistor (e.g., T... The source and drain of the B3 transistor are connected between the fourth selection control line (e.g., DemuxD) and the low-level power supply line VGL; the control electrode of the ninth inverting transistor (e.g., TB3) is connected to the third selection control line (e.g., DemuxB1); the inverting control unit 102 further includes: a fourth inverting control group; the fourth inverting control group includes a tenth inverting transistor (e.g., TD1), an eleventh inverting transistor (e.g., TD2), and a twelfth inverting transistor (e.g., TD3); wherein the tenth inverting transistor (e.g., TD1), the eleventh inverting transistor (e.g., TD2), and the twelfth inverting transistor... The control stages of each transistor (e.g., TD3) are connected to the fourth selection control line (e.g., DemuxD). The source and drain of the tenth inverting transistor (e.g., TD1) are connected between the first selection control line (e.g., DemuxR1) and the low-level power supply line VGL. The source and drain of the eleventh inverting transistor (e.g., TD2) are connected between the second selection control line (e.g., DemuxG1) and the low-level power supply line VGL. The source and drain of the twelfth inverting transistor (e.g., TD3) are connected between the third selection control line (e.g., DemuxB1) and the low-level power supply line VGL. Figure 9 The control timing of the display panel shown is as follows: Figure 10 As shown, the positions indicated by numbers 7, 8, 9, and 10 represent how the corresponding selection transistors in the error-proof charging circuit are pulled back to or maintained at an inactive level when the inverting control transistors are operating. For a detailed analysis, please refer to the aforementioned... Figure 6 The analysis will not be repeated here.

[0037] In some embodiments, the selection control line connected to one of the multiplexing units 101 can be defined as a selection control line group; wherein, each of the at least one multiplexing unit 101 is connected to a selection control line in the same selection control line group, and the error-proof charging circuit 102 includes one of the phase-inverting control units. For example, as... Figure 5 The multiplexing unit composed of selection transistors K11 and K12 and the multiplexing unit composed of selection transistors K21 and K22 are connected to the selection control line in the same selection control group. At this time, the error-proof charging circuit 102 includes one of the inverting control units 1021.

[0038] In other embodiments, the at least one multiplexing unit is connected to a selection control line in a plurality of different selection control line groups, and the error-proof charging circuit includes a plurality of the inverting control units, the number of which is equal to the number of the selection control line groups. Examples are provided in Embodiments 4 and 5 below.

[0039] Specifically, for Embodiments 4 and 5, the details are as follows: Example 4 Mux2:4 This application also provides a mux2:4 display panel, see details below. Figure 11 As shown. In this fourth embodiment, the multiplexing circuit 101 may include a multiplexing unit composed of selection transistors K11 and K12 (referred to as multiplexing unit 1) and a multiplexing unit composed of selection transistors K21 and K22 (referred to as multiplexing unit 2). The selection control line groups connected to multiplexing unit 1 and multiplexing unit 2 are different: selection transistors K11 and K12 in multiplexing unit 1 are respectively connected to selection control lines DemuxR1 and DemuxG1 (referred to as selection control line group 1), while selection transistors K21 and K22 in multiplexing unit 2 are respectively connected to selection control lines DemuxR2 and DemuxG2 (referred to as selection control line group 2). In this case, the error-proof charging circuit 102 includes two inverting control units 1021, as shown... Figure 11As shown, it includes: an inverting control unit 1021-1 and an inverting control unit 1021-2. The inverting control unit 1021-1 includes: an inverting control transistor TR1 of a first inverting control group and an inverting control transistor TG1 of a second inverting control group. The inverting control unit 1021-2 includes: an inverting control transistor TR2 of a first inverting control group and an inverting control transistor TG2 of a second inverting control group. That is, the number of selection control line groups is the same as the number of inverting control units. The control timing of Embodiment 4 is similar to that of Embodiment 1 and can be understood by referring to it.

[0040] Example 5 Mux2:6 This application also provides a mux2:6 display panel, see details below. Figure 12 As shown. In this fifth embodiment, the multiplexing circuit 101 may include a multiplexing unit composed of selection transistors K11, K12, and K13 (referred to as multiplexing unit 1) and a multiplexing unit composed of selection transistors K21, K22, and K23 (referred to as multiplexing unit 2). The selection control line groups connected to multiplexing unit 1 and multiplexing unit 2 are different: selection transistors K11, K12, and K23 in multiplexing unit 1 are respectively connected to selection control lines DemuxR1, DemuxG1, and DemuxB1 (referred to as selection control line group 1), while selection transistors K21, K22, and K23 in multiplexing unit 2 are respectively connected to selection control lines DemuxR2, DemuxG2, and DemuxB2 (referred to as selection control line group 2). In this case, the error-proof charging circuit 102 includes two inverting control units 1021, as shown... Figure 11 As shown, it includes: an inverting control unit 1021-1 and an inverting control unit 1021-2. The inverting control unit 1021-1 includes: inverting control transistors TR1 and TR2 of a first inverting control group, inverting control transistors TG1 and TG2 of a second inverting control group, and inverting control transistors TB1 and TB2 of a third inverting control group. The inverting control unit 1021-2 includes: inverting control transistors TR3 and TR4 of a first inverting control group, inverting control transistors TG3 and TG4 of a second inverting control group, and inverting control transistors TB3 and TB4 of a third inverting control group. That is, the number of selected control line groups is the same as the number of inverting control units. The control timing of Embodiment 5 is similar to that of Embodiment 2 and can be understood by referring to it.

[0041] It should be noted that the multiplexing circuit provided in this application is not limited to the embodiments listed above, and can also be applied to multiplexing circuits with higher slicing.

[0042] The display panel provided in the embodiments of this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area. The display area includes multiple pixel columns; each pixel column is connected to at least one data line and includes multiple pixel units; the non-display area includes a multiplexing circuit and a fault-proof charging circuit, wherein; The multiplexing circuit includes at least one multiplexing unit, and the multiplexing unit includes a first selection transistor and a second selection transistor, wherein; The source and drain of the first selection transistor are connected between a data input line and a first data line, and the control electrode of the first selection transistor is connected to a first selection control line; the source and drain of the second selection transistor are connected between the data input line and a second data line, and the control electrode of the second selection transistor is connected to a second selection control line. The error-proof charging circuit includes an inverting control unit corresponding to the multiplexing unit. The inverting control unit includes: a first inverting control group and a second inverting control group, wherein the first inverting control group includes a first inverting transistor, and the second inverting control group includes a second inverting transistor. The source and drain of the first inverting transistor are connected between the second selection control line and the low-level power supply line, and the control electrode of the first inverting transistor is connected to the first selection control line; and the source and drain of the second inverting transistor are connected between the first selection control line and the low-level power supply line, and the control electrode of the second inverting transistor is connected to the second selection control line. The multiplexing unit is configured to respond to the first selection signal transmitted by the first selection control line and the second selection signal transmitted by the second selection control line being at an active level in sequence, so that the first selection transistor and the second selection transistor are turned on respectively, so as to connect the data input line with the first data line and the second data line in a time-division manner, and provide data signals for the corresponding pixel units; The inverting control unit is configured to control the first inverting transistor to turn on in response to the first selection signal being at an active level, so as to pull the level of the control electrode of the second selection transistor back to or maintain it at an inactive level; and to control the second inverting transistor to turn on in response to the second selection signal being at an active level, so as to pull the level of the control electrode of the first selection transistor back to or maintain it at an inactive level.

2. The display panel according to claim 1, characterized in that, The multiplexing unit further includes a third selection transistor, the source and drain of which are connected between the data input line and the third data line, and the control electrode of which is connected to the third selection control line. The first inverting control group further includes a third inverting transistor, the source and drain of which are connected between the third selection control line and the low-level power supply line, and the control electrode of which is connected to the first selection control line. The second inverting control group further includes a fourth inverting transistor, the source and drain of which are connected between the third selection control line and the low-level power supply line, and the control electrode of which is connected to the second selection control line. The inverting control unit further includes a third inverting control group, which includes a fifth inverting transistor and a sixth inverting transistor. The source and drain of the fifth inverting transistor are connected between the first selection control line and the low-level power supply line, and the control electrode of the fifth inverting transistor is connected to the third selection control line. The source and drain of the sixth inverting transistor are connected between the second selection control line and the low-level power supply line, and the control electrode of the sixth inverting transistor is connected to the third selection control line.

3. The display panel according to claim 2, characterized in that, The multiplexing unit further includes a fourth selection transistor, the source and drain of which are connected between the data input line and the fourth data line, and the control electrode of which is connected to the fourth selection control line. The first inverting control group further includes a seventh inverting transistor, the source and drain of which are connected between the fourth selection control line and the low-level power supply line, and the control electrode of which is connected to the first selection control line. The second inverting control group further includes an eighth inverting transistor, the source and drain of which are connected between the fourth selection control line and the low-level power supply line, and the control electrode of which is connected to the second selection control line. The third inverting control group further includes a ninth inverting transistor, the source and drain of which are connected between the fourth selection control line and the low-level power supply line, and the control electrode of which is connected to the third selection control line. The inverting control unit further includes: a fourth inverting control group; the fourth inverting control group includes a tenth inverting transistor, an eleventh inverting transistor, and a twelfth inverting transistor; wherein the control stages of the tenth inverting transistor, the eleventh inverting transistor, and the twelfth inverting transistor are all connected to the fourth selection control line, the source and drain of the tenth inverting transistor are connected between the first selection control line and the low-level power supply line; the source and drain of the eleventh inverting transistor are connected between the second selection control line and the low-level power supply line; and the source and drain of the twelfth inverting transistor are connected between the third selection control line and the low-level power supply line.

4. The display panel according to any one of claims 1 to 3, characterized in that, When the at least one multiplexing unit includes multiple multiplexing units, each of the multiple multiplexing units is connected to one of the data input lines; the multiple data input lines are provided by one or more source driver chips.

5. The display panel according to any one of claims 1 to 3, characterized in that, A selection control line connected to one of the multiplexing units is defined as a selection control line group; In this embodiment, each of the at least one multiplexing unit is connected to the selection control line in the same selection control line group, and the error-proof charging circuit includes one of the phase-inverting control units.

6. The display panel according to claim 5, characterized in that, The at least one multiplexing unit is connected to the selection control line in a plurality of different selection control line groups, and the error-proof charging circuit includes a plurality of the inverting control units, the number of which is equal to the number of the selection control line groups.

7. The display panel according to any one of claims 1 to 3, characterized in that, The transistors in the multiplexing unit are the same type of transistors as those in the inverting control unit.

8. The display panel according to claim 7, characterized in that, The transistor in the multiplexing unit and the transistor in the inverting control unit are both N-type thin-film transistors; the N-type thin-film transistors include high-mobility oxide semiconductor materials; the high-mobility oxide semiconductor materials are indium gallium zinc oxide semiconductor materials, indium zinc oxide semiconductor materials, or indium gallium zinc tin oxide semiconductor materials.

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