Single power embedded flash boot circuit

Abstract

The application discloses a single power supply embedded flash memory starting circuit, which comprises a single edge delay module, a NAND gate and a starting module.The single edge delay module delays the rising edge and the falling edge of an original input signal to form a first input signal and a second input signal, and outputs the first input signal and the second input signal to the first input of the NAND gate.The second input of the NAND gate is connected with the original input signal, and the output of the NAND gate is connected with the input of the starting module.The starting module is used for generating a bias signal, a clock signal and a reference voltage, and the clock signal is output to a power supply after being selected by a gating module, and the bias signal and the reference voltage are respectively output to the bias voltage end and the positive input end of a comparator.The power supply is used for supplying power for a band gap reference circuit.The band gap reference circuit generates a second bias signal and a second reference voltage, and outputs the second bias signal and the second reference voltage to the gating module and a relaxation oscillator.The relaxation oscillator generates a second clock signal and outputs the second clock signal to the gating module.The application can drive the BGR to generate a stable reference voltage, and the reference voltage is used for adjusting the potential generated by the starting circuit, so that the power supply can work to generate the voltage required by the embedded flash memory in a standby state.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a single-power-supply embedded flash memory boot circuit. Background Technology

[0002] Embedded flash memory is an important component of MCUs. Embedded flash memory operates in various modes, such as read, erase, program, standby, and deep standby. Generally, embedded flash memory enters standby mode after power-on. In standby mode, the high voltage generated by the charge pumps remains at the voltage level required for read mode.

[0003] Charge pumps typically utilize modulation circuits to obtain the required voltage value. Their working principle involves comparing the high voltage output from the charge pump, after voltage division, with a reference voltage. If the reference voltage is reached, the charge pump shuts off; otherwise, it turns on. The reference voltage is generally generated by a bandgap reference (BGR) circuit. However, with advancements in process technology and decreasing power supply voltages, especially in single-supply scenarios, conventional low-supply-voltage BGRs struggle to meet accuracy requirements. If embedded flash memory cannot obtain a stable reference voltage, it will be unable to generate the correct high voltage after startup, affecting the normal operation of the flash memory. Summary of the Invention

[0004] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] The technical problem to be solved by the present invention is to provide a single-supply embedded flash memory startup circuit that can drive the BGR to generate a stable reference voltage, adjust the potential generated by the startup circuit with the reference voltage, and enable the power supply to generate the voltage required for the embedded flash memory in standby mode.

[0006] To solve the above-mentioned technical problems, the present invention provides a single-power-supply embedded flash memory boot circuit, comprising: The single-sided delay module DELAY delays the rising and falling edges of the original input signal to form a first input signal and a second input signal, which are then output to the first input of the NAND gate. The NAND gate has its second input connected to the original input signal and its output connected to the STARTER input of the startup module. The STARTER module generates a bias signal VB, a clock signal CLK, and a reference voltage VREF. After being selected by the SWITCH module, the clock signal CLK is output to the power supply PUMP_V1P5, and the bias signal VB and the reference voltage VREF are output to the comparator bias voltage terminal and positive input terminal, respectively. The power supply PUMP_V1P5 supplies power to the bandgap reference circuit BGR. The bandgap reference circuit BGR generates a second bias signal VBB and a second reference voltage VREFB, which are output to the gating module SWITCH and the relaxation oscillator OSC. The relaxation oscillator OSC generates a second clock signal CLKB, which is output to the strobe module SWITCH.

[0007] Preferably, the single-power embedded flash memory startup circuit is further improved by using a single-sided delay module DELAY to delay the rising edge of the original input signal by 4µs to form a first input signal and to delay the falling edge of the original input signal by 1µs to form a second input signal.

[0008] Preferably, the single-supply embedded flash memory startup circuit is further improved such that when the first input signal arrives, the SWITCH selection module outputs a first bias signal VBA, a first clock signal CLKA, and a first reference voltage VREFA; When the second input signal arrives, the SWITCH strobe module outputs the second bias signal VBB, the second clock signal CLKB, and the second reference voltage VREFB.

[0009] Preferably, the single-supply embedded flash memory startup circuit is further improved, and the startup module STARTER includes two parts: the first part is used to generate a first bias signal VBA, and the second part is used to generate a first clock signal CLKA. The first part includes: the drain of the first PMOSP1 is connected to the drain of the first NMOSN1 through a series resistor, the source of the first PMOSP1 is input voltage, and the gate of the first PMOSP1 is connected to its drain to generate a first bias signal VBA. The gate of the first NMOS N1 is connected to the input signal; The second part includes: the gate of the third PMOSP3 is connected to the input signal, its source is connected to the input voltage, and its drain is connected to the source of the fourth PMOSP4, the source of the fifth PMOSP5, and the source of the sixth PMOSP6. The fourth PMOS P4 and the second NMOS N2 are connected in drain-drain series; the fifth PMOS P5 and the third NMOS N3 are connected in drain-drain series; the sixth PMOS P6 and the fourth NMOS N4 are connected in drain-drain series. The second NMOS source N2, the third NMOS source N3, and the fourth NMOS source N4 are grounded; The drains of the fourth PMOS P4, the fifth PMOS P5, and the sixth PMOS P6 are grounded through capacitors. The drain of the sixth PMOS P6 outputs a clock signal via an inverter.

[0010] Preferably, the single-power embedded flash memory boot circuit is further improved by comprising three identical SWITCH strobe circuits. Its input signal is a set of signals with opposite levels. When the input signal is high, it outputs the corresponding bias signal, clock signal and reference voltage according to the input signal state.

[0011] Preferably, the single-power embedded flash memory boot circuit is further improved such that each group of gating circuits includes: The drain of the fifth NMOS N5 is connected to the source of the seventh PMOS P7, and the source of the fifth NMOS N5 is connected to the drain of the seventh PMOS P7. The drain gate of the seventh PMOS P7 is connected to the gate of the sixth NMOS N6; The drain of the sixth NMOS N6 is connected to the source of the eighth PMOS P8, ​​and the source of the sixth NMOS N6 is connected to the drain of the eighth PMOS P8.

[0012] Preferably, the single-power embedded flash memory boot circuit is further improved, wherein the power supply PUMP_V1P5 is a cross-coupled charge pump.

[0013] Preferably, the single-supply embedded flash memory boot circuit is further improved, and the power supply PUMP_V1P5 includes: The seventh NMOS N7 has its source connected to the input node VIN, its gate connected to the first clock signal CK, and its drain connected to the drain of the eleventh PMOS P11. The eighth NMOS N8 has its source connected to the input node VIN, its gate connected to the second clock signal CKb, and its drain connected to the drain of the twelfth PMOS P12 and grounded through a capacitor. The eleventh PMOSP11 has its source connected to an N-well, its gate connected to the first clock signal CK, and its drain connected to the drain of the eleventh PMOSP11 and the gate of the twelfth PMOSP12. The twelfth PMOSP12 has its source connected to the N-well, its gate connected to the second clock signal CKb, and its drain connected to the gate of the eleventh PMOSP11 and the drain of the twelfth PMOSP12. The source terminals of PMOSP9 and PMOSP12 are connected to the output node VOUT.

[0014] Preferably, the single-power embedded flash memory boot circuit is further improved. The main design concept of this invention is that, upon power-on startup, the startup circuit generates a high voltage to drive the charge pump (BGR), causing the BGR to produce a stable reference voltage. This reference voltage then adjusts the potential generated by the startup circuit to achieve the preset driving voltage required by the BGR. After the reference voltage is generated, each charge pump starts working, generating the voltage value required for the embedded flash memory in standby mode. Attached Figure Description

[0015] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the overall architecture of the present invention.

[0016] Figure 2 This is a schematic diagram of the architecture of the STARTER priority embodiment of the present invention.

[0017] Figure 3 This is a schematic diagram of the architecture of the preferred embodiment of the SWITCH selection module of the present invention.

[0018] Figure 4 This is a schematic diagram of the preferred embodiment architecture of the power supply PUMP_V1P5 of the present invention.

[0019] Figure 5 This is a schematic diagram of the simulation results of the present invention. Figure 1 .

[0020] Figure 6 This is a schematic diagram of the simulation results of the present invention. Figure 2 . Detailed Implementation

[0021] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements.

[0022] First embodiment; refer to Figure 1 As shown, the present invention provides a single-power-supply embedded flash memory boot circuit, comprising: The single-sided delay module DELAY delays the rising and falling edges of the original input signal to form a first input signal and a second input signal, which are then output to the first input of the NAND gate. For example, the rising edge of the original input signal is delayed by 4µs to form the first input signal, and the falling edge of the original input signal is delayed by 1µs to form the second input signal. The NAND gate has its second input connected to the original input signal and its output connected to the STARTER input of the startup module. The STARTER module generates a bias signal VB, a clock signal CLK, and a reference voltage VREF. After being selected by the SWITCH module, the clock signal CLK is output to the power supply PUMP_V1P5, and the bias signal VB and the reference voltage VREF are output to the comparator bias voltage terminal and positive input terminal, respectively. The power supply PUMP_V1P5 supplies power to the bandgap reference circuit BGR. The bandgap reference circuit BGR generates a second bias signal VBB and a second reference voltage VREFB, which are output to the gating module SWITCH and the relaxation oscillator OSC. The relaxation oscillator OSC generates a second clock signal CLKB, which is output to the strobe module SWITCH. When the first input signal arrives, the SWITCH gating module outputs the first bias signal VBA, the first clock signal CLKA, and the first reference voltage VREFA. When the second input signal arrives, the SWITCH strobe module outputs the second bias signal VBB, the second clock signal CLKB, and the second reference voltage VREFB.

[0023] Furthermore, it should be understood that although the terms "first," "second," etc., may be used herein to describe different elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of exemplary embodiments according to the present invention, the first element, component, region, layer, or portion discussed below may also be referred to as the second element, component, region, layer, or portion.

[0024] Second embodiment; refer to Figure 2 As shown, the present invention provides a startup module STARTER that can be used in the first embodiment described above. The startup module STARTER includes two parts: a first part is used to generate a first bias signal VBA, and a second part is used to generate a first clock signal CLKA. The first part includes: the drain of the first PMOSP1 is connected to the drain of the first NMOSN1 through a series resistor, the source of the first PMOSP1 is input voltage, and the gate of the first PMOSP1 is connected to its drain to generate a first bias signal VBA. The first NMOS N1 gate is connected to the input signal ENSTART; The second part includes: the gate of the third PMOSP3 is connected to the input signal ENSTART, its source is connected to the input voltage, and its drain is connected to the source of the fourth PMOSP4, the source of the fifth PMOSP5, and the source of the sixth PMOSP6; The fourth PMOS P4 and the second NMOS N2 are connected in drain-drain series; the fifth PMOS P5 and the third NMOS N3 are connected in drain-drain series; the sixth PMOS P6 and the fourth NMOS N4 are connected in drain-drain series. The second NMOS source N2, the third NMOS source N3, and the fourth NMOS source N4 are grounded; The drains of the fourth PMOS P4, the fifth PMOS P5, and the sixth PMOS P6 are grounded through capacitors. The drain of the sixth PMOS P6 outputs a clock signal via an inverter.

[0025] Third embodiment; This invention provides a SWITCH selection module that can be used in the first embodiment described above. The SWITCH selection module consists of three sets of selection circuits with the same structure. Its input signal is a set of signals with opposite levels. When the input signal is high, it outputs a corresponding bias signal, clock signal and reference voltage according to the state of the input signal. refer to Figure 3 As shown, each group of gating circuits includes: The drain of the fifth NMOS N5 is connected to the source of the seventh PMOS P7, and the source of the fifth NMOS N5 is connected to the drain of the seventh PMOS P7. The drain gate of the seventh PMOS P7 is connected to the gate of the sixth NMOS N6; The drain of the sixth NMOS N6 is connected to the source of the eighth PMOS P8, ​​and the source of the sixth NMOS N6 is connected to the drain of the eighth PMOS P8. Among them, ENSTART and ENSTARTb are input signals, VBA, VBB, and VB are bias signals, and VREF, VREFA, and VREFB are reference voltages.

[0026] Fourth embodiment; refer to Figure 4 As shown, the present invention provides a power supply PUMP_V1P5 that can be used in the first embodiment described above, which employs a cross-coupled charge pump and includes: The seventh NMOS N7 has its source connected to the input node VIN, its gate connected to the first clock signal CK, and its drain connected to the drain of the eleventh PMOS P11. The eighth NMOS N8 has its source connected to the input node VIN, its gate connected to the second clock signal CKb, and its drain connected to the drain of the twelfth PMOS P12 and grounded through a capacitor. The eleventh PMOSP11 has its source connected to an N-well, its gate connected to the first clock signal CK, and its drain connected to the drain of the eleventh PMOSP11 and the gate of the twelfth PMOSP12. The twelfth PMOSP12 has its source connected to the N-well, its gate connected to the second clock signal CKb, and its drain connected to the gate of the eleventh PMOSP11 and the drain of the twelfth PMOSP12. The source terminals of PMOSP9 and PMOSP12 are connected to the output node VOUT.

[0027] refer to Figure 5 , Figure 6As shown, when the DPSTBb signal is pulled high, the circuit starts working. Due to the DELAY module, the ENSTART signal is high at this time. The STARTER module starts working, generating the bias signal VBA and the clock signal CLKA. After being selected by the SWITCH module, the outputs CLK=CLKA, VB=VBA, and VREF=VDD. These three signals are sent to PUMP_V1P5 and a comparator. The comparator controls the output of PUMP_V1P5 to be:

[0028] The power supply PUMP_V1P5 serves as the power input for the BGR, enabling the BGR to start working and generating a bias signal VBB and a reference voltage VREFB. VBB and VREFB are then transmitted to the OSC to generate a frequency-adjustable and stable clock signal CLKB.

[0029] After a certain delay, the ENSTART signal is pulled down by the DELAY module. At this time, the STARTER module stops working, and the SWITCH module outputs CLK=CLKB, VB=VBB, and VREF=VREFB, causing the power supply PUMP_V1P5 to drop to the set value.

[0030] At this point, the high-voltage pumps in the embedded flash memory begin to work, enter standby mode, and the startup is complete.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0032] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A single-supply embedded flash memory boot circuit, characterized in that, include: The single-sided delay module (DELAY) delays the rising and falling edges of the original input signal to form a first input signal and a second input signal, which are then output to the first input of the NAND gate. The NAND gate has its second input connected to the original input signal, and its output connected to the STARTER input, the OSC input, and the BGR input. The STARTER module generates a bias signal (VB), a clock signal (CLK), and a reference voltage (VREF). After being selected by the SWITCH module, the clock signal (CLK) is output to the power supply (PUMP_V1P5), and the bias signal (VB) and the reference voltage (VREF) are output to the bias voltage terminal and the positive input terminal of the comparator, respectively. The power supply (PUMP_V1P5) powers the bandgap reference circuit (BGR) and the negative input of the comparator. The bandgap reference circuit (BGR) generates a second bias signal (VBB) and a second reference voltage (VREFB) which are output to the swivel module (SWITCH) and the relaxation oscillator (OSC). The relaxation oscillator (OSC) generates a second clock signal (CLKB) which is output to the strobe module (SWITCH).

2. The single-power embedded flash memory boot circuit as described in claim 1, characterized in that: The single-sided delay module (DELAY) delays the rising edge of the original input signal by 4µs to form the first input signal, and delays the falling edge of the original input signal by 1µs to form the second input signal.

3. The single-power embedded flash memory boot circuit as described in claim 1, characterized in that: When the first input signal arrives, the strobe module (SWITCH) outputs the first bias signal (VBA), the first clock signal (CLKA), and the first reference voltage VREFA; When the second input signal arrives, the strobe module (SWITCH) outputs the second bias signal (VBB), the second clock signal (CLKB), and the second reference voltage (VREFB).

4. The single-power embedded flash memory boot circuit as described in claim 1, characterized in that, The startup module consists of two parts: the first part is used to generate the first bias signal (VBA), and the second part is used to generate the first clock signal (CLKA). The first part includes: the drain of the first PMOS (P1) is connected to the drain of the first NMOS (N1) through a series resistor, the source of the first PMOS (P1) is input voltage, and the gate of the first PMOS (P1) is connected to its drain to generate a first bias signal (VBA). The gate of the first NMOS (N1) is connected to the input signal; The second part includes: the gate of the third PMOS (P3) is connected to the input signal, its source is connected to the input voltage, and its drain is connected to the source of the fourth PMOS (P4), the source of the fifth PMOS (P5), and the source of the sixth PMOS (P6); The fourth PMOS (P4) and the second NMOS (N2) are connected in series with their drains in series; the fifth PMOS (P5) and the third NMOS (N3) are connected in series with their drains in series; and the sixth PMOS (P6) and the fourth NMOS (N4) are connected in series with their drains in series. The source of the second NMOS (N2), the source of the third NMOS (N3), and the source of the fourth NMOS (N4) are grounded; The drains of the fourth PMOS (P4), the fifth PMOS (P5), and the sixth PMOS (P6) are grounded through capacitors respectively; The drain of the sixth PMOS (P6) outputs a clock signal via an inverter.

5. The single-power embedded flash memory boot circuit as described in claim 1, characterized in that, The SWITCH module consists of three identical SWITCH circuits. Its input signals are a set of signals with opposite levels. When the input signal is high, it outputs the corresponding bias signal, clock signal and reference voltage according to the state of the input signal.

6. The single-supply embedded flash memory boot circuit as described in claim 5, characterized in that, Each gating circuit includes: The drain of the fifth NMOS (N5) is connected to the source of the seventh PMOS (P7), and the source of the fifth NMOS (N5) is connected to the drain of the seventh PMOS (P7). The drain and gate of the seventh PMOS (P7) are connected to the gate of the sixth NMOS (N6); The drain of the sixth NMOS (N6) is connected to the source of the eighth PMOS (P8), and the source of the sixth NMOS (N6) is connected to the drain of the eighth PMOS (P8).

7. The single-supply embedded flash memory boot circuit as described in claim 1, characterized in that: The power supply (PUMP_V1P5) is a cross-coupled charge pump.

8. The single-supply embedded flash memory boot circuit as described in claim 7, characterized in that, The power supply (PUMP_V1P5) includes: The seventh NMOS (N7) has its source connected to the input node (VIN), its gate connected to the first clock signal (CK), and its drain connected to the drain of the eleventh PMOS (P11). The eighth NMOS (N8) has its source connected to the input node (VIN), its gate connected to the second clock signal (CKb), and its drain connected to the drain of the twelfth PMOS (P12) and grounded through a capacitor. The eleventh PMOS (P11) has its source connected to an N-well, its gate connected to the first clock signal (CK), and its drain connected to the drain of the eleventh PMOS (P11) and the gate of the twelfth PMOS (P12). The twelfth PMOS (P12) has its source connected to an N-well, its gate connected to the second clock signal (CKb), and its drain connected to the gate of the eleventh PMOS (P11) and the drain of the twelfth PMOS (P12). The sources of the ninth PMOS (P9) and the twelfth PMOS (P12) are connected to the output node (VOUT).

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