A method of packaging a semiconductor chip

Abstract

The application discloses a packaging method of a semiconductor chip, and relates to the technical field of semiconductor packaging, which comprises the following steps: collecting data after bump preparation of the semiconductor chip to obtain a bump topography data set; cleaning after preparation of a substrate to obtain substrate surface data, and fusing the substrate surface data with the bump topography data set to generate a topography quality data set; establishing a chip prediction model, outputting a solder joint failure probability and optimized process parameters; turning over the chip, performing alignment operation to obtain an aligned chip and substrate assembly; passing through a reflow soldering furnace, performing optimized soldering parameters and forming uniform intermetallic compounds to obtain a soldered chip and substrate assembly; and processing the soldered chip and substrate assembly by using a dispensing machine and a molding press to obtain a packaged chip assembly. By establishing the chip prediction model, the application significantly reduces the solder joint failure rate, improves the adaptability of the process parameters, and avoids missing the failure solder joint.

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