Semiconductor structure and method for manufacturing semiconductor structure

Abstract

This application provides a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes: a substrate; the substrate includes a base and a conductive line layer formed on the surface of the substrate; wherein the conductive line layer includes at least two spaced conductive lines; an insulating layer is formed on the side of the conductive line layer away from the substrate; wherein at least two contact holes corresponding to the conductive lines and air gaps are formed in the insulating layer; the air gaps are formed by removing the remaining portion of the sacrificial layer formed by plasma etching; the remaining portion of the sacrificial layer is formed by adjusting the plasma etching direction using a Faraday cage. Through this application embodiment, the dielectric constant of the insulating layer is reduced, thereby reducing the signal transmission delay of the semiconductor device.

Description

Technical Field

[0001] The embodiments in this application relate to the field of semiconductor technology, specifically to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Technology

[0002] As semiconductor devices continue to evolve towards higher integration and higher performance, the parasitic capacitance effect in conductive interconnect structures has become a key factor restricting the performance improvement of semiconductor devices. Since the parasitic capacitance between conductors is positively correlated with the dielectric constant of the insulating material between conductors, in order to reduce the resistance-capacitance (RC) delay caused by the parasitic capacitance effect, advanced semiconductor processes typically combine single-damascene or dual-damascene processes with copper interconnect processes, and fill the spaces between conductors with low-dielectric-constant (Low-K) insulating material to reduce the parasitic capacitance of the conductive interconnect structure.

[0003] However, due to the inherent properties of materials, it is difficult to reduce the dielectric constant of existing low dielectric constant materials to an ideal level close to that of air, resulting in the signal transmission delay of semiconductor devices failing to meet the performance requirements of the devices. Summary of the Invention

[0004] In view of this, several embodiments of this application provide a semiconductor structure and a method for manufacturing the semiconductor structure to reduce the signal transmission delay of semiconductor devices.

[0005] In one aspect, an embodiment of this application provides a semiconductor structure comprising: a substrate; the substrate including a base and a conductive line layer formed on the surface of the base; wherein the conductive line layer includes at least two spaced conductive lines; an insulating layer formed on the side of the conductive line layer away from the base; wherein at least two contact holes corresponding to the conductive lines and air gaps located between adjacent contact holes are formed in the insulating layer; the air gaps are formed by removing the remaining portion of the sacrificial layer formed by plasma etching; the remaining portion of the sacrificial layer is formed by adjusting the plasma etching direction using a Faraday cage.

[0006] Optionally, the substrate further includes a dielectric layer formed on the surface of the conductive line layer away from the substrate; wherein the dielectric layer is made of silicon, carbon, and nitrogen.

[0007] In another aspect, one embodiment of this application provides a method for manufacturing a semiconductor structure, the method comprising: providing a substrate; the substrate including a substrate and a conductive line layer formed on the surface of the substrate; wherein the conductive line layer includes at least two spaced conductive lines; forming a sacrificial layer on the side of the conductive line layer away from the substrate; performing plasma etching on the sacrificial layer to form sacrificial layer apertures and sacrificial layer remainders; wherein, during the plasma etching of the sacrificial layer, the etching direction is adjusted by means of a Faraday cage; forming a transition insulating layer based on the sacrificial layer apertures; removing the sacrificial layer remainders; forming an insulating layer based on the transition insulating layer; wherein at least two contact holes corresponding to the conductive lines and air gaps located between adjacent contact holes are formed in the insulating layer.

[0008] Optionally, during the plasma etching process of the sacrificial layer, the Faraday cage is disposed on the side of the sacrificial layer away from the conductive circuit layer; the ions in the plasma move in a first direction before passing through the Faraday cage, and after passing through the Faraday cage, at least some of the ions change their movement direction to a second direction, and some of the ions change their movement direction to a third direction, and the second direction is different from the third direction.

[0009] Optionally, during the plasma etching process of the sacrificial layer, the opening direction of the sacrificial layer aperture is taken as the width direction, and the opening width of the sacrificial layer aperture along the width direction close to the conductive circuit layer first decreases and then increases.

[0010] Optionally, the step of forming a transition insulating layer based on the pores of the sacrificial layer includes: depositing an insulating material in the pores of the sacrificial layer using a vapor deposition process to form a transition insulating layer with a shape matching the pores of the sacrificial layer.

[0011] Optionally, the step of removing the remaining portion of the sacrificial layer includes: cleaning the remaining portion of the sacrificial layer with a solution containing hydrofluoric acid to create an air gap within the transition insulation layer.

[0012] Optionally, taking the distribution direction of the conductive lines as the width direction, the width of the air gap along the width direction first increases and then decreases, along the direction close to the conductive line layer.

[0013] Optionally, the step of forming an insulating layer based on the transition insulating layer includes: depositing an insulating material based on the transition insulating layer using a vapor deposition process to form an insulating material layer; wherein the air gap in the insulating material layer and the air gap in the transition insulating layer are the same air gap; etching the insulating material layer based on a contact hole mask corresponding to the conductive line to form at least two contact holes corresponding to the conductive line in the insulating material layer, thereby obtaining the insulating layer.

[0014] Optionally, the sacrificial layer is made of silicon oxide or silicon nitride.

[0015] In several embodiments provided in this application, an insulating layer containing contact holes and air gaps is formed on the side of a conductive line layer comprising at least two spaced conductive lines away from the substrate. The air gaps are formed by removing the remaining portion of the sacrificial layer, and the remaining portion of the sacrificial layer is formed by adjusting the plasma etching direction using a Faraday cage. Unexpected effects are achieved, such as increasing the porosity of the insulating layer by replacing part of the solid in the insulating layer with air gaps, making the equivalent dielectric constant of the insulating layer closer to the ideal level, thereby suppressing parasitic capacitance effects and reducing the signal transmission delay of semiconductor devices. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of a conductive interconnect structure provided for related technologies.

[0018] Figure 2 This is a schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this application.

[0019] Figure 3 A partial structural schematic diagram of the substrate provided in an embodiment of this application.

[0020] Figure 4 This is a schematic diagram of a sacrificial layer formed on the side of the conductive line layer away from the substrate, provided as an embodiment of this application.

[0021] Figure 5 This is a schematic diagram of plasma etching of the sacrificial layer using a Faraday cage, provided as an embodiment of this application.

[0022] Figure 6 This is a schematic diagram of the formation of sacrificial layer pores and sacrificial layer residue provided in an embodiment of this application.

[0023] Figure 7 This is a schematic diagram of the formation of a transition insulating layer provided in an embodiment of this application.

[0024] Figure 8 This is a schematic diagram of the removal of the remaining portion of the sacrificial layer provided in an embodiment of this application.

[0025] Figure 9 This is a schematic diagram of the formation of an insulating material layer provided in an embodiment of this application.

[0026] Figure 10 This is a schematic diagram of etching an insulating material layer based on a contact hole mask, provided as an embodiment of this application.

[0027] Figure 11 This is a schematic diagram of the formation of an insulating layer provided in an embodiment of this application.

[0028] Structural designation explanation

[0029] 100. Conductive interconnect structure; 101. Low dielectric constant material layer; 102. Metal line; 103. Nitride layer; 104. Mask layer; 105. Barrier layer; 106. Hole; 210. Conductive line layer; 211. Isolation section; 212. Conductive line; 220. Dielectric layer; 230. Sacrificial layer; 231. Remaining part of sacrificial layer; 232. Pore of sacrificial layer; 240. Faraday cage; 250. Insulating layer; 251. Transition insulating layer; 252. Insulating material deposition section; 253. Air gap; 260. Contact hole mask; 261. Contact hole. Detailed Implementation

[0030] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0031] The accompanying drawings provided in this application are only schematic illustrations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complex.

[0032] In the description of the embodiments of this application, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," "center," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of the stated features.

[0033] In conductive interconnect structures, parasitic capacitances may form between adjacent wires or between wires and the substrate due to proximity effects. These parasitic capacitances may interact with the wire resistance to produce resistive-capacitive delay, leading to signal transmission delay and performance degradation in semiconductor devices. See Equation 1. Equation 1 shows that the resistive-capacitive delay is proportional to both wire resistance and parasitic capacitance. Therefore, in related technologies, the resistive-capacitive delay of semiconductor devices is typically improved by reducing wire resistance and decreasing parasitic capacitance.

[0034] Formula 1

[0035] in, Indicates resistance-capacitance delay. Indicates the resistance of the wire. This represents parasitic capacitance.

[0036] Please see Figure 1 In related technologies, copper interconnect technology is typically used to form the conductive interconnect structure 100. Specifically, metallic copper (Cu) can be used instead of metal (Al) to fabricate the metal lines 102 to reduce the resistance of the wires. Insulating low-dielectric-constant material layers 101 are filled between different metal lines 102 within the same interconnect layer and between different interconnect layers to reduce parasitic capacitance. Nitride layers 103 are disposed between the low-dielectric-constant material layers 101 located at different positions within the conductive interconnect structure 100 to improve the mechanical strength and chemical stability of the semiconductor device. The low-dielectric-constant material layers 101 are then etched based on a mask layer 104 and a barrier layer 105 to form holes 106 for supporting contact structures. The mask layer 104 can be made of tetraethyl orthosilicate (TEOS), and the barrier layer 105 can be made of titanium nitride (TiN).

[0037] As the proximity effect works, the shorter the distance between adjacent metal lines 102 and the higher the dielectric constant of the low-dielectric-constant material layer 101, the larger the parasitic capacitance. As semiconductor process nodes shrink, the overall size of semiconductor devices gradually decreases, and the critical dimension requirement for the distance between adjacent metal lines 102 continuously diminishes. Therefore, in related technologies, reducing the dielectric constant of the insulating low-dielectric-constant material layer 101 is commonly used to reduce parasitic capacitance.

[0038] Researchers conducted experimental measurements on the dielectric constant K of the low dielectric constant materials provided in the related technology and found that the dielectric constant K of the low dielectric constant materials provided in the related technology is relatively large, and there is a significant difference from the dielectric constant of air under ideal conditions (K=1).

[0039] Further investigation into the reasons for the relatively high dielectric constant of the low-dielectric-constant materials provided in related technologies reveals that these materials are primarily formed by increasing the porosity of the insulating material. Specifically, organic modification of the insulating material can be performed, i.e., introducing organic groups, such as methyl groups (-CH3), into silicon oxynitride (SiON), which has high thermal stability, to form Si-C and Si-ON bonds. This increases the gaps between silicon oxynitride molecules, thereby increasing the material's porosity and reducing its dielectric constant. However, due to the limitations of the properties of silicon oxynitride, the dielectric constant of the low-dielectric-constant materials formed by the above methods is difficult to approach the ideal dielectric constant, resulting in the resistance-capacitance delay of semiconductor devices remaining at a high level.

[0040] Therefore, it is necessary to provide a method for manufacturing a semiconductor structure that can further increase the porosity of the organically modified insulating material.

[0041] Please see Figure 2 One embodiment of this application provides a method for manufacturing a semiconductor structure. The method may include steps S110, S120, S130, S140, S150, and S160.

[0042] S110: Provides a substrate.

[0043] Please see Figure 3 In this embodiment, the substrate may include a substrate (not shown) and a conductive line layer 210 formed on the surface of the substrate.

[0044] In this embodiment, the substrate can serve as the basis for forming the semiconductor structure. Specifically, the substrate can be composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. For example, the substrate can be made of materials such as silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), or silicon carbide (SiC). The substrate can be a single-layer structure or a multi-layer structure. In this embodiment, the substrate can be a structure wafer on which integrated circuit elements such as field-effect transistors have already been formed.

[0045] In this embodiment, the conductive line layer 210 can be used to realize electrical connections between semiconductor devices. Specifically, the conductive line layer 210 may include at least two spaced conductive lines 212 and an isolation portion 211 surrounding the conductive lines 212. At least two spaced wire trenches can be formed on the isolation material layer based on photolithography and etching processes, and metal material can be filled into the wire trenches to form the conductive lines 212. The remaining portion of the isolation material layer serves as the isolation portion 211 to achieve electrical isolation between adjacent conductive lines 212. To reduce the resistance-capacitance delay of the semiconductor device, the material of the conductive lines 212 can be copper, and the material of the isolation portion 211 can be organically modified silicon oxynitride or other low dielectric constant materials.

[0046] To enhance the mechanical strength of the semiconductor structure and provide protection for the conductive lines 212 during the subsequent formation of contact holes, in some embodiments, the substrate may further include a dielectric layer 220 formed on the surface of the conductive line layer 210 away from the substrate. Specifically, the dielectric layer 220 may be made of silicon carbon nitride (SiCN).

[0047] S120: A sacrificial layer is formed on the side of the conductive line layer away from the substrate.

[0048] Since the dielectric constant of insulating materials can be reduced by increasing their porosity, air gaps can be formed within the insulating material layer to overcome the material property limitations of the insulating materials provided by related technologies and further improve their porosity. However, the insulating materials provided by related technologies have low mechanical strength. If the layer structure formed by this insulating material is directly anisotropically etched using plasma etching, it may lead to the collapse of the layer structure, thereby reducing the production yield of semiconductor devices. Therefore, a sacrificial layer can be formed on the side of the conductive circuit layer away from the substrate using a material with higher mechanical strength. The sacrificial layer is then etched using plasma etching to form pores within it. Finally, an insulating material is used to replace the sacrificial layer material, thereby forming air gaps within the insulating layer.

[0049] Please see Figure 4In this embodiment, the sacrificial layer 230, after patterning, can be used as a template for forming air gaps in the insulating layer. Specifically, the sacrificial layer 230 can be selectively removed in subsequent processes, and its material can be silicon nitride (Si3N4) or silicon oxide (SiO2). The sacrificial layer 230 can be formed by chemical vapor deposition or atomic layer deposition.

[0050] S130: Plasma etching is performed on the sacrificial layer to form sacrificial layer pores and the remaining part of the sacrificial layer.

[0051] After the sacrificial layer is formed, plasma etching can be used to perform anisotropic etching on the sacrificial layer. During the plasma etching process, the etching direction can be adjusted by using a Faraday cage to reduce the etching process complexity of forming sacrificial layer pores of a specific shape within the sacrificial layer.

[0052] Please refer to the following: Figure 5 and Figure 6 Since the shape of the air gaps in the insulating layer is modeled after the shape of the sacrificial layer pores 232, in order to improve the porosity of the insulating layer material while maintaining the mechanical strength of the insulating layer, in this embodiment, during the plasma etching process of the sacrificial layer 230, the opening direction of the sacrificial layer pores 232 is taken as the width direction, and the opening width of the sacrificial layer pores 232 along the width direction can first decrease and then increase along the direction close to the conductive circuit layer. The minimum opening width of the sacrificial layer pores 232 along the width direction is greater than 0.

[0053] In this embodiment, the remaining portion 231 of the sacrificial layer can be a structure formed by the remaining material after the sacrificial layer 230 is plasma etched.

[0054] In this embodiment, the Faraday cage 240 can be a conductive shielding structure used to regulate the distribution of the plasma electric field. Specifically, during the plasma etching of the sacrificial layer 230, the Faraday cage 240 can be disposed on the side of the sacrificial layer 230 away from the conductive circuit layer. By adjusting the geometry and position of the Faraday cage 240, the ions in the plasma can have their bombardment direction changed under the action of the Faraday cage 240 before reaching the sacrificial layer 230. Specifically, the Faraday cage 240 can have at least two surfaces extending in different directions and forming the same or different angles with the surface of the sacrificial layer 230 away from the conductive circuit layer. In this case, based on these surfaces of the Faraday cage 240, ions moving in the same direction in the plasma can be adjusted to bombard at least two different directions, thereby controlling the directionality of plasma etching and improving the uniformity of plasma etching, thereby forming sacrificial layer apertures 232 in the sacrificial layer 230 with an opening width that first decreases and then increases along the direction close to the conductive circuit layer. For example, the Faraday cage 240 can be composed of at least two sub-Faraday cages shaped like triangular pyramids or triangular prisms. This application embodiment does not impose a specific limitation on the number of Faraday cages 240. The number of sacrificial layer pores 232 can correspond to the number of Faraday cages 240.

[0055] When the bombardment direction of ions in the plasma is changed by using the Faraday cage 240, the direction of motion of ions in the plasma before passing through the Faraday cage 240 can be the first direction. After passing through the Faraday cage 240, at least some ions in the plasma change their direction of motion to the second direction, and some ions change their direction of motion to the third direction. The second direction is different from the third direction.

[0056] S140: A transition insulating layer is formed based on the porosity of the sacrificial layer.

[0057] After the sacrificial layer pores are formed, insulating material can be filled into the sacrificial layer pores to form a transition insulating layer composed of multiple transition insulating structures.

[0058] Please see Figure 7In this embodiment, the step of forming a transition insulating layer based on the pores of the sacrificial layer may include: depositing insulating material in the pores 232 of the sacrificial layer using a vapor deposition process to form a transition insulating layer 251 with a shape matching the pores 232 of the sacrificial layer. Specifically, to simplify the process of depositing insulating material, a mask may not be used during the deposition of insulating material in the pores 232 of the sacrificial layer. Therefore, in addition to the formation of the transition insulating layer 251 in the pores 232 of the sacrificial layer, an insulating material deposition portion 252 may also be formed on the surface of the sacrificial layer 230 away from the conductive line layer. This insulating material deposition portion 252 can be removed later during the process of removing the remaining portion 231 of the sacrificial layer. The insulating material may be organically modified silicon oxynitride or other low dielectric constant materials.

[0059] S150: Remove the remaining parts of the sacrificial layer.

[0060] After the transition insulation layer is formed, the remaining part of the sacrificial layer can be washed away using a wet cleaning process, so that an air gap is formed between adjacent transition insulation structures.

[0061] Please refer to the following: Figure 7 and Figure 8 In this embodiment, the step of removing the remaining portion of the sacrificial layer may include: cleaning the remaining portion 231 of the sacrificial layer with a solution containing hydrofluoric acid (HF), thereby forming an air gap 253 within the transition insulating layer 251. Specifically, the selection ratio of the cleaning solution may differ depending on whether the material of the sacrificial layer 230 is silicon oxide or silicon nitride. For example, when the material of the sacrificial layer 230 is silicon nitride, the removal rate of silicon nitride by the cleaning solution can be increased by adding substances for buffering or for improving reactivity.

[0062] Since the shape of the air gap 253 in the transition insulation layer 251 matches the shape of the remaining portion 231 of the sacrificial layer located between adjacent transition insulation structures, in this embodiment, with the distribution direction of the conductive lines 212 as the width direction, the width of the air gap 253 first increases and then decreases along the direction close to the conductive line layer.

[0063] S160: An insulating layer is formed based on a transition insulating layer.

[0064] After removing the remaining portion of the sacrificial layer, an insulating layer corresponding to the conductive line layer can be formed based on the transition insulating layer.

[0065] Please refer to the following: Figures 9 to 11In this embodiment, the step of forming an insulating layer based on the transition insulating layer may include: depositing an insulating material based on the transition insulating layer 251 using a vapor deposition process to form an insulating material layer; etching the insulating material layer based on the contact hole mask 260 corresponding to the conductive line 212 to form at least two contact holes 261 corresponding to the conductive line 212 within the insulating material layer, thereby obtaining the insulating layer 250.

[0066] In this embodiment, the air gap 253 within the insulating material layer and the air gap 253 within the transition insulating layer are the same air gap. Specifically, an insulating material layer can be formed by depositing insulating material in the region corresponding to the conductive circuit layer 210 around the transition insulating layer using a vapor deposition process. To save process costs and simplify process steps, the type of insulating material and vapor deposition process parameters used in the formation of the insulating material layer can be the same as those used in the formation of the transition insulating layer.

[0067] In this embodiment, the contact hole mask 260 can be used to define the location of the contact hole 261 during the etching process. Specifically, to improve the etching accuracy of forming the contact hole 261, the contact hole mask 260 can be a multilayer structure. For example, the contact hole mask 260 may include a protective layer made of tetraethyl orthosilicate, a diffusion barrier layer made of titanium nitride, a photolithography sacrificial layer made of silicon oxynitride and silicon dioxide, an organic dielectric layer (ODL) made of an organic polymer, a spin-on hard mask bottom (SHB) layer made of an organic-inorganic hybrid material, and a photoresist (PR) layer made of photoresist. The contact hole mask 260 can be formed by sequentially depositing the above materials on the surface of the insulating material layer away from the conductive line layer 210.

[0068] In this embodiment, the contact hole 261 can provide a basis for the formation of subsequent contact structures. Specifically, the contact hole 261 can expose the conductive line 212.

[0069] To reduce the negative impact of the contact hole 261 formation process on the insulating material layer structure, and to simplify the formation process of the contact hole 261, in this embodiment, the contact hole 261 can be formed on the insulating material layer by etching based on the contact hole mask 260 using an all-in-one (AIO) etching process.

[0070] To reduce the damage to the shape of the contact hole 261 caused by the air gap 253, in this embodiment, the air gap 253 can be located between adjacent contact holes 261. That is, at least two contact holes 261 corresponding to the conductive line 212 and an air gap 253 located between adjacent contact holes 261 can be formed in the insulating layer 250.

[0071] In the above embodiments, a single damascene process is used to form the conductive lines and contact holes respectively. In some embodiments, during the process of forming the conductive lines and contact holes using a double damascene process, an air gap can be formed in the insulating layer by plasma etching of the sacrificial layer with a Faraday cage, followed by forming a transition insulating layer based on the remaining portion of the etched sacrificial layer, then removing the remaining portion of the sacrificial layer, and forming an insulating layer corresponding to the conductive line layer based on the transition insulating layer. This method increases the porosity of the insulating layer and reduces its dielectric constant.

[0072] Please continue reading. Figure 11 Another embodiment of this application provides a semiconductor structure that may include a substrate and an insulating layer 250. Specifically, the substrate may include a base and a conductive line layer 210 formed on the surface of the base. The conductive line layer 210 may include at least two spaced conductive lines 212. The insulating layer 250 may be formed on the side of the conductive line layer 210 away from the substrate, and at least two contact holes 261 corresponding to the conductive lines 212 and air gaps 253 located between adjacent contact holes 261 may be formed within the insulating layer 250. The air gaps 253 may be formed by removing the remaining portion of the sacrificial layer formed by plasma etching; the remaining portion of the sacrificial layer may be formed by adjusting the plasma etching direction using a Faraday cage.

[0073] To enhance the mechanical strength of the semiconductor structure, in this embodiment, the substrate may further include a dielectric layer 220 formed on the surface of the conductive line layer 210 away from the substrate. Specifically, the dielectric layer 220 may be made of silicon, carbon, or nitride.

[0074] For other technical effects of the semiconductor structure described in the above embodiments, please refer to other embodiments of this application for comparison and explanation, and they will not be repeated here.

[0075] In the semiconductor structure manufacturing method and semiconductor structure provided in the embodiments of this application, by forming an insulating layer containing contact holes and air gaps on the side away from the substrate of a conductive line layer including at least two spaced conductive lines, wherein the air gaps are formed by removing the remaining portion of the sacrificial layer and the remaining portion of the sacrificial layer is formed by adjusting the plasma etching direction using a Faraday cage, the unexpected effects achieved include: since air gaps are formed between the contact holes in the insulating layer, the air gaps replace part of the solid in the insulating layer, thereby increasing the porosity of the insulating layer, making the equivalent dielectric constant of the insulating layer closer to the ideal level, thereby reducing the resistance-capacitance delay of the semiconductor structure, and further reducing the signal transmission delay of the semiconductor device.

[0076] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of this application.

[0077] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0078] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0079] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0080] As should be understood from the several embodiments provided in this application, the disclosed semiconductor structure can be implemented in other ways. For example, the embodiments of the semiconductor structure described above are merely illustrative.

[0081] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; the substrate comprises a substrate and a conductive circuit layer formed on the surface of the substrate; wherein the conductive circuit layer comprises at least two spaced conductive circuits; an insulating layer formed on the side of the conductive circuit layer away from the substrate; wherein the insulating layer is formed with at least two contact holes corresponding to the conductive circuits and air gaps between adjacent contact holes; the air gaps are formed by first filling the sacrificial layer apertures formed by plasma etching of the sacrificial layer with an insulating material, and then removing the remaining part of the sacrificial layer formed by plasma etching of the sacrificial layer; the opening width of the sacrificial layer apertures first decreases and then increases along the direction close to the conductive circuit layer; the remaining part of the sacrificial layer is formed by adjusting the plasma etching direction with a Faraday cage.

2. The semiconductor structure of claim 1, wherein, The substrate further comprises: a dielectric layer formed on the surface of the side of the conductive circuit layer away from the substrate; wherein the material of the dielectric layer is silicon carbon nitride.

3. A method of manufacturing a semiconductor structure, characterized by, The manufacturing method of the semiconductor structure comprises: providing a substrate; the substrate comprises a substrate and a conductive circuit layer formed on the surface of the substrate; wherein the conductive circuit layer comprises at least two spaced conductive circuits; forming a sacrificial layer on the side of the conductive circuit layer away from the substrate; plasma etching the sacrificial layer to form sacrificial layer apertures and a remaining part of the sacrificial layer; wherein during the plasma etching of the sacrificial layer, the etching direction is adjusted by means of a Faraday cage; the opening width of the sacrificial layer apertures first decreases and then increases along the direction close to the conductive circuit layer; filling the sacrificial layer apertures with an insulating material to form a transition insulating layer; wherein the transition insulating layer is composed of multiple transition insulating structures; removing the remaining part of the sacrificial layer to form air gaps between adjacent transition insulating structures; forming an insulating layer based on the transition insulating layer; wherein the insulating layer is formed with at least two contact holes corresponding to the conductive circuits and the air gaps between adjacent contact holes.

4. The method of manufacturing a semiconductor structure according to claim 3, wherein During the plasma etching of the sacrificial layer, the Faraday cage is arranged on the side of the sacrificial layer away from the conductive circuit layer; the motion direction of ions in the plasma before passing through the Faraday cage is the first direction, and after passing through the Faraday cage, at least part of the ions changes the motion direction to the second direction, and part of the ions changes the motion direction to the third direction, and the second direction is different from the third direction.

5. The method of manufacturing a semiconductor structure according to claim 3, wherein The step of filling the sacrificial layer apertures with an insulating material to form a transition insulating layer comprises: depositing the insulating material in the sacrificial layer apertures by a vapor deposition process to form a transition insulating layer with a shape matching the sacrificial layer apertures.

6. The method of manufacturing a semiconductor structure according to claim 3, wherein The step of removing the remaining part of the sacrificial layer comprises: cleaning and removing the remaining part of the sacrificial layer with a solution containing hydrofluoric acid to form air gaps in the transition insulating layer.

7. The method of manufacturing a semiconductor structure according to claim 6, wherein Taking the distribution direction of the conductive circuits as the width direction, along the direction close to the conductive circuit layer, the width of the air gaps along the width direction first increases and then decreases.

8. The method of manufacturing a semiconductor structure according to claim 6, wherein The step of forming an insulating layer based on the transition insulating layer comprises: depositing an insulating material based on the transition insulating layer by using a vapor deposition process to form an insulating material layer, wherein the air gap in the insulating material layer is the same as the air gap in the transition insulating layer; etching the insulating material layer based on a contact hole mask corresponding to the conductive circuit to form at least two contact holes corresponding to the conductive circuit in the insulating material layer to obtain the insulating layer.

9. The method of manufacturing a semiconductor structure according to claim 3, wherein The material of the sacrificial layer is silicon oxide or silicon nitride.

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