A robust bidirectional stacked electrostatic discharge protection circuit

Abstract

The application provides a robust bidirectional stacked electrostatic protection circuit, which comprises a bidirectional stacked electrostatic protection module and a floating charge discharge module. The bidirectional stacked electrostatic protection module contains at least one floating node, which can accumulate residual charge during normal operation of the circuit or electrical characteristic test characterization. The floating charge discharge module is composed of a state control module and a charge discharge module. The state control module monitors the potential state of the floating node in real time and generates a control signal. The charge discharge module is turned on in response to the control signal to discharge the accumulated charge of the floating node. The floating charge discharge module includes a MOS transistor, which is connected to a first port through the state control module, and the source of the MOS transistor is connected to the floating node, and the drain is connected to a second port. The application can timely discharge the accumulated charge on the floating node inside the series high-voltage ESD protection circuit.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection technology, and specifically to a robust bidirectional stacked ESD protection circuit. Background Technology

[0002] During the use of electronic devices, static electricity can easily be generated on the human body, clothing, and device surfaces due to friction, contact separation, and other reasons. When static electricity accumulates to a certain level, it will cause electrostatic discharge, releasing high-energy charges. This electrostatic discharge can cause serious damage to sensitive components such as integrated circuits inside electronic devices, leading to decreased device performance or even complete failure.

[0003] In some electronic devices, signal swings at certain ports may exhibit both positive and negative voltages simultaneously. For these ports, bidirectional ESD protection circuitry is required: bidirectional voltage blocking capability during normal chip operation, and bidirectional electrostatic discharge capability in the event of an ESD event. In practical ESD protection engineering, bidirectional ESD protection is achieved by connecting two unidirectional ESD devices in series, either head-to-head or tail-to-tail. In this case, to provide effective ESD protection, the clamping voltage after the ESD circuit is turned on needs to be monitored; typically, it must not exceed the failure voltage of the protected circuit under a specific ESD excitation level.

[0004] Existing bidirectional stacked ESD circuits, such as Figure 1(a)-Figure 1(c) As shown, for bidirectional I / O or power ports, a common ESD protection circuit strategy is to connect Zener diodes, BJTs (bipolar junction transistors), or MOSFETs in series "head-to-head" or "tail-to-tail". In this case, the internal node Ax is floating, where x = 1, 2, 3. Resistors R1 and R2 are used to limit the base current, ensuring the transistor conducts under appropriate conditions; resistors R3 and R4 are used to limit the gate current, ensuring the MOSFET conducts under appropriate conditions.

[0005] However, for chip ports employing the aforementioned bidirectional ESD circuitry, the actual ESD protection level of the port sometimes falls far short of its design value. Research indicates that this is typically due to the charge storage behavior of the internal floating nodes within the bidirectional ESD circuitry. When an ESD event occurs, the non-zero potential caused by these stored charges has a certain probability of being superimposed on the IV characteristic curve of the ESD protection device, thus drastically deteriorating its clamping voltage characteristics and ultimately significantly reducing the port's ESD protection level.

[0006] Figure 2(a) shows the influence of the ESD circuit's IV characteristics on the floating potential of Ax. The applied bias voltage represents the port voltage or the pre-charge phenomenon during ESD testing. As shown in Figure 2(a), under certain circumstances, when the applied bias voltage disappears, the Ax potential cannot be discharged to zero. As shown in Figure 2(c), when the Ax potential is not zero, the IV curve of the ESD circuit (two red lines) will drift to the right along the X-axis, thus significantly deteriorating the electrostatic protection effect of the ESD circuit. In other words, the ESD robustness will be severely affected by the Ax potential.

[0007] Therefore, a bidirectional electrostatic protection solution is needed to address the interference of non-zero potential on the internal floating nodes on the ESD protection effect. Summary of the Invention

[0008] To address the problems in the prior art, this invention provides a robust bidirectional stacked electrostatic discharge protection circuit.

[0009] This invention relates to a robust bidirectional stacked electrostatic discharge (ESD) protection circuit, comprising a bidirectional stacked ESD protection module and a floating charge discharge module, wherein...

[0010] Bidirectional stacked electrostatic protection module: one end is connected to the first port and the other end is connected to the second port. The bidirectional stacked electrostatic protection module includes at least one floating node. The floating node can accumulate residual charge during normal circuit operation or electrical characteristic testing and characterization.

[0011] The floating charge discharge module consists of a state control module and a charge discharge module. The state control module monitors the potential state of the floating node in real time and generates a control signal; the charge discharge module responds to the control signal and conducts to discharge the charge accumulated in the floating node.

[0012] The floating charge discharge module includes a discharge tube. The control end of the discharge tube is connected to the first port through the state control module. The input end of the discharge tube is connected to the floating node, and the output end is connected to the second port.

[0013] Furthermore, the state control module is a control path connecting the first port and the control terminal of the bleed tube, and the bleed tube is a device with switching characteristics.

[0014] Furthermore, the discharge tube is a MOS transistor, and the floating charge discharge module also includes a first resistor and a first diode. The first resistor is disposed on the control path, the first diode is disposed between the drain of the MOS transistor and the second port, the first transistor is disposed in the opposite direction to the body diode of the MOS transistor, and the first resistor is disposed between the gate of the MOS transistor and the first port.

[0015] Furthermore, the state control module is a logic control circuit, with its first input terminal connected to a first port, its second input terminal connected to a second port, and its output terminal connected to the gate of a MOS transistor.

[0016] Furthermore, the MOS transistor is a PMOS transistor, with its source connected to a floating node and its drain connected to the second port. The state control module is a MAX(A,B) logic circuit, with its first input terminal connected to the first port and a voltage value of A, its second input terminal connected to the second port and a voltage value of B, and its output terminal connected to the gate of the PMOS transistor.

[0017] Furthermore, the MAX(A,B) logic circuit includes a first PMOS transistor and a second PMOS transistor. The source of the first PMOS transistor is connected to a first port, and its gate is connected to a second port. The source of the second PMOS transistor is connected to a second port, and its gate is connected to a first port. The drains of the first PMOS transistor and the drains of the second PMOS transistor are connected together and serve as the output terminal of the MAX(A,B) logic circuit.

[0018] Furthermore, the MOS transistor is an NMOS transistor, with its source connected to a floating node and its drain connected to the second port. The state control module is a MIN(C,D) logic circuit, with its first input terminal connected to the first port and a voltage value of C, its second input terminal connected to the second port and a voltage value of D, and its output terminal connected to the gate of the NMOS transistor.

[0019] Furthermore, the MIN(C,D) logic circuit includes a first NMOS transistor and a second NMOS transistor. The source of the first NMOS transistor is connected to a first port, and its gate is connected to a second port. The source of the second NMOS transistor is connected to a second port, and its gate is connected to a first port. The drains of the first NMOS transistor and the drains of the second NMOS transistor are connected together and serve as the output terminal of the MIN(C,D) logic circuit.

[0020] Furthermore, the bidirectional stacked electrostatic protection module adopts a multi-level stacked structure. The bidirectional stacked electrostatic protection module includes a first electrostatic protection unit and a second electrostatic protection unit. The first electrostatic protection unit and the second electrostatic protection unit are connected in series and arranged in opposite directions. The floating node exists between the first electrostatic protection unit and the second electrostatic protection unit. Both the first electrostatic protection unit and the second electrostatic protection unit are provided with N electrostatic protection devices arranged in the same direction.

[0021] or,

[0022] The bidirectional stacked electrostatic discharge (ESD) protection module includes two stacked pairs of ESD protection devices. Each pair of ESD protection devices includes a first ESD protection device and a second ESD protection device, which are arranged in opposite directions.

[0023] When the bidirectional stacked electrostatic protection module is composed of two or more electrostatic protection devices stacked together, the floating node includes a first floating node between the first and second electrostatic protection devices arranged tail to tail, and a second floating node between the first and second electrostatic protection devices arranged head to head.

[0024] The floating charge discharge module includes a first MOS transistor and a second MOS transistor. The state control module includes a first state control unit for controlling the first MOS transistor and a second control unit for controlling the second MOS transistor. Multiple first floating nodes are each connected to the source of the first MOS transistor via a diode, and the diodes connected to the first floating nodes are oriented in the opposite direction to the body diodes of the first MOS transistor. Similarly, multiple second floating nodes are each connected to the source of the second MOS transistor via a diode, and the diodes connected to the second floating nodes are oriented in the opposite direction to the body diodes of the second MOS transistor.

[0025] The first MOS transistor is a PMOS transistor, and the second MOS transistor is an NMOS transistor.

[0026] Furthermore, the floating charge discharge module is also provided with an overcurrent protection structure, which is a rectifier diode connected in series between the drain of the MOS transistor and the second port, or the overcurrent protection structure is to keep the substrate of the MOS transistor floating.

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows: In order to prevent the charge accumulated on the floating nodes from affecting ESD devices and to achieve highly robust ESD protection, especially for series-type bidirectional ESD protection circuits or various stacked bidirectional ESD protection circuits, the present invention introduces an intelligent "floating charge discharge module" through circuit structure optimization. This module is composed of switching devices. By accurately monitoring the working status of the "bidirectional stacked electrostatic protection circuit", it can effectively and timely discharge the accumulated charge on the floating nodes inside the circuit, avoiding interference of the non-zero potential on the internal floating nodes on the ESD clamping voltage, thereby realizing the intrinsic ESD protection capability of the protection circuit. Attached Figure Description

[0028] To more clearly illustrate the solutions in this invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0029] Figure 1(a) is a circuit schematic diagram of an embodiment of an existing bidirectional stacked ESD circuit;

[0030] Figure 1(b) is a circuit schematic diagram of an existing bidirectional stacked ESD circuit embodiment two;

[0031] Figure 1(c) is a circuit schematic diagram of an existing bidirectional stacked ESD circuit embodiment three;

[0032] Figures 2(a) and 2(b) are schematic diagrams showing the influence of the floating potential of Ax on the IV characteristics of the existing bidirectional stacked ESD circuit.

[0033] Figure 2(c) is a schematic diagram of the rightward drift of the IV curve of the existing bidirectional stacked ESD circuit;

[0034] Figure 3 This is a schematic diagram of the robust bidirectional stacked electrostatic discharge protection circuit structure of the present invention;

[0035] Figure 4 The circuit schematics are for the first and second embodiments of the present invention.

[0036] Figure 5 These are circuit schematics for the third and fourth embodiments of the present invention;

[0037] Figure 6 These are circuit schematics for the fifth and sixth embodiments of the present invention;

[0038] Figure 7 These are circuit schematics for the seventh and eighth embodiments of the present invention;

[0039] Figure 8 These are circuit schematics of the ninth and tenth embodiments of the present invention;

[0040] Figure 9 The circuit schematics are for the eleventh and twelfth embodiments of the present invention.

[0041] Figure 10 These are circuit schematics for the thirteenth and fourteenth embodiments of the present invention. Detailed Implementation

[0042] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains; the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects, not to describe a particular order.

[0043] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment to other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this invention can be combined with other embodiments.

[0044] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0045] like Figure 3 As shown, the robust bidirectional stacked electrostatic discharge (ESD) protection circuit of the present invention includes a bidirectional stacked ESD protection module and a floating charge discharge module, wherein,

[0046] Bidirectional stacked electrostatic protection module: one end is connected to the first port and the other end is connected to the second port. The bidirectional stacked electrostatic protection module contains K floating nodes, where K is a positive integer. The floating nodes can accumulate residual charge during normal circuit operation or electrical characteristic testing and characterization.

[0047] The floating charge discharge module consists of a state control module and a charge discharge module. The state control module monitors the potential state of the floating node in real time and generates a control signal. The charge discharge module responds to the control signal and turns on to discharge the charge accumulated in the floating node correctly and in a timely manner.

[0048] like Figures 4-10 As shown, the floating charge discharge module includes a discharge tube. The control terminal of the discharge tube is connected to the first port through the state control module. The input terminal of the discharge tube is connected to the floating node, and the output terminal is connected to the second port. In this invention, any device with switching characteristics can be used as a discharge tube, including but not limited to MOS transistors, electronic switches, etc.

[0049] As an embodiment of the present invention, this example uses a MOS transistor. The MOS transistor is connected to the first port through the state control module. The source of the MOS transistor is connected to the floating node, and the drain is connected to the second port.

[0050] The electrostatic discharge (ESD) protection devices in this example bidirectional stacked ESD protection module can be ESD diodes, Zener diodes, MOSFETs, BJTs (bipolar junction transistors), thyristors, etc. These ESD protection devices can be mixed and stacked, with at least one stack level. This invention is not limited to ESD protection; it can also be used for surge protection and protection against other electrostatic discharge models.

[0051] The following description is based on a specific embodiment. In this example, an ESD diode is used as the electrostatic protection device. The various reference numerals in the embodiments are explained as follows:

[0052] ● 100, 120, 200, 220, 300, 320, 400, 420, 500, 520, 600, 620, 700, 720 usually represent port 1;

[0053] ● 101, 121, 201, 221, 301, 321, 401, 421, 501, 521, 601, 621, 701, 721 usually represent port 2;

[0054] ●102, 103, 122, 123, 202, 203, 222, 223, 302, 303, 322, 323, 402, 403, 422 ,423,502,503,522,523,602,603,622,623,702-1,702-N,703-1,703-N,

[0055] 722-1, 722-2, 722-N, 723-1, 723-2, and 723-N typically represent ESD diodes.

[0056] ●104, 124, 204, 224, 304, 324, 404, 424, 504, 524, 604, 624, 704, 724-1

[0057] 724-2, 724-M, and 724-N typically represent floating nodes in bidirectional ESD circuits;

[0058] ● 105, 125, 205, 225, 405, 505, 507, 508, 525, 527, 528, 705, and 725 typically represent P-type MOS transistors (PMOS transistors for short).

[0059] ● 305, 325, 425, 605, 607, 608, 625, 627, 628, and 727 typically represent N-type MOS transistors (NMOS transistors for short).

[0060] ●206, 226, 306, 326, 506, 526, 606, 626, 726-1, 726-2, 726-3, and 726-4 typically represent rectifier diodes;

[0061] ●207, 227, 307, and 327 typically represent resistors;

[0062] ● 509, 529, 609, and 629 typically represent the output nodes of logic circuits;

[0063] ● 110, 130, 210, 230, 310, 330, 410, 430, 510, 530, 610, 630, 710, and 730 typically represent bidirectional ESD paths;

[0064] • 111, 131, 211, 231, 311, 331, 411, 431, 511, 531, 611, 631, 711, 731-1, 731-2 typically represent floating charge discharge paths;

[0065] • 112, 132, 212, 232, 312, 332, 412, 432, 512, 532, 612, 632, 712, 732-1, 732-2 typically represent the gate control path of the bleeder.

[0066] • A, B, C, and D are typically the inputs to a logic circuit;

[0067] • E and F are usually the outputs of logic circuits.

[0068] like Figure 4 As shown, in the first and second embodiments of the present invention, the state control module in this example is a metal connection line connecting the first port and the gate of the MOS transistor.

[0069] like Figure 4As shown in Figure (a), in the first embodiment of the present invention, three paths are included: a bidirectional ESD path 110 consisting of the bidirectional stacked electrostatic protection module, a floating charge discharge path 111 consisting of the floating charge discharge module, and a discharge tube gate control path 112 consisting of the state control module. Specifically, the bidirectional ESD path 110 is composed of two ESD diodes (102, 103) connected back-to-back in series; the floating charge discharge path 111 is a PMOS transistor 105; and the discharge tube gate control path 112 is connected to port 100.

[0070] The working principle of this invention is as follows:

[0071] (1) When a forward bias is applied to port 100, ESD diode 102 is forward biased and conducts while ESD diode 103 is reverse biased and cut off. At this time, the potential of the floating node 104 in the middle is approximately the applied forward bias - 0.7V (0.7V is the diode forward voltage drop). Simultaneously, the gate voltage VG of PMOS transistor 105 is equal to the voltage V100 of port 100, and the source voltage VS is equal to the voltage V104 of floating node 104. Since VG > VS, PMOS transistor 105 is in the off state. Therefore, the floating charge discharge path 111 will not be turned on under normal chip operating conditions, avoiding any impact on the operation of the internal circuitry and the ESD circuitry.

[0072] (2) After the forward bias is completed, both ESD diodes 102 and 103 are in the reverse bias cutoff state and cannot discharge the charge accumulated in the floating node 104. Therefore, the floating node 104 maintains a high potential (relative to ground). At this time, the potential of port 100 returns to zero, and the source voltage of PMOS transistor 105 is higher than its gate voltage, causing transistor 105 to conduct. The charge in the intermediate node 104 is then discharged to the ground port 101 through the conducting PMOS transistor 105.

[0073] (3) When a negative bias is applied to port 100, the ESD diode 103 is forward biased and conducts, so the potential of the floating node 104 is approximately -0.7V (relative to ground). After the negative bias ends, since the voltage across the capacitor cannot change abruptly, the potential of the intermediate node 104 is raised. At this time, the PMOS transistor 105 is turned on to discharge the charge accumulated in node 104.

[0074] like Figure 4 As shown in Figure (b), this is a second embodiment of the present invention. The main difference between this embodiment and the first embodiment is that the gate of the PMOS transistor 125 is connected to port 121, while the drain is connected to port 120. The charge discharge working principle of this embodiment is similar to that of the first embodiment, and will not be described again here.

[0075] like Figure 5As shown, the third and fourth embodiments of the present invention are structural improvements based on the first and second embodiments, wherein (a) is the third embodiment of the present invention and (b) is the fourth embodiment of the present invention.

[0076] The main improvements of the third and fourth embodiments of the present invention are as follows:

[0077] (1) A rectifier diode 206 and a rectifier diode 226 are added to the floating charge discharge paths 211 and 231, respectively. The anodes of the diodes 206 and 226 are connected to the drain terminals of PMOS transistors 205 and 225, respectively, and the cathodes are connected to ports 201 and 230, respectively. The purpose of the rectifier diodes 206 and 226 is to prevent the channel and body diodes of PMOS transistors 205 and 225 from turning on during negative bias, so as to avoid the PMOS transistors from burning out due to excessive current.

[0078] (2) Add a resistor 207 and a resistor 227 to the gate control paths 212 and 232 respectively. The function of the resistor is to limit the current on the gate control path and protect the gate of the MOS transistor.

[0079] like Figure 6 As shown, the fifth and sixth embodiments of the present invention are structural improvements based on the third and fourth embodiments, wherein (a) is the fifth embodiment of the present invention and (b) is the sixth embodiment of the present invention. The main changes in the two embodiments include:

[0080] ESD diode series connection method: changed from "head to head" to "tail to tail" (i.e., cathode connected); discharge tube type: the MOS transistors in floating charge discharge paths 311 and 331 are replaced with N-type MOS transistors.

[0081] by Figure 6 The fifth embodiment shown in Figure (a) is used as an example for explanation: After the positive or negative bias of port 300 ends, the potential of intermediate node 304 is negative (relative to ground); at this time, the gate voltage of NMOS transistor 305 is 0V (ground), while the source voltage is the negative potential of intermediate node 304; since the gate voltage is higher than the source voltage and satisfies VGS > Vth (threshold voltage), NMOS transistor 305 is turned on; the charge accumulated in floating node 304 is discharged to ground port 301 through the turned-on NMOS transistor 305.

[0082] like Figures 7-10As shown, embodiments seven through fourteen of the present invention further optimize the gate control circuit of the MOS transistor. The state control module is a logic control circuit, with its first input terminal connected to a first port, its second input terminal connected to a second port, and its output terminal connected to the gate of the MOS transistor. The logic control circuit can be a comparator, a comparison circuit, etc.

[0083] like Figure 7 As shown in Figure (a), the logic control circuit in this example introduces a maximum value comparator circuit (also called a MAX logic circuit), which compares the voltages across ports 400 and 401 and outputs the maximum value to node E. Node E is connected to the gate of PMOS transistor 405, which can control the conduction state of the PMOS transistor.

[0084] The MOS transistor is a PMOS transistor, with its source connected to a floating node and its drain connected to the second port. The state control module is a MAX(A,B) logic circuit, with its first input connected to port 400 and a voltage value of A, its second input connected to port 401 and a voltage value of B, and its output connected to the gate of the PMOS transistor.

[0085] The truth table for the MAX(A,B) logic circuit in this example is shown in Table 1:

[0086] Table 1 Truth Table for MAX(A,B) Logic Circuit

[0087]

[0088] Regardless of whether the bias applied to port 400 is positive or negative, the output node E of this MAX(A,B) logic circuit is always at a high potential. However, the source voltage of PMOS transistor 405 is less than its gate voltage, so PMOS transistor 405 remains off during voltage bias. The output node E has a zero potential if and only if both ports 400 and 401 are at a low potential (i.e., after the positive or negative bias has ended). However, at this time, the floating node 404 remains at a high potential due to charge accumulation, so PMOS transistor 405 turns on and discharges the floating charge of the intermediate floating node.

[0089] like Figure 7As shown in Figure (b), in the eighth embodiment of the present invention, the MOS transistor in this embodiment is an NMOS transistor. The source of the NMOS transistor is connected to a floating node, and the drain is connected to the second port. The state control module is a MIN(C,D) logic circuit. The first input terminal of the MIN(C,D) logic circuit is connected to the first port with a voltage value of C. The second input terminal of the MIN(C,D) logic circuit is connected to the second port with a voltage value of D. The output terminal of the MIN(C,D) logic circuit is connected to the gate of the NMOS transistor.

[0090] The truth table for the MIN(C,D) logic circuit in this example is shown in Table 2:

[0091] Table 2 Truth Table for MIN(C,D) Logic Circuit

[0092] "0” "1” "0” "1” "0” "0” "1” "1” "1”

[0093] This example uses a minimum comparator (MIN) circuit to control the gate of NMOS transistor 425, suitable for a stacked ESD diode structure connected in a tail-to-tail configuration. During forward or negative bias, the output node F is at a low potential, so NMOS transistor 425 remains off. When the bias ends, the floating node 424 induces a negative potential (relative to ground) due to the accumulation of negative charge. Since the comparator circuit output node F is at zero potential (high potential relative to the intermediate node 424), NMOS transistor 425 turns on to discharge the negative charge.

[0094] like Figure 8 As shown in Figure (a), this ninth embodiment of the present invention has the following main improvements compared to the seventh embodiment:

[0095] The MAX logic circuit in the seventh embodiment is implemented using two PMOS transistors 507 and 508. The source of PMOS transistor 507 is connected to port 500, and its gate is connected to port 501; the source of PMOS transistor 508 is connected to port 501, and its gate is connected to port 500. The drains of the two PMOS transistors are connected together and serve as the output port of the MAX logic circuit. They are connected to the gate of PMOS transistor 505 to control the conduction state of PMOS transistor 505.

[0096] The working principle of this embodiment is as follows:

[0097] When a forward pulse is applied to the port 500, the PMOS transistor 507 is turned on (VS>VG), while the PMOS transistor 508 is turned off (VS<VG). Therefore, the output node 509 of the logic circuit is at a high level, and thus the PMOS transistor 505 is turned off. After the forward pulse at the port 500 ends, both the port 500 and the port 501 are at zero potential, and the output node of the logic circuit is also at zero potential. The floating node 504 maintains a high potential due to charge accumulation, so the PMOS transistor 505 is turned on (VS>VG) and discharges the charge. The mechanism of the negative pulse is similar to that in the forward pulse process, so it will not be repeated here.

[0098] Preferably, in this example, a rectifier diode 506 is added in the floating charge discharge path 511 to prevent the body diode of the PMOS transistor 505 from being turned on, causing overcurrent and burning out. When the substrate of the PMOS transistor 505 is floating, the rectifier diode 506 can be omitted. In addition, in this embodiment, the substrates of the two PMOS transistors (507 and 508) constituting the logic circuit are kept floating to avoid the interference of the body diode on the circuit function.

[0099] As Figure 8 shown in figure (b) of , as the tenth embodiment of the present invention, compared with the ninth embodiment, in this embodiment, the drain of the PMOS transistor 525 is connected to the port 520 through a rectifier diode 526. The principle of the tenth embodiment is the same as that of the ninth embodiment, so it will not be repeated here.

[0100] Figure 9 Figures (a) and (b) of are schematic circuit diagrams of the eleventh embodiment and the twelfth embodiment of the present invention respectively. Taking the eleventh embodiment as an example for description, compared with the eighth embodiment, the main improvements of this embodiment are as follows:

[0101] The MIN logic circuit in the eighth embodiment is implemented by two NMOS transistors 607 and 608. The source of the NMOS transistor 607 is connected to the port 600, and the gate thereof is connected to the port 601; the source of the NMOS transistor 608 is connected to the port 601, and the gate thereof is connected to the port 600. The drains of the two NMOS transistors are connected to the gate of the NMOS transistor 605 for controlling the on-state thereof.

[0102] The working principle of this embodiment is:

[0103] When a positive pulse is applied to the port 600, the NMOS transistor 607 is turned off (VG<VS) and the NMOS transistor 608 is turned on (VG>VS. Therefore, the logic output node 609 is at zero potential, and the NMOS transistor 605 is turned off. After the positive pulse ends, both the port 600 and the port 601 are at zero potential, and the logic output node is also at zero potential. The floating node maintains a negative potential (relative to ground) due to charge accumulation, and at this time the NMOS transistor 605 is turned on to discharge the charge. The mechanism of the negative pulse process is similar to that of the positive pulse process, so it will not be repeated here.

[0104] Preferably, in this example, a rectifier diode 606 is added in the floating charge discharge path 611 to prevent overcurrent conduction of the body diode of the NMOS transistor 605 from causing burning. When the substrate of the NMOS transistor 605 is floating, the rectifier diode 606 can be omitted. In addition, in this embodiment, the substrates of the two PMOS transistors (607 and 608) constituting the comparison circuit are kept floating to avoid interference of the body diode with the circuit function.

[0105] as Figure 9 shown in figure (b) of , as the twelfth embodiment of the present invention, compared with the eleventh embodiment, in this embodiment, the drain of the NMOS transistor 625 is connected to the port 620 through the rectifier diode 626. The twelfth embodiment has the same principle as the eleventh embodiment, so it will not be repeated here.

[0106] Figure 10 (a) and (b) of are respectively circuit schematic diagrams of the thirteenth embodiment and the fourteenth embodiment of the present invention. The thirteenth embodiment and the fourteenth embodiment show two different configuration modes for implementing robust multi-stage stacked bidirectional ESD protection according to the present invention.

[0107] The thirteenth embodiment illustrates a first multi-level stacked structure comprising two sets of ESD diode strings stacked in the same direction. The first string consists of N ESD diodes, 702-1 to 702-N, with their anodes all facing port 700 and their cathodes all facing port 701. The second string consists of N ESD diodes, 703-1 to 703-N, with their anodes all facing port 701 and their cathodes all facing port 700. These two sets of diode strings are connected head-to-head. The floating node 704 between the two sets of diode strings is connected to the source of a PMOS transistor 705. When a positive or negative bias is applied to port 700, the MAX logic circuit outputs a high level, and the PMOS transistor 705 remains off, not affecting the circuit function. When the positive or negative bias ends, the floating node 704 exhibits a high potential due to charge accumulation. The logic circuit outputs a zero potential, the PMOS transistor 705 turns on (VS-VG<0), and pulls the potential of the floating node 704 low. Because the diode strings between ports 700 and 701 and floating node 704 are all forward-biased diode strings, the intermediate nodes of the diode strings are all pulled down to a low potential.

[0108] The fourteenth embodiment illustrates a second multi-level stacked structure, employing ESD diodes with different orientations alternately connected in series. In this structure, the anodes of diodes 722-1, 722-2, and 722-N face port 720, and the cathodes face port 721; the anodes of diodes 723-1, 723-2, and 723-N face port 721, and the cathodes face port 720. Because the ESD diodes are connected alternately in series, diodes 722-1 and 723-1 are connected "head-to-head," forming a floating node 724-1; diodes 723-1 and 722-N are connected "tail-to-tail," forming a floating node 724-2, and so on. The floating nodes formed by the "head-to-head" connection are connected to the source of the PMOS transistor 725 via current-limiting diodes 726-1 and 726-3; the floating nodes formed by the "tail-to-tail" series connection are connected to the source of the NMOS transistor 727 via current-limiting diodes 726-2 and 726-4. The current-limiting diode serves to prevent the MOS body diode from interfering with the circuit function. When a positive or negative bias is applied to port 720, the MAX and MIN logic circuits output the highest and lowest potentials, respectively, thus keeping both PMOS transistor 725 and NMOS transistor 727 off. After the positive or negative bias ends, the floating nodes formed by "head-to-head" connections exhibit a positive potential (relative to ground) due to the accumulation of positive charge, while the floating nodes formed by "tail-to-tail" series connections exhibit a negative potential (relative to low) due to the accumulation of negative charge. Both the MAX and MIN logic circuits output zero potential. Therefore, both PMOS transistor 725 (VS-VG<0) and NMOS transistor 727 (VG-VS>0) are turned on, discharging the floating charge accumulated in each floating node.

[0109] As can be seen from the above embodiments, in order to prevent the charge accumulated on the floating nodes from affecting ESD devices and to achieve highly robust ESD protection, especially series-type bidirectional ESD protection circuits or various stacked bidirectional ESD protection circuits, the present invention can effectively and timely discharge the accumulated charge on the floating nodes inside the circuit through circuit structure optimization, avoiding interference of the non-zero potential on the internal floating nodes on the ESD clamping voltage, thereby realizing the intrinsic ESD protection capability of the protection circuit.

[0110] The specific embodiments described above are preferred embodiments of the present invention and are not intended to limit the specific scope of the present invention. The scope of the present invention includes, but is not limited to, these specific embodiments. All equivalent changes made in accordance with the present invention are within the protection scope of the present invention.

Claims

1. A robust bidirectional stacked electrostatic discharge protection circuit, characterized in that: It includes a bidirectional stacked electrostatic protection module and a floating charge discharge module, wherein, Bidirectional stacked electrostatic protection module: one end is connected to a first port and the other end is connected to a second port. The bidirectional stacked electrostatic protection module includes at least one floating node, and also includes a first electrostatic protection device and a second electrostatic protection device arranged in series and in opposite directions. The number of the first electrostatic protection device and the second electrostatic protection device is at least one. The floating node is arranged between the first electrostatic protection device and the second electrostatic protection device. The floating node can accumulate residual charge during normal circuit operation or electrical characteristic testing and characterization. The floating charge discharge module consists of a state control module and a charge discharge module. The state control module monitors the potential state of the floating node in real time and generates a control signal; the charge discharge module responds to the control signal and conducts to discharge the charge accumulated in the floating node. The floating charge discharge module includes a discharge tube. The control end of the discharge tube is connected to the first port through the state control module. The input end of the discharge tube is connected to the floating node, and the output end is connected to the second port.

2. The robust bidirectional stacked electrostatic discharge protection circuit according to claim 1, characterized in that: The state control module is a control path connecting the first port and the control terminal of the bleed tube, and the bleed tube is a device with switching characteristics.

3. The robust bidirectional stacked electrostatic discharge protection circuit according to claim 2, characterized in that: The discharge tube is a MOS transistor. The floating charge discharge module also includes a first resistor and a first diode. The first resistor is disposed on the control path. The first diode is disposed between the drain of the MOS transistor and the second port. The disposed direction of the first diode is opposite to the disposed direction of the body diode of the MOS transistor. The first resistor is disposed between the gate of the MOS transistor and the first port.

4. The robust bidirectional stacked electrostatic discharge protection circuit according to claim 3, characterized in that: The state control module is a logic control circuit. The first input terminal of the logic control circuit is connected to the first port, the second input terminal is connected to the second port, and the output terminal of the logic control circuit is connected to the gate of the MOS transistor.

5. The robust bidirectional stacked electrostatic discharge protection circuit according to claim 4, characterized in that: The MOS transistor is a PMOS transistor, with its source connected to a floating node and its drain connected to the second port. The state control module is a MAX(A,B) logic circuit, with its first input connected to the first port and a voltage value of A, its second input connected to the second port and a voltage value of B, and its output connected to the gate of the PMOS transistor.

6. The robust bidirectional stacked electrostatic discharge protection circuit according to claim 5, characterized in that: The MAX(A,B) logic circuit includes a first PMOS transistor and a second PMOS transistor. The source of the first PMOS transistor is connected to a first port, and its gate is connected to a second port. The source of the second PMOS transistor is connected to a second port, and its gate is connected to a first port. The drains of the first PMOS transistor and the drains of the second PMOS transistor are connected together and serve as the output terminal of the MAX(A,B) logic circuit.

7. The robust bidirectional stacked electrostatic discharge protection circuit according to claim 4, characterized in that: The MOS transistor is an NMOS transistor, with its source connected to a floating node and its drain connected to the second port. The state control module is a MIN(C,D) logic circuit, with its first input connected to the first port and a voltage value of C, its second input connected to the second port and a voltage value of D, and its output connected to the gate of the NMOS transistor.

8. The robust bidirectional stacked electrostatic discharge protection circuit according to claim 7, characterized in that: The MIN(C,D) logic circuit includes a first NMOS transistor and a second NMOS transistor. The source of the first NMOS transistor is connected to a first port, and its gate is connected to a second port. The source of the second NMOS transistor is connected to a second port, and its gate is connected to a first port. The drains of the first NMOS transistor and the drains of the second NMOS transistor are connected together and serve as the output terminal of the MIN(C,D) logic circuit.

9. The robust bidirectional stacked electrostatic discharge protection circuit according to claim 1, characterized in that: The bidirectional stacked electrostatic protection module adopts a multi-level stacked structure. The bidirectional stacked electrostatic protection module includes a first electrostatic protection unit and a second electrostatic protection unit. The first electrostatic protection unit and the second electrostatic protection unit are connected in series and arranged in opposite directions. The floating node exists between the first electrostatic protection unit and the second electrostatic protection unit. Both the first electrostatic protection unit and the second electrostatic protection unit are provided with N electrostatic protection devices arranged in the same direction. or, The bidirectional stacked electrostatic discharge (ESD) protection module includes two or more stacked pairs of ESD protection devices. Each ESD protection device pair includes a first ESD protection device and a second ESD protection device. The first and second ESD protection devices are connected in series and arranged in opposite directions. When the bidirectional stacked electrostatic protection module is composed of two or more electrostatic protection devices stacked together, the floating node includes a first floating node between the first and second electrostatic protection devices arranged tail to tail, and a second floating node between the first and second electrostatic protection devices arranged head to head. The floating charge discharge module includes a first MOS transistor and a second MOS transistor. The state control module includes a first state control unit for controlling the first MOS transistor and a second control unit for controlling the second MOS transistor. Multiple first floating nodes are each connected to the source of the first MOS transistor via a diode, and the diodes connected to the first floating nodes are oriented in the opposite direction to the body diodes of the first MOS transistor. Similarly, multiple second floating nodes are each connected to the source of the second MOS transistor via a diode, and the diodes connected to the second floating nodes are oriented in the opposite direction to the body diodes of the second MOS transistor. The first MOS transistor is a PMOS transistor, and the second MOS transistor is an NMOS transistor.

10. The robust bidirectional stacked electrostatic discharge protection circuit according to any one of claims 3-9, characterized in that: The floating charge discharge module is also provided with an overcurrent protection structure, which keeps the substrate of the MOS transistor floating.

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