A control method of a heavy parallel ac source integrated machine

Abstract

The application relates to the field of alternating current modular power supplies, in particular to a multi-module heavy parallel alternating current source and load integrated machine control method. The method has two modes of power supply and load. In the source mode, single-module heavy unit forward operation and reverse operation can be controlled, and multi-module heavy parallel operation can be realized. In the load mode, the heavy unit can be controlled to operate as an electronic load, and multi-module heavy parallel load mode operation can be realized. The power supply and load modes can control single-module heavy unit current sharing and multi-module current sharing.

Description

Technical Field

[0001] This invention relates to the field of AC modular power supplies, and more specifically to a control method for a multi-module parallel AC power supply integrated unit. Background Technology

[0002] With the increasing demand for grid characteristic simulation and off-grid anti-islanding testing of photovoltaic inverters and energy storage inverters, the need for load simulation is also rising. To meet testing requirements at power levels of several hundred kilovolt-amperes, modular source-load integrated testing systems have emerged. Compared to traditional source-load integrated systems, they feature high power density, good flexibility, high configurability, strong system reliability, and convenient maintenance, making them widely applicable to various testing scenarios.

[0003] Modular AC power supplies, with their flexible configuration, high reliability, and high efficiency, have become a core solution for complex testing scenarios, particularly suitable for R&D verification, industrial automation, and high-precision instrumentation. Their significance lies not only in their technological breakthroughs but also in their rapid response to dynamic demands and optimization of lifecycle costs.

[0004] Therefore, it is particularly important to develop a control method for a parallel AC source-carrier integrated machine. Summary of the Invention

[0005] The purpose of this invention is to provide a control method for a parallel AC source-carrier integrated unit that can combine high power density, flexible expansion capability, efficient current sharing control, and dual-mode operation.

[0006] To achieve the above objectives, the present invention employs the following technical solutions.

[0007] A control method for a parallel AC power source and load integrated unit includes two operating modes: power supply mode and load mode. The power supply modes include single-module parallel inverter control and multi-module parallel inverter control, and the load modes include single-module parallel electronic load control and multi-module parallel electronic load control. The control method is implemented based on one or more stand-alone systems. Each stand-alone system includes a master core, three slave cores, and three reprocessing power units. Each phase reprocessing power module constitutes a single module; phases A, B, and C are independent single modules. The master core is independent of each single module and is used for setting values ​​for the entire stand-alone system and calculating the outer loop of the source mode voltage. The three slave cores correspond to phases A, B, and C of the inverter output power supply, respectively. Each slave core controls one reprocessing power unit and is responsible for the loop calculation of the corresponding phase. The master core and slave cores transmit data via a high-speed serial port. The rechargeable power unit includes two or more rechargeable power units. Each rechargeable power unit includes a single H-bridge, a bus capacitor, two primary inductors, a primary filter capacitor, and a secondary filter inductor. The rechargeable power unit is equipped with an inductor current sampling point, an output current sampling point, and an output voltage UO sampling point.

[0008] Furthermore, the recombined power unit is a double-recombined power unit, comprising two recombined power units; The first power unit includes a single H-bridge composed of switches VT1~VT4, a bus capacitor C1, primary inductors L1~L2, a primary filter capacitor C3, and a secondary filter inductor L5; the second power unit includes a single H-bridge composed of switches VT5~VT8, a bus capacitor C2, primary inductors L3~L4, a primary filter capacitor C4, and a secondary filter inductor L6. The dual power unit is equipped with inductor current sampling points IL1 and IL2, output current sampling points IO1 and IO2, and output voltage sampling point UO.

[0009] Furthermore, the specific steps for controlling a single-module parallel inverter are as follows: S11. The main core acquires a given signal Ug, wherein the given signal Ug is an AC signal, a DC signal, or an AC / DC superposition signal; S12. The main core calculates the difference between the given signal Ug and the output voltage feedback signal Uf, and obtains the signal U after being amplified by the outer loop PID error. PID And transmit the signal U via a high-speed serial port PID Send to the corresponding slave core; S13, the signal U received from the core PID And given as two inner loops respectively: the first inner loop will U PID The signal is compared with the inductor current feedback signal IL1 and the average output current I0 / 2. After error amplification by the inner loop PI control loop, the signal Upi1 is obtained, which is used to control the first refactoring power unit and thus control the output waveform; the second inner loop will convert U... PID The signal is compared with the inductor current feedback signal IL2 and the average value of the output current I0 / 2. The error is amplified by the second inner loop PI control loop to obtain the signal Upi2, which is used to control the second H-bridge power unit. Wherein, I0 / 2=(I01+I02) / 2, and IO1 and IO2 are the output currents of the two H-bridge power units, respectively.

[0010] Furthermore, the single-module parallel inverter includes forward operation control and reverse operation control; The flow sharing control of the forward operation control is as follows: The inductor current provides negative feedback, while the output current provides positive feedback. If IL1>I0 / 2, the first inner loop will UPID After the signal is compared with the inductor current feedback signal IL1 and the average output current I0 / 2, a negative error signal is generated and superimposed on the U of the first inner loop PID signal, the first inner loop PI control reduces Upi1, so that the output voltage of the first dual-active power unit decreases to reduce the output current. Meanwhile, when IL2<I0 / 2, a positive error signal is generated after comparison and superimposed on the U of the second inner loop PID signal, the second inner loop PI control increases Upi2, so that the output voltage of the second dual-active power unit increases to increase the output current, thereby realizing circulating current suppression; if IL1<I0 / 2, a positive error signal is generated and superimposed on the U of the first inner loop PID signal, the first inner loop PI control increases Upi1, so that the output voltage of the first dual-active power unit increases to increase the output current. Meanwhile, when IL2>I0 / 2, a negative error signal is generated and superimposed on the U of the second inner loop PID signal, the second inner loop PI control reduces Upi2, so that the output voltage of the second dual-active power unit decreases to reduce the output current, thereby realizing circulating current suppression; The current sharing control for reverse operation is: Inductor current is positive feedback, and output current is negative feedback; If IL1>I0 / 2, the first inner loop processes U PID After the signal is compared with the inductor current feedback signal IL1 and the average output current I0 / 2, a positive error signal is generated and superimposed on the U of the first inner loop PID signal, the first inner loop PI control increases Upi1, so that the output voltage of the first dual-active power unit increases to reduce the output current; meanwhile, when IL2<I0 / 2, a negative error signal is generated after comparison and superimposed on the U of the second inner loop PID signal, the second inner loop PI control reduces Upi2, so that the output voltage of the second dual-active power unit decreases to increase the output current; if IL1<I0 / 2, a negative error signal is generated and superimposed on the U of the first inner loop PID signal, the first inner loop PI control reduces Upi1, so that the output voltage of the first dual-active power unit decreases to increase the output current. Meanwhile, when IL2>I0 / 2, a positive error signal is generated and superimposed on the U of the second inner loop PID signal, the second inner loop PI control increases Upi2, so that the output voltage of the second dual-active power unit increases to reduce the output current, thereby realizing circulating current suppression and simulating reverse power feedback to the power grid.

[0011] Further, the specific steps of control for multi-module dual-active parallel inverter are: S21, the main core of the host calculates the voltage outer loop for the total multi-module parallel output voltage Uf_total, and the difference between the given voltage Ug_total and Uf_total is amplified by the outer loop PID error to obtain the signal UPID _total, the signal U is transmitted through the high-speed serial port PID _total is issued to each slave core; S22, each slave core calculates the average output current I0 / 2_i of its own module, and uploads I0 / 2_i to the host master core through the high-speed serial port, wherein i is the slave number, I0 / 2_i=(I01_i+I02_i) / 2, I01_i and I02_i are respectively the output currents of the two H-bridge power units of the i-th slave; the host master core二次 averages all I0 / 2_i to obtain the total average current Iave of the slave cores, and issues the Iave to each slave core through the high-speed serial port; S23, the i-th slave core uses the U PID _total as the inner loop given, the first inner loop compares U PID _total with the first inductor current feedback signal IL1_i of the slave and Iave, obtains the signal Upi1_i through error amplification of the first inner loop PI control link, which is used to control the first multiplexing power unit, and then controls the output waveform; the second inner loop compares U PID _total with the second inductor current feedback signal IL2_i of the slave and Iave, obtains the signal Upi2_i through error amplification of the second inner loop PI control link, which is used to control the second multiplexing power unit; The multi-module includes one host and at least two slaves, the host includes a host master core, the slave includes a slave core of the slave and two multiplexing power units controlled by each slave core, and the slave cores include host slave cores and slave cores of slaves.

[0012] Further, the multi-module multiplexed parallel inverter includes forward operation control and reverse operation control; The current sharing control of the forward operation control is: The slave core inductor current is negative feedback, and the average current Iave calculated by the master core is positive feedback; If IL1_i of the i-th slave is greater than Iave, a negative error signal is superimposed on U PID _total, which reduces Upi1_i and the output voltage of the corresponding H-bridge power unit, and decreases the output current. Meanwhile, if IL2_i is less than Iave, a positive error signal is superimposed on U PID _total, which increases Upi2_i and the output voltage of the corresponding H-bridge power unit, and increases the output current; if IL1_i of the i-th slave is less than Iave, a positive error signal is superimposed on U PID _total, which increases Upi1_i and the output voltage of the corresponding H-bridge power unit, and increases the output current. Meanwhile, if IL2_i is greater than Iave, a negative error signal is superimposed on U PID_total, reduce Upi2_i and the output voltage of the corresponding H-bridge power unit, reduce the output current, and suppress the circulating current between modules; The current sharing control for reverse operation is: The slave core inductor current adopts positive feedback, and the average current Iave calculated by the master core adopts negative feedback; If IL1_i of the i-th slave is greater than Iave, a positive error signal is superimposed on U PID _total, increase Upi1_i and the output voltage of the corresponding H-bridge power unit, reduce the output current; meanwhile, if IL2_i is less than Iave, a negative error signal is superimposed on U PID _total, reduce Upi2_i and the output voltage of the corresponding H-bridge power unit, and increase the output current; if IL1_i of the i-th slave is less than Iave, a negative error signal is superimposed on U PID _total, reduce Upi1_i and the output voltage of the corresponding H-bridge power unit, increase the output current; meanwhile, if IL2_i is greater than Iave, a positive error signal is superimposed on U PID _total, increase Upi2_i and the output voltage of the corresponding H-bridge power unit, reduce the output current, so as to realize reverse current control and grid feedback simulation.

[0013] Further, the specific steps of load mode control are: S31, the master core obtains the given current value Ig, averages the given current signal to obtain Ig_ave according to the number of heavy-loaded modules, and issues Ig_ave to each slave core through a high-speed serial port as the outer loop given; S32, the slave core takes Ig_ave as the given current outer loop and compares it with the average output current I0 / 2 of the current slave core to obtain an error signal, and amplifies the error signal through PID to obtain signal I PID , wherein I0 / 2=(I01+I02) / 2, and IO1 and IO2 are respectively the output currents of the two H-bridge power units of the current slave core; S33, the slave core takes I PID as the inner loop given; the first channel is compared with the inductor current feedback signal IL1 and the average output current I0 / 2 of the current slave core, and the error is amplified through the first inner loop PI control link to obtain the signal Upi1, which is used to control the first H-bridge power unit; the second channel is compared with the inductor current feedback signal IL2 and the average output current I0 / 2 of the current slave core, and the error is amplified through the second inner loop PI control link to obtain the signal Upi2, which is used to control the second H-bridge power unit; the inductor current feedback signals IL1 and IL2 adopt negative feedback, and the average output current I0 / 2 adopts positive feedback; S34. The outer current loop controls the output current to be infinitely close to Ig_ave, realizing current sharing within and between modules, and controlling the total output current waveform to simulate the load.

[0014] Furthermore, the master core is a single-machine master core in single-module parallel electronic load control and a host master core in multi-module parallel electronic load control; the slave core is a single-machine slave core in single-module parallel electronic load control and a slave slave core in multi-module parallel electronic load control; the single-module parallel electronic load control includes a single-machine system consisting of one host and one slave, and the multi-module parallel electronic load control includes one host and at least two slaves.

[0015] Furthermore, the circuit connection relationship of the dual power unit is as follows: The bus capacitor C1 of the first power unit is connected in parallel to the DC side of the first H-bridge composed of VT1~VT4. One end of the first-stage inductor L1 is connected to the midpoint of the right arm of the first H-bridge, and the other end is connected to the first end of the first-stage filter capacitor C3. One end of the first-stage inductor L2 is connected to the midpoint of the left arm of the first H-bridge, and the other end is connected to the second end of the first-stage filter capacitor C3. The second-stage filter inductor L5 is connected in series between the first end of C3 and the positive terminal of the output voltage UO, and the negative terminal of UO is connected to the second end of C3. The bus capacitor C2 of the second power unit is connected in parallel to the DC side of the second H-bridge composed of VT5~VT8. One end of the first-stage inductor L3 is connected to the midpoint of the right arm of the second H-bridge, and the other end is connected to the first end of the first-stage filter capacitor C4. One end of the first-stage inductor L4 is connected to the midpoint of the left arm of the second H-bridge, and the other end is connected to the second end of the first-stage filter capacitor C4. The second-stage filter inductor L6 is connected in series between the first end of C4 and the positive terminal of the output voltage UO, and the second end of C4 is connected to the negative terminal of U0. The connection points of L1 and the right arm of the first H bridge, and L3 and the right arm of the second H bridge, are the inductor current sampling points IL1 and IL2, respectively. The connection points of L5 and the first terminal of C3, and L6 and the first terminal of C4, are the output current sampling points IO1 and IO2, respectively. The positive terminal of the output voltage U0 is the output voltage sampling point.

[0016] Furthermore, the power unit is expanded into a triple or more multi-unit power unit. After expansion, the parameter settings and signal distribution logic of the master core and the loop calculation and control logic of the slave core are adaptively adjusted to realize the current sharing control and power / load mode operation of the multi-unit.

[0017] The advantages of this invention are: It has a high degree of functional integration, with both power supply and load modes, and can complete integrated source and load testing without additional equipment, simplifying the test system architecture. It has strong current sharing accuracy. Within a single module, it uses I0 / 2 as the reference, and between multiple modules, it uses Iave as the reference. Through error superposition and feedback adjustment, it effectively suppresses circulating current caused by device parameter errors, resulting in small output current fluctuations. It offers good flexibility for expansion, supporting the expansion of power units from dual to multiple levels. Multiple modules connected in parallel can cover a wider power range and adapt to different test scenarios. The control response is rapid, with high-speed serial communication between the master and slave cores. The combination of outer-loop PID and inner-loop PI control results in a short dynamic response time and can realize AC, DC, AC-DC superposition output and grid feedback simulation. It has high reliability, with each module designed independently and without mutual interference. The failure of a single module does not affect the operation of the overall system, and maintenance is convenient. Attached Figure Description

[0018] Figure 1 This is a block diagram of a standalone system of the present invention; Figure 2 This is a schematic diagram of the single-module rechargeable power module of the present invention; Figure 3 This is a block diagram of the forward operation control of the single-module source mode of the present invention; Figure 4 This is a block diagram of the single-module source mode reverse operation control of the present invention; Figure 5 This is a block diagram of the forward operation control of the multi-module source mode of the present invention; Figure 6 This is a block diagram of the multi-module source mode reverse operation control of the present invention; Figure 7 This is a block diagram of the single-module load mode control of the present invention; Figure 8 This is a block diagram of the multi-module parallel loading mode control of the present invention. Detailed Implementation

[0019] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0020] Example 1 This embodiment provides a control method for a parallel AC source-load integrated unit, specifically divided into power supply mode and load mode. The source mode includes a single-module parallel inverter control method and a multi-module combined control method for parallel inverters; the load mode includes a single-module parallel electronic load control method and a multi-module combined control method for parallel electronic loads.

[0021] This embodiment uses a dual-power unit as an example. Please refer to the system architecture design. Figure 1The single-unit system includes one master core, three slave cores, and three reprocessing power units. Each phase reprocessing power module constitutes a single module. Phases A, B, and C are independent single modules. The master core is independent of the single modules and is used for setting the system settings and calculating the outer loop of the source mode voltage. The three slave cores correspond to phases A, B, and C of the inverter output power supply, respectively. Each slave core controls one reprocessing power unit and is responsible for the loop calculation of the corresponding phase. The master core and slave cores transmit data through a high-speed serial port.

[0022] Please refer to Figure 2 The bus capacitor C1 of the first rechargeable power unit is connected in parallel to the DC side of the first H-bridge composed of VT1~VT4. One end of the first-stage inductor L1 is connected to the midpoint of the right arm of the first H-bridge, and the other end is connected to the first end of the first-stage filter capacitor C3. One end of the first-stage inductor L2 is connected to the midpoint of the left arm of the first H-bridge, and the other end is connected to the second end of the first-stage filter capacitor C3. The second-stage filter inductor L5 is connected in series between the first end of C3 and the positive terminal of the output voltage UO, and the negative terminal of UO is connected to the second end of C3. The bus capacitor C2 of the second power unit is connected in parallel to the DC side of the second H-bridge composed of VT5~VT8. One end of the first-stage inductor L3 is connected to the midpoint of the right arm of the second H-bridge, and the other end is connected to the first end of the first-stage filter capacitor C4. One end of the first-stage inductor L4 is connected to the midpoint of the left arm of the second H-bridge, and the other end is connected to the second end of the first-stage filter capacitor C4. The second-stage filter inductor L6 is connected in series between the first end of C4 and the positive terminal of the output voltage UO, and the second end of C4 is connected to the negative terminal of U0. The connection points of L1 and the right arm of the first H bridge, and L3 and the right arm of the second H bridge, are the inductor current sampling points IL1 and IL2, respectively. The connection points of L5 and the first terminal of C3, and L6 and the first terminal of C4, are the output current sampling points IO1 and IO2, respectively. The positive terminal of the output voltage U0 is the output voltage sampling point.

[0023] 1. Control logic for power mode The power supply mode is used to simulate grid output, supporting independent operation of a single module and parallel operation of multiple modules, including both forward and reverse operating conditions.

[0024] When a single module is running in forward mode, its working status is as follows: Figure 3 As shown, the master core is used for voltage outer loop control calculations, and the voltage outer loop output is sent to the slave core as the inner loop setpoint. The slave core is used to refactor the inner loop calculations. Specifically, the setpoint module is an AC signal, a DC signal, or a superimposed AC / DC signal. The difference between the setpoint signal Ug and the output voltage feedback signal Uf is calculated, and after being amplified by the outer loop PID error, the signal Ug is obtained. PID and transmit U via high-speed serial port PID It is then passed down to the slave core.

[0025] U received from the core to the main core PIDThe signals are then used as two inner loop references. One loop is compared with the inductor current feedback signal IL1 and the output current feedback signal I0 / 2. After error amplification by the inner loop PI control loop, the signal Upi1 is obtained. The other loop is compared with the inductor current feedback signal IL2 and the output current feedback signal I0 / 2. After error amplification by the inner loop PI control loop, the signal Upi2 is obtained. These signals are used to control the power module and thus control the output waveform.

[0026] When a single module is running in forward mode, the current sharing principle of the module is as follows: the main core receives the given signal Ug, compares it with the feedback signal Uf of UO, and then amplifies it through a PID controller to obtain Ug. PID The data is sent to the slave core; the slave core will then send U... PID The comparison is split into two paths, with comparisons made to IL1, I0 / 2 and IL2, I0 / 2 respectively. Each branch outputs Upi1 and Upi2 via P control, driving the two H-bridges respectively. Current sharing is achieved through error superposition: if the current exceeds the limit, the H-bridge lowers the output voltage; if the current is insufficient, the output voltage is increased, thus suppressing circulating current.

[0027] When a single module is run in reverse, its working status is as follows: Figure 4 As shown, the working principle is basically the same as in the forward direction, the difference being that in reverse operation, the inductor current is positive feedback and the output current is negative feedback. The slave core calculates the difference between the inductor current and the average output current I0 / 2 to obtain a current signal opposite to that in the forward operation. The slave core receives the voltage outer loop output U from the master core. PID Then, these are used as the inputs for the two inner loops, and corresponding inner loop control is performed to control the power supply to work in reverse to simulate the power grid.

[0028] When a single module is running in reverse, the current sharing principle is similar to that in forward mode. The core also calculates the average current I0 / 2 of the two paths. The inner loop uses the inductor current and the average current for calculation, and the error signal is superimposed on the outer loop given U received from the core. PID The difference is that the error signal is in the opposite direction to the positive direction. Reverse current control is achieved by adjusting the output voltage to simulate grid feedback.

[0029] The multi-module parallel inverter control method can control multiple combined modules. The multi-module system consists of a master unit (including the master core) and multiple slave units. It can realize all output modes of a single-module parallel inverter, control the current sharing of the internal units of a single module, and ensure that the output voltage of the master and slave modules is consistent. It can achieve steady-state suppression of circulating current between different modules, and suppress the output circulating current caused by the error of the power supply device parameters. The output voltage is adjusted in real time through the circulating current error to achieve dynamic suppression of circulating current.

[0030] When multiple modules are running in a forward configuration, their working states are as follows: Figure 5As shown, the host core amplifies the difference between the given voltages Ug_total and Uf_total using an outer-loop PID converter to obtain the outer-loop PID, thus obtaining U... PID _total; Each slave device uploads its own I0 / 2 from its slave core, and the master device averages this to obtain the total average current Iave; U PID _total and Iave are sent to the slave device. The slave device controls the current according to the single module logic, and adjusts the current based on Iave to suppress the circulating current between modules.

[0031] When multiple modules run in reverse, their working states are as follows: Figure 6 As shown, the slave inductor current is the positive feedback, and the master Iave is the negative feedback; the error signal direction is adjusted to realize reverse current sharing and grid feedback simulation.

[0032] 2. Control logic for load mode The load mode is used to simulate real loads and supports single-module and multi-module operation. Its core is current loop control.

[0033] The block diagram of the single-module parallel electronic load control is as follows: Figure 7 As shown, the master core provides a current Ig, which is averaged to obtain Ig / 2 and then sent to the slave core. The slave core uses Ig / 2 as the outer current loop reference, compares it with I0 / 2, and obtains Ig / 2 via PID control. PID ;I PID As the inner loop reference, the H bridge is driven by P control after being compared with IL1 and IL2 in two branches respectively; the outer current loop ensures that the output current is close to Ig / 2, realizing current sharing and load waveform control.

[0034] Multi-module parallel electronic load control block diagram as follows Figure 8 As shown, the host core calculates the average value of the total given current Ig_total based on the total number of refactoring units N, obtaining Ig_avg=Ig_total / N, and then sends Ig_avg to each slave unit; the slave units are controlled according to single-module logic, and the current outer loop ensures that the current of each unit is consistent, realizing the overall load simulation.

[0035] Example 2 In Example 1, the dual power units of each module can be expanded to triple or more, while increasing the number of H-bridges. For example, in triple configuration: The newly added H-bridge consists of switching transistors VT9~VT12, and is equipped with bus capacitor C5, primary inductors L7~L8, primary filter capacitor C6, and secondary filter inductor L9. It also adds an inductor current sampling point IL3 and an output current sampling point IO3. The circuit connection structure is the same as that of the first and second power units. The output terminals of the secondary filter inductors of the three H-bridges are connected in parallel and then connected to the total output voltage UO to ensure that the three-phase load draws current in a balanced manner.

[0036] The total current value Ig given by the main core is evenly distributed according to the triplet number, that is, the average current under single module is Ig / 3, replacing Ig / 2 under doublet; the average value of total output current I0 / 3=(IO1+IO2+IO3) / 3, replacing I0 / 2 under doublet. If the inductor current IL3 > I0 / 3, a negative error signal is generated in the forward power supply mode or a positive error signal is generated in the reverse power supply mode. These signals are superimposed on the reference signal. By lowering or raising the corresponding voltage Up3, the output voltage of the H-bridge is adjusted until IL3 approaches I0 / 3, thus achieving current balance of the triplet unit.

[0037] Expanding the power unit multiplication enables the maintenance of current sharing and mode control capabilities, adapting to higher power demands.

[0038] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for controlling a parallel AC source-carrier integrated machine, characterized in that, It includes two operating modes: power mode and load mode; The power supply mode includes single-module parallel inverter control and multi-module parallel inverter control, and the load mode includes single-module parallel electronic load control and multi-module parallel electronic load control. The control method is implemented based on one or more stand-alone systems. Each stand-alone system includes a master core, three slave cores, and three reprocessing power units. Each phase reprocessing power module constitutes a single module; phases A, B, and C are independent single modules. The master core is independent of each single module and is used for setting values ​​for the entire stand-alone system and calculating the outer loop of the source mode voltage. The three slave cores correspond to phases A, B, and C of the inverter output power supply, respectively. Each slave core controls one reprocessing power unit and is responsible for the loop calculation of the corresponding phase. The master core and slave cores transmit data via a high-speed serial port. The rechargeable power unit includes two or more rechargeable power units. Each rechargeable power unit includes a single H-bridge, a bus capacitor, two first-stage inductors, a first-stage filter capacitor, and a second-stage filter inductor. The rechargeable power unit is equipped with an inductor current sampling point, an output current sampling point, and an output voltage U0 sampling point. The recombined power unit is a double-recombined power unit, comprising two recombined power units; The first power unit includes a single H-bridge composed of switches VT1 to VT4, a bus capacitor C1, primary inductors L1 to L2, a primary filter capacitor C3, and a secondary filter inductor L5; the second power unit includes an H-bridge composed of switches VT5 to VT8, a bus capacitor C2, primary inductors L3 to L4, a primary filter capacitor C4, and a secondary filter inductor L6. The dual power unit is equipped with inductor current sampling points IL1 and IL2, output current sampling points IO1 and IO2, and output voltage sampling point U0. The specific steps for controlling the single-module parallel inverter are as follows: S11. The main core acquires a given signal Ug, wherein the given signal Ug is an AC signal, a DC signal, or an AC / DC superposition signal; S12. The main core calculates the difference between the given signal Ug and the output voltage feedback signal Uf, and obtains the signal U after being amplified by the outer loop PID error. PID And transmit the signal U via a high-speed serial port PID Send to the corresponding slave core; S13, the signal U received from the core PID And given as two inner loops respectively: the first inner loop will U PID The signal is compared with the inductor current feedback signal IL1 and the average output current I0 / 2. After error amplification by the inner loop PI control loop, the signal Upi1 is obtained, which is used to control the first refactoring power unit and thus control the output waveform; the second inner loop will convert U... PID The signal is compared with the inductor current feedback signal IL2 and the average value of the output current I0 / 2. The error is amplified by the second inner loop PI control loop to obtain the signal Upi2, which is used to control the second H-bridge power unit. Wherein, I0 / 2=(I01+I02) / 2, and IO1 and IO2 are the output currents of the two H-bridge power units, respectively.

2. The control method for the integrated AC source and load generator in parallel as described in claim 1, characterized in that, The single-module parallel inverter includes forward operation control and reverse operation control; The flow sharing control of the forward operation control is as follows: The inductor current provides negative feedback, while the output current provides positive feedback. If IL1>I0 / 2, the first inner loop outputs U PID signal is compared with the inductor current feedback signal IL1 and the average output current I0 / 2 to generate a negative error signal, which is then superimposed on the U of the first inner loop PID signal, and Upi1 is reduced through PI control of the first inner loop, so that the output voltage of the first interleaved power unit is reduced to decrease the output current. Meanwhile, since IL2<I0 / 2, a positive error signal is generated after comparison and superimposed on the U of the second inner loop PID signal, and Upi2 is increased through PI control of the second inner loop, so that the output voltage of the second interleaved power unit is increased to increase the output current, thereby realizing circulating current suppression. If IL1<I0 / 2, a positive error signal is generated and superimposed on the U of the first inner loop PID signal, and Upi1 is increased through PI control of the first inner loop, so that the output voltage of the first interleaved power unit is increased to increase the output current. Meanwhile, since IL2>I0 / 2, a negative error signal is generated and superimposed on the U of the second inner loop PID signal, and Upi2 is reduced through PI control of the second inner loop, so that the output voltage of the second interleaved power unit is reduced to decrease the output current, thereby realizing circulating current suppression; The flow sharing control of the reverse operation control is as follows: The inductor current provides positive feedback, while the output current provides negative feedback. If IL1 > I0 / 2, the first inner loop will output U PID signal is compared with the inductor current feedback signal IL1 and the average output current I0 / 2 to generate a positive error signal, which is superimposed on the U of the first inner loop PID signal, Upi1 is increased through PI control of the first inner loop, so that the output voltage of the first parallel power unit is increased to reduce the output current; meanwhile, since IL2 < I0 / 2, a negative error signal is generated after comparison and superimposed on the U of the second inner loop PID signal, Upi2 is decreased through PI control of the second inner loop, so that the output voltage of the second parallel power unit is decreased to increase the output current; if IL1 < I0 / 2, a negative error signal is generated and superimposed on the U of the first inner loop PID signal, Upi1 is decreased through PI control of the first inner loop, so that the output voltage of the first parallel power unit is decreased to increase the output current; meanwhile, since IL2 > I0 / 2, a positive error signal is generated and superimposed on the U of the second inner loop PID signal, Upi2 is increased through PI control of the second inner loop, so that the output voltage of the second parallel power unit is increased to reduce the output current, thereby realizing circulating current suppression and simulating reverse power feedback to the power grid.

3. The control method for the integrated AC source and load generator in parallel as described in claim 1, characterized in that, The specific steps for controlling the multi-module parallel inverter are as follows: S21. The main core of the host computer calculates the outer loop of the total output voltage Uf_total of the multiple modules in parallel. The difference between the given voltage Ug_total and Uf_total is amplified by the outer loop PID error to obtain the signal U. PID _total, transmitting signal U via high-speed serial port PID _total is distributed to each slave core; S22. Each slave core calculates the average output current I0 / 2_i of its own module and uploads I0 / 2_i to the host core via a high-speed serial port, where i is the slave number, I0 / 2_i = (I01_i + I02_i) / 2, and IO1_i and IO2_i are the output currents of the two H-bridge power units of the i-th slave. The host core performs a second average on all I0 / 2_i to obtain the total average current Iave of the slave cores, and sends Iave to each slave core via a high-speed serial port. S23, the i-th slave core will transfer the U PID Given _total as the inner loop, the first inner loop will be U PID The total signal is compared with the first inductor current feedback signals IL1_i and Iave of the slave device. After error amplification by the first inner loop PI control circuit, the signal Upi1_i is obtained, which is used to control the first refactoring power unit and thus control the output waveform. The second inner loop will then convert U... PID _total is compared with the second inductor current feedback signals IL2_i and Iave of the slave device. After error amplification by the second inner loop PI control loop, signal Upi2_i is obtained, which is used to control the second power unit. The multi-module includes a master unit and at least two slave units. The master unit includes a master core, and each slave unit includes a slave core and a dual power unit controlled by each slave core. The slave core includes a master core and a slave core.

4. The control method for the integrated AC source and load generator in parallel as described in claim 3, characterized in that, The multi-module parallel inverter includes forward operation control and reverse operation control; The flow sharing control of the forward operation control is as follows: The core inductor current is used for negative feedback, while the average current Iave calculated by the main core is used for positive feedback. If IL1_i of the i-th slave is greater than Iave, a negative error signal is superimposed on U PID _total to reduce Upi1_i and the output voltage of the corresponding H-bridge power unit, thereby decreasing the output current. Meanwhile, if IL2_i is less than Iave, a positive error signal is superimposed on U PID _total to increase Upi2_i and the output voltage of the corresponding H-bridge power unit, thereby increasing the output current; if IL1_i of the i-th slave is less than Iave, a positive error signal is superimposed on U PID _total to increase Upi1_i and the output voltage of the corresponding H-bridge power unit, thereby increasing the output current. Meanwhile, if IL2_i is greater than Iave, a negative error signal is superimposed on U PID _total to decrease Upi2_i and the output voltage of the corresponding H-bridge power unit, thereby decreasing the output current and suppressing circulation between modules; The flow sharing control of the reverse operation control is as follows: The core inductor current is the positive feedback, while the average current Iave calculated by the main core is the negative feedback. If IL1_i of the i-th slave is greater than Iave, a positive error signal is superimposed on U PID _total, increase Upi1_i and the output voltage of the corresponding H-bridge power unit to reduce the output current. Meanwhile, if IL2_i is less than Iave, a negative error signal is superimposed on U PID _total, reduce Upi2_i and the output voltage of the corresponding H-bridge power unit to increase the output current; if IL1_i of the i-th slave is less than Iave, a negative error signal is superimposed on U PID _total, reduce Upi1_i and the output voltage of the corresponding H-bridge power unit to increase the output current. Meanwhile, if IL2_i is greater than Iave, a positive error signal is superimposed on U PID _total, increase Upi2_i and the output voltage of the corresponding H-bridge power unit to reduce the output current, so as to realize reverse current control and grid feedback simulation.

5. The control method for the integrated AC source and load generator in parallel as described in claim 1, characterized in that, The specific steps for load mode control are as follows: S31. The main core obtains the given current value Ig, averages the given current signal according to the number of refactoring modules to obtain Ig_ave, and sends it to each slave core via high-speed serial port as the outer loop given value. S32. The slave core compares Ig_ave, used as the outer current loop reference, with the current average output current I0 / 2 of the current slave core to obtain an error signal. The error signal is then amplified by a PID controller to obtain signal I. PID Wherein, I0 / 2 = (I01 + I02) / 2, and IO1 and IO2 are the output currents of the two H-bridge power units of the current slave core, respectively; S33, the kernel will I PID As the inner loop reference, the first path compares the current inductor current feedback signal IL1 and the average output current I0 / 2 of the current slave core, and the result is amplified by the error of the first inner loop PI control loop to obtain signal Upi1, which is used to control the first H-bridge power unit; the second path compares the current inductor current feedback signal IL2 and the average output current I0 / 2 of the current slave core, and the result is amplified by the error of the second inner loop PI control loop to obtain signal Upi2, which is used to control the second H-bridge power unit; the inductor current feedback signals IL1 and IL2 are negative feedback, and the average output current I0 / 2 is positive feedback; S34. The outer current loop controls the output current to be infinitely close to Ig_ave, realizing current sharing within and between modules, and controlling the total output current waveform to simulate the load.

6. The control method for the integrated AC source and load generator in parallel as described in claim 5, characterized in that, The master core is a single-machine master core in single-module parallel electronic load control and a host master core in multi-module parallel electronic load control. The slave core is a single-machine slave core in single-module parallel electronic load control and a slave slave core in multi-module parallel electronic load control. The single-module parallel electronic load control includes a single-machine system consisting of one host and one slave, and the multi-module parallel electronic load control includes one host and at least two slaves.

7. The control method for the integrated AC source and load generator in parallel as described in claim 1, characterized in that, The circuit connection relationship of the dual power unit is as follows: The bus capacitor C1 of the first power unit is connected in parallel to the DC side of the first H-bridge composed of VT1~VT4. One end of the first-stage inductor L1 is connected to the midpoint of the right arm of the first H-bridge, and the other end is connected to the first end of the first-stage filter capacitor C3. One end of the first-stage inductor L2 is connected to the midpoint of the left arm of the first H-bridge, and the other end is connected to the second end of the first-stage filter capacitor C3. The second-stage filter inductor L5 is connected in series between the first end of C3 and the positive terminal of the output voltage U0, and the negative terminal of U0 is connected to the second end of C3. The bus capacitor C2 of the second power unit is connected in parallel to the DC side of the second H-bridge composed of VT5~VT8. One end of the first-stage inductor L3 is connected to the midpoint of the right arm of the second H-bridge, and the other end is connected to the first end of the first-stage filter capacitor C4. One end of the first-stage inductor L4 is connected to the midpoint of the left arm of the second H-bridge, and the other end is connected to the second end of the first-stage filter capacitor C4. The second-stage filter inductor L6 is connected in series between the first end of C4 and the positive terminal of the output voltage U0, and the second end of C4 is connected to the negative terminal of U0. The connection points of L1 and the right arm of the first H bridge, and L3 and the right arm of the second H bridge, are the inductor current sampling points IL1 and IL2, respectively. The connection points of L5 and the first terminal of C3, and L6 and the first terminal of C4, are the output current sampling points IO1 and IO2, respectively. The positive terminal of the output voltage U0 is the output voltage sampling point.

8. The control method for the integrated AC source and load generator in parallel as described in claim 1, characterized in that, The power unit is expanded into a triple or more multi-functional power unit. After expansion, the parameter settings and signal distribution logic of the master core and the loop calculation and control logic of the slave core are adaptively adjusted to realize the current sharing control and power / load mode operation of the multi-functional unit.

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