A data coding method, system, device, medium and product

Abstract

The application discloses a data decoding method, system, device, medium and product, and the method is applied to a decoder system, and comprises a path processing unit, a surviving path inheritance unit, a plurality of decoding processing units and a plurality of storage units. The decoding processing unit is used for acquiring current data to be processed and performing decoding processing on each information bit, and a current path calculation result is determined. The path processing unit is used for processing all current path calculation results to obtain a current surviving path calculation result set. The surviving path inheritance unit is used for establishing a data path relationship between the decoding processing unit and the storage unit according to a historical mapping relationship, managing the historical mapping relationship according to the current surviving path calculation result set, and obtaining a current mapping relationship. The storage unit is used for storing a decoding process calculation result of a parent path. The mapping relationship avoids a copy operation in path inheritance, reduces processing time delay caused by memory copying and power consumption cost in the memory copying process.

Description

Technical Field

[0001] This invention relates to the field of channel coding technology, and in particular to a data decoding method, system, device, medium, and product. Background Technology

[0002] Among common implementations of Polar decoders, the Successive Cancellation List (SCL) algorithm is a widely used approach. Essentially, SCL is an improvement on the Successive Cancellation (SC) algorithm. SC decodes bit-by-bit, determining the current bit's value based on the previous bit's decoding result. This approach cannot correct errors, limiting performance. SCL, however, introduces the concept of list decoding. For each bit, it retains L most probable paths (which can be considered hypothetical or possible paths), and finally selects the path with the highest likelihood from these L paths as the decoded output. Therefore, SCL effectively reduces the impact of error propagation, significantly improving decoding performance.

[0003] While the SCL algorithm offers a significant performance improvement over the SC algorithm, it also suffers from high computational complexity and large storage requirements (including memory size and frequent memory read / write operations). Particularly when path inheritance is involved, all computation results from the inherited path need to be copied to the new path (the surviving path after inheritance), resulting in numerous memory read / write operations. This leads to significant processing latency and power consumption for the hardware implementation. Summary of the Invention

[0004] This invention provides a data decoding method, system, device, medium, and product to enable decoding without the need for copying.

[0005] According to a first aspect of the present invention, a data decoding method is provided, applied to a decoder system, the system comprising: a path processing unit, a surviving path inheritance unit, a plurality of decoding processing units, and a plurality of storage units, wherein the number of storage units is the same as the number of decoding processing units, the method comprising:

[0006] The decoding processing unit obtains the current data to be processed for each information bit, decodes the current data to be processed, and determines the current path calculation result.

[0007] The path processing unit processes all the current path calculation results to obtain the current surviving path calculation result set;

[0008] The surviving path inheritance unit establishes a data path relationship between the decoding processing unit and the storage unit based on the historical mapping relationship, so that the decoding processing unit reads the current data to be processed according to the data path relationship; the historical mapping relationship is the association between the path number of the parent path and the corresponding storage unit in the historical surviving path calculation result of the previous bit.

[0009] The historical mapping relationships are managed based on the current surviving path calculation result set to obtain the current mapping relationship;

[0010] The storage unit stores the decoding process calculation results of the parent path specified by the surviving path inheritance unit.

[0011] According to a second aspect of the present invention, a decoder system is provided, characterized in that it comprises: a path processing unit, a surviving path inheritance unit, a plurality of decoding processing units and a plurality of storage units, wherein the number of storage units is the same as the number of decoding processing units;

[0012] The decoding processing unit is used to obtain the current data to be processed for each information bit, and to perform decoding processing on the current data to be processed to determine the current path calculation result;

[0013] The path processing unit is used to process all the current path calculation results to obtain the current surviving path calculation result set;

[0014] The survivor path inheritance unit is used to establish a data path relationship between the decoding processing unit and the storage unit according to the historical mapping relationship, so that the decoding processing unit reads the current data to be processed according to the data path relationship; the historical mapping relationship is the association between the path number of the parent path and the corresponding storage unit in the historical survivor path calculation result of the previous bit.

[0015] The historical mapping relationships are managed based on the current surviving path calculation result set to obtain the current mapping relationship;

[0016] The storage unit is used to store the decoding process calculation results of the parent path specified by the surviving path inheritance unit.

[0017] According to a third aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0018] At least one decoder system; and

[0019] A memory communicatively connected to the at least one decoder system; wherein,

[0020] The memory stores a computer program that can be executed by the at least one decoder system, the computer program being executed by the at least one decoder system to enable the at least one decoder system to perform the data decoding method according to any embodiment of the present invention.

[0021] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions, the computer instructions being configured to cause a decoder system to execute and implement the data decoding method described in any embodiment of the present invention.

[0022] According to a fifth aspect of the present invention, embodiments of the present invention also provide a computer program product, the computer program product including a computer program, which, when executed by a decoder system, implements the data decoding method of any embodiment of the present invention.

[0023] The technical solution of this invention is applied to a decoder system. The system includes: a path processing unit, a surviving path inheritance unit, multiple decoding processing units, and multiple storage units. The number of storage units is the same as the number of decoding processing units. The method includes: obtaining the current data to be processed for each information bit through the decoding processing unit, and performing decoding processing on the current data to be processed to determine the current path calculation result; processing all current path calculation results through the path processing unit to obtain the current surviving path calculation result set; establishing a data path relationship between the decoding processing unit and the storage unit according to the historical mapping relationship through the surviving path inheritance unit, so that the decoding processing unit reads the current data to be processed according to the data path relationship; the historical mapping relationship is the association between the path number of the parent path in the historical surviving path calculation result of the previous bit and the corresponding storage unit; managing the historical mapping relationship according to the current surviving path calculation result set to obtain the current mapping relationship; and storing the decoding process calculation result of the parent path specified by the surviving path inheritance unit through the storage unit. By establishing a mapping relationship, the entire SCL decoding process achieves zero memory copying requirements during path inheritance, avoiding the operation in ordinary SCL decoder implementations where the calculation result of the parent path must be copied to the surviving path during path inheritance. This greatly reduces the processing latency caused by memory copying, as well as the power consumption cost during memory copying.

[0024] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a flowchart of a data decoding method provided in Embodiment 1 of the present invention;

[0027] Figure 2 This is a flowchart of a data decoding method provided in Embodiment 2 of the present invention;

[0028] Figure 3 This is a schematic diagram of a decoder system according to Embodiment 3 of the present invention;

[0029] Figure 4 This is a schematic diagram of the structure of an electronic device that implements an embodiment of the present invention. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] Example 1

[0033] Figure 1The flowchart of a data decoding method provided in Embodiment 1 of the present invention is applicable to the case of decoding by the SCL algorithm. The method can be executed by a decoder system, which includes: a path processing unit, a surviving path inheritance unit, multiple decoding processing units and multiple storage units. The number of storage units is the same as the number of decoding processing units. The decoder system can be implemented in hardware and / or software and can be configured in an electronic device.

[0034] To facilitate understanding of this invention, the main implementation process of the SCL algorithm can be described first. The main implementation process of the algorithm is as follows:

[0035] Initialization: First, set the initial state of all L paths to 0, and set the path metric (PM) to 0. Bit-by-bit decoding process: Information bit processing: For each information bit, calculate the path metric for each path under both 0 and 1 assumptions. From these 2L possible extended paths, select the L paths with the smallest path metric and retain them. Frozen bit processing: For frozen bits, directly set their value to 0, then calculate the corresponding path metric, and again retain the L paths with the smallest path metric. Path metric calculation: Path metrics are usually represented using the absolute value of LLR (log-likelihood ratio). Path inheritance and pruning: After each processing step, or after processing a fixed number of bits, pruning and inheritance operations are required to retain the L paths with the smallest path metric. Final path selection: After processing all bits, select the path with the smallest path metric from the retained L paths as the final decoding result.

[0036] Regarding the memory copying problem mentioned above, while some hardware implementation strategies have attempted to address and optimize this drawback, such as incremental storage, path sharing, efficient memory architectures, and parallel processing, these only partially alleviate and optimize the problem. Furthermore, they introduce more complex processing logic (new control paths). Therefore, this pain point has not yet been effectively resolved.

[0037] This invention addresses the biggest shortcoming and pain point in the implementation of the SCL algorithm by proposing a path inheritance method that does not require copying memory (from the historical path to the new path) during the path inheritance process, which greatly reduces the latency and power consumption of the decoding process.

[0038] like Figure 1 As shown, the method includes:

[0039] S110. The decoding processing unit obtains the current data to be processed for each information bit, performs decoding processing on the current data to be processed, and determines the current path calculation result.

[0040] In this embodiment, information bits can be understood as the original data bits that need to be transmitted via polar codes in the SCL decoding algorithm. They are the core processing object in the decoding process. In the "bit-by-bit processing" stage of SCL decoding, the algorithm processes each information bit. The data to be processed can be understood as the data used for decoding. The current path calculation result can be understood as the calculation result of the decoded path after SCL decoding, including the path metric, list number, and bit information. The list number represents the "list" as indicated by L in the SCL algorithm. Generally, L represents the number of lists, and L_i represents the index (serial number) of a list. For example, L = 8 indicates that the SCL algorithm supports a maximum of 8 lists.

[0041] Specifically, the decoding processing unit sends read-related control signals to the surviving path inheritance unit for each bit to obtain the current data to be processed from the storage unit, and performs decoding processing on the current data to be processed to determine the current path calculation result.

[0042] For example, the decoding unit implements a basic Polar decoding unit based on the SC algorithm, supporting up to L parallel processing units, which can be distinguished by numbers such as 010, 011, ... This unit is a general-purpose decoding unit, implementing single-bit SC decoding or SC decoding of consecutive multi-bit symbols.

[0043] S120. The path processing unit processes all current path calculation results to obtain the current surviving path calculation result set.

[0044] In this embodiment, the current surviving path calculation result set can be understood as the path remaining after path deletion during the decoding process, which is called the current surviving path, and the corresponding calculation result is the current surviving path calculation result. Multiple current surviving path calculation results constitute the current surviving path calculation result set.

[0045] Specifically, the path processing unit can receive all current path calculation results from the decoding processing unit, sort them according to the path metric value, retain the multiple paths with the smallest path metric value, and retain the same number as the number of decoding processing units. Other paths are deleted, and the remaining results are recorded as the current surviving path calculation results and constitute the current surviving path calculation result set.

[0046] S130. The surviving path inheritance unit establishes a data path relationship between the decoding processing unit and the storage unit based on the historical mapping relationship, so that the decoding processing unit can read the current data to be processed according to the data path relationship.

[0047] In this embodiment, the historical mapping relationship can be understood as the association between the path number of the parent path and the corresponding storage unit in the historical surviving path calculation result of the previous bit. The parent path refers to the original path before path expansion for each surviving path within the L surviving paths (SCL algorithm supporting a maximum of L lists). The path number is the list number mentioned above, used for representation by sequence number. The data path relationship can be understood as indicating the data read / write enable relationship between the decoding processing unit and the storage unit. For example, decoding processing unit L1 reads data from storage unit L3.

[0048] Specifically, the surviving path inheritance unit can determine the matching storage unit from the historical mapping relationship based on the parent path number corresponding to the decoding processing unit, establish the data path relationship between the decoding processing unit and the storage unit, and directly associate the read / write enable and chip select signals of L storage units with the path number to which the parent path belongs, so that the decoding processing unit can read the current data to be processed according to the data path relationship.

[0049] S140. Calculate the result set of the current surviving path to manage the historical mapping relationship and obtain the current mapping relationship.

[0050] In this embodiment, the current mapping relationship can be understood as the updated mapping relationship calculated according to the current surviving path result set.

[0051] Specifically, the surviving path inheritance unit can inherit the intermediate calculation results corresponding to each current surviving path from its parent path, including path metrics, decoded bits of decoded paths, and other information. This inherited information is a value that needs to be stored independently for each path. The surviving path integration unit allocates storage units for this inherited information and establishes a current mapping relationship between the path number of the parent path corresponding to this information and the corresponding storage unit number, thus representing the current surviving path through the path number.

[0052] S150. Store the decoding process calculation results of the parent path specified by the surviving path inheritance unit through the storage unit.

[0053] In this embodiment, the decoding process calculation result can be understood as the intermediate calculation result corresponding to the current surviving path inheriting from its parent path, including path metric value, decoded bits of the decoded path, and other information.

[0054] Specifically, the storage unit can receive the write enable signal from the surviving path inheritance unit and write the decoding process calculation result of the specified parent path into itself for storage. Each storage unit stores a complete list of decoding process calculation data.

[0055] The technical solution of this invention is applied to a decoder system. The system includes: a path processing unit, a surviving path inheritance unit, multiple decoding processing units, and multiple storage units. The number of storage units is the same as the number of decoding processing units. The method includes: obtaining the current data to be processed for each information bit through the decoding processing unit, and performing decoding processing on the current data to be processed to determine the current path calculation result; processing all current path calculation results through the path processing unit to obtain the current surviving path calculation result set; establishing a data path relationship between the decoding processing unit and the storage unit according to the historical mapping relationship through the surviving path inheritance unit, so that the decoding processing unit reads the current data to be processed according to the data path relationship; the historical mapping relationship is the association between the path number of the parent path in the historical surviving path calculation result of the previous bit and the corresponding storage unit; managing the historical mapping relationship according to the current surviving path calculation result set to obtain the current mapping relationship; and storing the decoding process calculation result of the parent path specified by the surviving path inheritance unit through the storage unit. By establishing a mapping relationship, the entire SCL decoding process achieves zero memory copying requirements during path inheritance, avoiding the operation in ordinary SCL decoder implementations where the calculation result of the parent path must be copied to the surviving path during path inheritance. This greatly reduces the processing latency caused by memory copying, as well as the power consumption cost during memory copying.

[0056] Example 2

[0057] Figure 2 This is a flowchart of a data decoding method provided in Embodiment 2 of the present invention. This embodiment is a further refinement of the above embodiment. Figure 2 As shown, the method includes:

[0058] S201. The decoding processing unit obtains input data through the input method in the first information bit, or obtains the current data to be processed through the data path relationship in addition to the first information bit, and performs decoding processing on the current data to be processed to determine the current path calculation result.

[0059] In this embodiment, the first information bit can be understood as the bit corresponding to the first decoding operation. The input data can be understood as the data to be decoded for the first time.

[0060] Specifically, the decoding processing unit can obtain input data as the current data to be processed through external input or other means in the first information bit. Alternatively, apart from the first information bit, it can read the current data to be processed from the storage unit through the data path relationship, and perform decoding processing on the current data to be processed according to the set decoding algorithm to determine the calculation result of the current path.

[0061] Furthermore, based on the above embodiments, the steps for obtaining the current data to be processed through data path relationships can be refined as follows:

[0062] Determine the target storage unit and storage address in the data path relationship; read the decoding calculation result from the target storage unit according to the storage address; use the decoding calculation result as the current data to be processed.

[0063] In this embodiment, the target storage unit can be understood as a unit that stores the decoding process calculation results of the parent path required by the decoding processing unit.

[0064] Specifically, the decoding processing unit can determine the target storage unit and storage address in the data path relationship, read the decoding calculation result from the target storage unit according to the storage address, and use the decoding calculation result as the current data to be processed.

[0065] S202. The path processing unit sorts the calculation results of each current path based on the path metric value to obtain a path sorting result set.

[0066] In this embodiment, the path metric can be understood as a key indicator used to evaluate the reliability of candidate paths. By quantifying the cumulative log-likelihood ratio (LLR) value of each path, the decoding paths are screened and optimized. The path ranking result set can be understood as the path results sorted according to the path metric.

[0067] Specifically, the path processing unit can sort the path metrics in the current path calculation results, for example, by sorting them from smallest to largest or from largest to smallest, to determine the sorted path result set.

[0068] S203. The path sorting result set is reduced according to the number of decoding processing units to obtain the current surviving path calculation result set.

[0069] Specifically, the path processing unit can reduce the path sorting result set according to the number of decoding processing units (e.g., L), retaining the L current paths with the smallest path metric value as the current surviving paths, and reducing the other paths to obtain the current surviving path calculation result set.

[0070] For example, the path processing unit can receive SC decoding outputs from L lists of the decoding processing unit, realizing the decoding of 2L lists (when the decoding processing unit performs single-bit decoding processing) or L*2 lists. M The sorting of the L paths (when the decoding unit performs multi-bit symbol decoding) is based on the path metric value of each sub-path in ascending order. The L paths with the smallest path metric value are retained, and the other paths are removed.

[0071] S204. Determine the path number of the parent path of each current surviving path calculation result in the current surviving path calculation result set through the surviving path inheritance unit.

[0072] Specifically, the path number (i.e. the list number mentioned above) to which the parent path of each current surviving path calculation result belongs is determined through the surviving path inheritance unit.

[0073] S205. Assign the path numbers that are not stored in the path sequence number to the corresponding storage units.

[0074] Specifically, the surviving path inheritance unit can allocate unstored path numbers in the path sequence to the corresponding storage units. This allocation can be done in a manner where one storage unit corresponds to one path number (each path number comes from a specific decoding processing unit, i.e., which decoding processing unit it corresponds to).

[0075] S206. Establish a mapping relationship between unstored path numbers and corresponding storage units to update the historical mapping relationship and obtain the current mapping relationship.

[0076] Specifically, the surviving path inheritance unit can establish a mapping relationship between unstored path numbers and corresponding storage units to update the historical mapping relationship and obtain the current mapping relationship.

[0077] S207. Determine the target path number corresponding to the decoding processing unit.

[0078] In this embodiment, each decoding processing unit corresponds to a target path number.

[0079] S208. Based on the target path number, search in the historical mapping relationship to determine the corresponding target storage unit and storage address.

[0080] Specifically, the surviving path inheritance unit can be searched in the historical mapping relationship based on the target path sequence number to determine the corresponding target storage unit and storage address.

[0081] For example, when the surviving path inheritance unit receives the read control signal from the decoding processing unit L1, the surviving path inheritance unit determines that the target path sequence number list corresponding to L1 is L1, and determines that the target storage unit corresponding to list number L1 is L_RAM4 and its storage address based on the historical mapping relationship.

[0082] S209. The target storage unit and its storage address are used as the data path relationship of the decoding processing unit.

[0083] The technical solution of this invention records the path index (list number) of the parent path during path expansion and reduction in the path processing unit. During path reduction calculation, the path index (list number) of the parent path is directly passed to the surviving path inheritance unit. The surviving path inheritance unit manages the mapping relationship between the storage unit and the parent path index, enabling flexible connection between the decoding processing unit and the storage unit based on this mapping relationship. The read / write enable and chip select signals of L RAMs are directly associated with the list number, allowing subsequent surviving paths to flexibly select RAM based on the inherited list number. Throughout the decoding process, only L RAMs are needed to store the intermediate results of the L lists of parallel decoding calculation units. During the entire SCL decoding process, there is zero memory copying requirement during path inheritance, avoiding the operation in ordinary SCL decoder implementations where the calculation result of the parent path must be copied to the surviving path. This significantly reduces the processing latency caused by memory copying and the power consumption cost during memory copying.

[0084] Example 3

[0085] Figure 3 This is a schematic diagram of a decoder system provided in Embodiment 3 of the present invention. Figure 3 As shown, the system includes: a path processing unit 31, a surviving path inheritance unit 32, multiple decoding processing units 33 and multiple storage units 34, wherein the number of storage units 34 is the same as the number of decoding processing units 33;

[0086] The decoding processing unit 33 is used to obtain the current data to be processed for each information bit, and to perform decoding processing on the current data to be processed to determine the current path calculation result;

[0087] The path processing unit 31 is used to process all the current path calculation results to obtain the current surviving path calculation result set;

[0088] The survivor path inheritance unit 32 is used to establish a data path relationship between the decoding processing unit 33 and the storage unit 34 according to the historical mapping relationship, so that the decoding processing unit 33 reads the current data to be processed according to the data path relationship; the historical mapping relationship is the association between the path number of the parent path and the corresponding storage unit 34 in the historical survivor path calculation result of the previous bit.

[0089] The historical mapping relationships are managed based on the current surviving path calculation result set to obtain the current mapping relationship;

[0090] The storage unit 34 is used to store the decoding process calculation results of the parent path specified by the surviving path inheritance unit 32.

[0091] The technical solution of this invention is applied to a decoder system. The system includes: a path processing unit 31, a surviving path inheritance unit 32, multiple decoding processing units 33, and multiple storage units 34. The number of storage units 34 is the same as the number of decoding processing units 33. The method includes: obtaining the current data to be processed for each information bit through the decoding processing unit 33, and performing decoding processing on the current data to be processed to determine the current path calculation result; processing all current path calculation results through the path processing unit 31 to obtain the current surviving path calculation result set; establishing a data path relationship between the decoding processing unit 33 and the storage units 34 according to the historical mapping relationship through the surviving path inheritance unit 32, so that the decoding processing unit 33 reads the current data to be processed according to the data path relationship; the historical mapping relationship is the association between the path number of the parent path in the historical surviving path calculation result of the previous bit and the corresponding storage unit 34; managing the historical mapping relationship according to the current surviving path calculation result set to obtain the current mapping relationship; and storing the decoding process calculation result of the parent path specified by the surviving path inheritance unit 32 through the storage unit 34. By establishing a mapping relationship, the entire SCL decoding process achieves zero memory copying requirements during path inheritance, avoiding the operation in ordinary SCL decoder implementations where the calculation result of the parent path must be copied to the surviving path during path inheritance. This greatly reduces the processing latency caused by memory copying, as well as the power consumption cost during memory copying.

[0092] Furthermore, the method for obtaining the currently pending data includes:

[0093] Input data is obtained through the input method in the first information bit, or the current data to be processed is obtained through the data path relationship in addition to the first information bit.

[0094] Furthermore, the decoding processing unit 33 is specifically used for:

[0095] Determine the target storage unit 34 and its storage address in the data path relationship;

[0096] The decoding calculation result is read from the target storage unit 34 according to the storage address;

[0097] The result of the decoding process is used as the current data to be processed.

[0098] Furthermore, the path processing unit 31 is specifically used for:

[0099] The calculation results of each current path are sorted based on the path metric to obtain a path sorting result set;

[0100] The path sorting result set is reduced according to the number of decoding processing units 33 to obtain the current surviving path calculation result set.

[0101] Furthermore, the survivor path inheritance unit 32 is specifically used for:

[0102] Determine the path number to which the parent path of each current surviving path calculation result belongs in the current surviving path calculation result set;

[0103] The path numbers that are not stored in the path sequence number are allocated to the corresponding storage unit 34;

[0104] A mapping relationship is established between the unstored path number and the corresponding storage unit 34 to update the historical mapping relationship and obtain the current mapping relationship.

[0105] Furthermore, the survivor path inheritance unit 32 is also specifically used for:

[0106] Determine the path number to which the parent path of each current surviving path calculation result belongs in the current surviving path calculation result set;

[0107] The path numbers that are not stored in the path sequence number are allocated to the corresponding storage unit 34;

[0108] A mapping relationship is established between the unstored path number and the corresponding storage unit 34 to update the historical mapping relationship and obtain the current mapping relationship.

[0109] The decoder system provided in the embodiments of the present invention can execute the data decoding method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0110] Example 4

[0111] Figure 4A schematic diagram of an electronic device 40 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0112] like Figure 4 As shown, the electronic device 40 includes at least one decoder system 41 and a memory, such as a read-only memory (ROM) 42 or a random access memory (RAM) 43, communicatively connected to the at least one decoder system 41. The memory stores computer programs executable by the at least one decoder system. The decoder system 41 can perform various appropriate actions and processes based on the computer program stored in the ROM 42 or loaded from storage unit 48 into the RAM 43. The RAM 43 may also store various programs and data required for the operation of the electronic device 40. The decoder system 41, ROM 42, and RAM 43 are interconnected via a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0113] Multiple components in electronic device 40 are connected to I / O interface 45, including: input unit 46, such as keyboard, mouse, etc.; output unit 47, such as various types of monitors, speakers, etc.; storage unit 48, such as disk, optical disk, etc.; and communication unit 49, such as network card, modem, wireless transceiver, etc. Communication unit 49 allows electronic device 40 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0114] The decoder system 41 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the decoder system 41 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various decoder systems running machine learning model algorithms, digital signal decoder systems (DSPs), and any suitable decoder system, controller, microcontroller, etc. The decoder system 41 performs the various methods and processes described above, such as data decoding methods.

[0115] In some embodiments, the data decoding method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 48. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 40 via ROM 42 and / or communication unit 49. When the computer program is loaded into RAM 43 and executed by decoder system 41, one or more steps of the data decoding method described above may be performed. Alternatively, in other embodiments, decoder system 41 may be configured to perform the data decoding method by any other suitable means (e.g., by means of firmware).

[0116] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable decoder system, which may be a dedicated or general-purpose programmable decoder system, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0117] Computer programs used to implement the methods of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a decoder system of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the decoder system, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The computer programs can be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0118] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0119] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0120] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0121] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0122] In one embodiment, the present invention further includes a computer program product, which includes a computer program that, when executed by a decoder system, implements the data decoding method of any embodiment of the present invention.

[0123] In implementing the computer program product, computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0124] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0125] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A data decoding method, characterized in that, A method is applied to a decoder system, the system comprising: a path processing unit, a surviving path inheritance unit, multiple decoding processing units, and multiple storage units, wherein the number of storage units is the same as the number of decoding processing units, and the method includes: The decoding processing unit acquires the current data to be processed for each information bit, performs SCL decoding calculation on the current data to be processed, and determines the current path calculation result. The path processing unit processes all the current path calculation results to obtain the current surviving path calculation result set; The surviving path inheritance unit establishes a data path relationship between the decoding processing unit and the storage unit based on the historical mapping relationship, so that the decoding processing unit reads the current data to be processed according to the data path relationship; the historical mapping relationship is the association between the path number of the parent path and the corresponding storage unit in the historical surviving path calculation result of the previous bit. The historical mapping relationships are managed based on the current surviving path calculation result set to obtain the current mapping relationship; The storage unit stores the decoding process calculation results of the parent path specified by the surviving path inheritance unit; The step of establishing the data path relationship between the decoding processing unit and the storage unit based on the historical mapping relationship includes: Determine the target path number corresponding to the decoding processing unit; Based on the target path number, the corresponding target storage unit and storage address are determined by searching the historical mapping relationship. The target storage unit and the storage address are used as the data path relationship of the decoding processing unit; The step of managing the historical mapping relationship based on the current surviving path calculation result set to obtain the current mapping relationship includes: Determine the path number to which the parent path of each current surviving path calculation result belongs in the current surviving path calculation result set; Assign the path numbers that are not stored in the path sequence numbers to the corresponding storage units; A mapping relationship is established between the unstored path numbers and their corresponding storage units to update the historical mapping relationship and obtain the current mapping relationship.

2. The method according to claim 1, characterized in that, The methods for obtaining the currently pending data include: Input data is obtained through the input method in the first information bit, or the current data to be processed is obtained through the data path relationship in addition to the first information bit.

3. The method according to claim 2, characterized in that, The step of obtaining the current data to be processed through the data path relationship includes: Determine the target storage unit and storage address in the data path relationship; The decoding process calculation result is read from the target storage unit according to the storage address; The result of the decoding process is used as the current data to be processed.

4. The method according to claim 1, characterized in that, The process of processing all the current path calculation results to obtain the current surviving path calculation result set includes: The current path calculation results are sorted based on the path metric to obtain a path sorting result set; The path sorting result set is reduced according to the number of decoding processing units to obtain the current surviving path calculation result set.

5. A decoder system, characterized in that, include: The system includes a path processing unit, a surviving path inheritance unit, multiple decoding processing units, and multiple storage units, wherein the number of storage units is the same as the number of decoding processing units. The decoding processing unit is used to obtain the current data to be processed for each information bit, and to perform SCL decoding calculation on the current data to be processed to determine the current path calculation result. The path processing unit is used to process all the current path calculation results to obtain the current surviving path calculation result set; The survivor path inheritance unit is used to establish a data path relationship between the decoding processing unit and the storage unit according to the historical mapping relationship, so that the decoding processing unit reads the current data to be processed according to the data path relationship; the historical mapping relationship is the association between the path number of the parent path and the corresponding storage unit in the historical survivor path calculation result of the previous bit. The historical mapping relationships are managed based on the current surviving path calculation result set to obtain the current mapping relationship; The storage unit is used to store the decoding process calculation results of the parent path specified by the surviving path inheritance unit; Specifically, the survivor path inheritance unit is used for: Determine the target path number corresponding to the decoding processing unit; Based on the target path number, the corresponding target storage unit and storage address are determined by searching the historical mapping relationship. The target storage unit and the storage address are used as the data path relationship of the decoding processing unit; The surviving path inheritance unit is further specifically used for: Determine the path number to which the parent path of each current surviving path calculation result belongs in the current surviving path calculation result set; Assign the path numbers that are not stored in the path sequence numbers to the corresponding storage units; A mapping relationship is established between the unstored path numbers and their corresponding storage units to update the historical mapping relationship and obtain the current mapping relationship.

6. An electronic device, characterized in that, The electronic device includes: At least one decoder system; and A memory communicatively connected to the at least one decoder system; wherein, The memory stores a computer program that can be executed by the at least one decoder system to enable the at least one decoder system to perform the data decoding method according to any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by the decoder system, implement the data decoding method of any one of claims 1-4.

8. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a decoder system, implements the data decoding method according to any one of claims 1-4.

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