Bit synchronization method for binary amplitude shift keying system and receiver

Abstract

Embodiments of the present application relate to the technical field of communication, and particularly relate to a bit synchronization method of a binary amplitude shift keying system and a receiver. The bit synchronization method comprises: obtaining bit data and a counting sequence received by the receiver, determining an Nth bit value of an Nth known signal set, determining an Nth counting subset of the counting sequence, and in response to a misalignment between the Nth known signal set corresponding to the Nth bit value and the Nth counting subset, adjusting a bit period of an N+1th bit value so that a bit period of an N+i th bit value is aligned with a counting period of an N+i th counting subset. Embodiments of the present application utilize bit values of known signal sets inserted into a modulated signal sequence to align and correct a modulated signal set and a corresponding counting subset, eliminate a deviation existing in bit synchronization, and ensure that the modulated signal set and the corresponding counting subset can be aligned, which is conducive to improving accuracy when bit decision is made on the modulated signal set.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a bit synchronization method and receiver for a binary amplitude keying system. Background Technology

[0002] Binary Amplitude Shift Keying (2ASK) transmits binary data (0s and 1s) by controlling the amplitude of a carrier signal. During reception, the receiver needs to perform bit synchronization to locate the start and end points of symbols and detect the presence of a carrier signal within a fixed symbol period to determine the symbol value. Interference exists during signal transmission, such as clock skew, jitter, and transmission delay. Over time, this interference can cause deviations in bit synchronization, affecting the receiver's decision. Summary of the Invention

[0003] One objective of this application is to provide a bit synchronization method and receiver for a binary amplitude keying system, thereby improving the bit synchronization deviation in related technologies.

[0004] In a first aspect, embodiments of this application provide a bit synchronization method for a binary amplitude shift keying (BSK) system, applied to a receiver in the BSK system. The bit synchronization method includes: acquiring bit data and a counting sequence received by the receiver, wherein the bit data includes a modulation signal sequence, the modulation signal sequence includes multiple modulation signal sets to be parsed and at least one known signal set that has been parsed, the known signal set being inserted between the multiple modulation signal sets, each known signal set corresponding to a known bit value, and the counting sequence including multiple counting subsets; determining the Nth bit value of the Nth known signal set, the Nth known signal set being the Nth signal set arranged in the modulation signal sequence; determining the Nth counting subset of the counting sequence; and, in response to a misalignment between the Nth known signal set corresponding to the Nth bit value and the Nth counting subset, adjusting the bit period of the (N+1)th bit value so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset, where N is a natural number and i ≥ 2.

[0005] Optionally, the step of adjusting the bit period of the (N+1)th bit value to align the bit period of the (N+i)th bit value with the counting period of the (N+i)th counting subset in response to a misalignment between the Nth known signal set and the Nth counting subset corresponding to the Nth bit value includes: detecting whether a misalignment occurs between the Nth known signal set and the Nth counting subset based on the numerical type of the Nth bit value; and adjusting the bit period of the (N+1)th bit value to align the bit period of the (N+i)th bit value with the counting period of the (N+i)th counting subset in response to a misalignment.

[0006] Optionally, the step of detecting whether a misalignment occurs between the Nth known signal set and the Nth counting subset based on the numerical type of the Nth bit value includes: in response to the numerical type of the Nth bit value being the natural number 0, detecting whether the Nth known signal set first shows a rising edge; if the Nth known signal set shows a rising edge, then determining that a misalignment occurs between the Nth known signal set and the Nth counting subset; if the Nth known signal set does not show a rising edge, then determining that no misalignment occurs between the Nth known signal set and the Nth counting subset.

[0007] Optionally, the Nth known signal set includes a plurality of modulated signals arranged in sequence. The step of detecting whether a misalignment occurs between the Nth known signal set and the Nth counting subset based on the numerical type of the Nth bit value includes: in response to the numerical type of the Nth bit value being the natural number 1, detecting whether the first modulated signal of the Nth known signal set is at a low level; if the first modulated signal of the Nth known signal set remains at a low level for a preset time, then it is determined that a misalignment occurs between the Nth known signal set and the Nth counting subset; if the first modulated signal of the Nth known signal set does not remain at a low level for a preset time, then it is determined that no misalignment occurs between the Nth known signal set and the Nth counting subset.

[0008] Optionally, the step of adjusting the bit period of the (N+1)th bit value in response to a misalignment between the Nth known signal set and the Nth counting subset, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset, includes: calculating a misalignment time based on the numerical type of the Nth bit value; and adjusting the bit period of the (N+1)th bit value based on the misalignment time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset.

[0009] Optionally, calculating the misalignment time based on the numerical type of the Nth bit value includes: recording the first time when the rising edge of the Nth known signal set first appears in response to the numerical type of the Nth bit value being the natural number 0; determining the end point of the counting period of the Nth counting subset corresponding to the Nth known signal set as the second time; and subtracting the first time from the second time to obtain the misalignment time.

[0010] Optionally, the step of calculating the misalignment time based on the numerical type of the Nth bit value includes: in response to the numerical type of the Nth bit value being the natural number 1, calculating the starting point of the counting period of the Nth counting subset corresponding to the Nth known signal set as the third time; recording the fourth time when the Nth known signal set first appears with a rising edge; and subtracting the third time from the fourth time to obtain the misalignment time.

[0011] Optionally, adjusting the bit period of the (N+1)th bit value according to the misalignment time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset, includes: in response to the misalignment time being greater than a preset time threshold and the value type of the Nth bit value being the natural number 0, subtracting the bit period from the misalignment time to obtain a first target time; updating the bit period of the (N+1)th bit value to the first target time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset.

[0012] Optionally, adjusting the bit period of the (N+1)th bit value according to the misalignment time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset, includes: in response to the misalignment time being greater than a preset time threshold and the value type of the Nth bit value being the natural number 1, adding the bit period to the misalignment time to obtain a second target time; updating the bit period of the (N+1)th bit value to the second target time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset.

[0013] In a second aspect, embodiments of this application provide a receiver, including: a memory and a processor, the memory being connected to the processor, the processor being configured to execute one or more computer programs stored in the memory, wherein when the processor executes the one or more computer programs, the receiver implements the bit synchronization method of the binary amplitude keying system described above.

[0014] The embodiments of this application can achieve the following technical effects: The embodiments of this application use the bit values ​​of the known signal set inserted into the modulation signal sequence to perform alignment correction on the modulation signal set and its corresponding counting subset, eliminate the deviation in bit synchronization, and ensure that the modulation signal set and its corresponding counting subset can be aligned, which is beneficial to improving the accuracy of bit decision on the modulation signal set. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A timing diagram of the modulation signal, count value, and symbol relationships provided for related technologies; Figure 2 A schematic flowchart illustrating a bit synchronization method for a binary amplitude keying system provided in this application embodiment; Figure 3 This is a schematic diagram illustrating the distribution between the known signal set and the modulation signal set provided in the embodiments of this application; Figure 4 A schematic diagram illustrating the distribution between a known signal set and a modulated signal set, provided for another embodiment of this application; Figure 5 A signal timing diagram for bit synchronization hysteresis provided in an embodiment of this application; Figure 6 This application provides a signal timing diagram for a bit synchronization lead scenario in an embodiment of the present application. Figure 7 A schematic diagram of the structure of a bit synchronization device for a binary amplitude keying system provided in this application embodiment; Figure 8 This is a schematic diagram of a receiver provided in an embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0018] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0019] A bit is the smallest unit of information and the basic unit for describing "information quantity" in digital communication. A bit can take two values: 0 or 1.

[0020] A symbol (also known as a bit symbol) is the actual physical unit transmitted in the channel of a communication system, used to "carry bit information". In a 2ASK communication system, a symbol has only two states: state 1, which means the carrier is transmitted (corresponding to bit "1"); and state 0, which means the carrier is not transmitted (corresponding to bit "0").

[0021] A symbol can consist of one or more modulation signals. When the symbol is 1, the modulation signal is a carrier signal, which can be regarded as a PWM signal. When the symbol is 0, the modulation signal is low.

[0022] The bit period refers to the duration during which a symbol (or bit) is 0 or 1. The bit period consists of the time of one or more modulated signals.

[0023] Please see Figure 1 `data_rev` represents the modulated signal actually received by the receiver. `data_bit_cnt` represents the receiver's counter counting the modulated signal contained in each symbol `data` (or bit). A count value of 0 indicates the start of the bit, and a count value of T-1 indicates the end of the bit. The counter is reset to zero after each bit cycle.

[0024] 1) Normal situation: like Figure 1 As shown, the bit start of each symbol data corresponds to the count value 0, and the bit end of each symbol data corresponds to the count value T-1. The bit period is T, meaning that one symbol data contains T modulation signals.

[0025] like Figure 1As shown, T is 6. When the symbol data is 1, the symbol data consists of 6 PWM signals. After each bit cycle, the counter is reset to start counting another symbol data. When the symbol data is 0, the symbol data consists of 6 modulation signals, all of which are low level.

[0026] 2) Lagging situation: data_rev_late represents a synchronously delayed modulation signal. Relative to the symbol data being 1, the timing start point lags behind the actual symbol. The actual part of the carrier signal has already entered the decision period of symbol 0, which will affect the decision of two adjacent bits.

[0027] 3) Advanced scenario: data_rev_pre represents a synchronously leading modulation signal. Relative to the symbol data being 1, the timing start point is ahead of the actual symbol, causing the actual carrier signal to shift and affecting the decision of that symbol.

[0028] Both delayed and advanced conditions can interfere with symbol decision-making to some extent and need to be corrected during reception.

[0029] The following embodiments of this application provide a bit synchronization method for a binary amplitude keying (BSK) system, applied to a receiver in a BSK system. Please refer to... Figure 2 The bit synchronization method in this application embodiment is implemented through steps S21 to S24, as detailed below: Step S21: Obtain the bit data and counting sequence received by the receiver.

[0030] The bit data includes a modulated signal sequence, which includes multiple sets of modulated signals to be parsed and at least one known set of signals that has already been parsed.

[0031] The bit period of the modulation signal set is the same as that of the known signal set. The modulation signal set includes multiple modulation signals, which can be PWM signals or low-level signals. The bit values ​​corresponding to the modulation signal set can be obtained by subsequent sampling and decision. When all the modulation signals in the modulation signal set are PWM signals, the bit value corresponding to the modulation signal set is 1; when all the modulation signals in the modulation signal set are low-level signals, the bit value corresponding to the modulation signal set is 0.

[0032] A known signal set is inserted between multiple modulated signal sets, and the bit value corresponding to each known signal set is a known value. For example, a known signal set has a bit value of 1, and in this embodiment, this known signal set is inserted between two modulated signal sets. A known signal set has a bit value of 0, and in this embodiment, this known signal set is inserted between two modulated signal sets.

[0033] Please see Figure 3 Given that the bit value of signal set A1 is 1, the bit value of signal set A2 is 0, and the bit value of signal set A3 is 1. In this embodiment, the known signal sets A1, A2, and A3 are sequentially inserted between the modulation signal set B15 and the modulation signal B16.

[0034] Given that the bit values ​​of signal set A4 are 1 and the bit values ​​of signal set A5 are 0, this embodiment inserts known signal sets A4 and A5 sequentially between modulation signal set B50 and modulation signal B51. This embodiment can utilize the bit values ​​of the known signal sets to correct the alignment between the modulation signal set to be parsed and the counting subset.

[0035] The counting sequence comprises multiple counting subsets. The receiver's counter resets to zero after counting one modulated signal set or one known signal set, and then begins counting another modulated signal set or another known signal set. Each counting subset corresponds to one signal set, which can be either a modulated signal set or a known signal set.

[0036] The total value of the count subset is consistent with the bit period. For example, when the bit period is 6, the total value is 6, and when the bit period is 7, the total value is 7.

[0037] Please see Figure 4 The modulated signal set B1 corresponds to the counting subset C1, the modulated signal set B15 corresponds to the counting subset C15, the known signal set A1 corresponds to the counting subset C16, the known signal set A2 corresponds to the counting subset C17, the known signal set A3 corresponds to the counting subset C18, the modulated signal B16 corresponds to the counting subset C19, the modulated signal B50 corresponds to the counting subset C53, the known signal set A4 corresponds to the counting subset C54, the known signal set A5 corresponds to the counting subset C55, and the modulated signal B51 corresponds to the counting subset C56.

[0038] In some embodiments, the bit data further includes header data, which is data arranged before the modulated signal sequence. The header data can be frame header data or a fixed signal sequence, where the bit values ​​of the fixed signal sequence are known. Embodiments of this application perform preliminary bit synchronization operations based on the header data to align and correct each signal set with its corresponding count subset.

[0039] The initial data and the modulated signal sequence are sequential in time. Once the initial data is aligned with its corresponding counting subset, it is relatively easy to align each signal set in the modulated signal sequence with its corresponding counting subset. This embodiment performs a preliminary bit synchronization operation based on the initial data, initially completing the alignment correction between each signal set and its corresponding counting subset. This facilitates more accurate and reliable subsequent alignment correction of each signal set with its corresponding counting subset.

[0040] Step S22: Determine the Nth bit value of the Nth known signal set.

[0041] The Nth known signal set is either the Nth signal set arranged in the modulation signal sequence or the signal set corresponding to the Nth bit period. Please refer to... Figure 4 Given signal set A1 is the 16th signal set, and the bit value of signal set A1 is 1, and the bit value of the 16th bit is 1. Given signal set A2 is the 17th signal set, and the bit value of signal set A2 is 0, and the bit value of the 17th bit is 0. Given signal set A3 is the 18th signal set, and the bit value of signal set A3 is 1, and the bit value of the 18th bit is 1.

[0042] Step S23: Determine the Nth counting subset of the counting sequence.

[0043] The Nth counting subset is the counting subset corresponding to the Nth counting cycle. Please combine this with... Figure 4 Given that the counting subset C16 corresponding to signal set A1 is the 16th counting subset, the counting subset C17 corresponding to signal set A2 is the 17th counting subset, and the counting subset C18 corresponding to signal set A3 is the 18th counting subset.

[0044] Step S24: In response to the misalignment between the Nth known signal set corresponding to the Nth bit value and the Nth counting subset, adjust the bit period of the (N+1)th bit value so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset, where N is a natural number and i≥2.

[0045] This application embodiment utilizes the bit values ​​of a known signal set inserted into the modulation signal sequence to perform alignment correction on the modulation signal set and its corresponding counting subset, eliminating the deviation in bit synchronization and ensuring that the modulation signal set and its corresponding counting subset can be aligned. This helps to improve the accuracy of bit decision-making on the modulation signal set.

[0046] In this embodiment of the application, steps S241 to S242 are used to adjust the bit period of the (N+1)th bit value so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset, as shown below: Step S241: Based on the numerical type of the Nth bit value, detect whether there is a misalignment between the Nth known signal set and the Nth counting subset.

[0047] The value of the Nth bit can be 0 or 1. In this application, different methods are used to detect whether there is a misalignment between the Nth known signal set and the Nth counting subset for different value types.

[0048] ① Method for detecting misalignment when the value of the Nth bit is a natural number 0 When the value of the Nth bit is a natural number 0, this embodiment uses steps S2411 to S2413 to detect whether there is a misalignment between the Nth known signal set and the Nth counting subset based on the value of the Nth bit, as shown below: Step S2411: In response to the fact that the value of the Nth bit is of the natural number 0, detect whether the Nth known signal set has its first rising edge.

[0049] Step S2412: If a rising edge appears in the Nth known signal set, then it is determined that there is a misalignment between the Nth known signal set and the Nth counting subset.

[0050] Step S2413: If the Nth known signal set does not have a rising edge, then it is determined that there is no misalignment between the Nth known signal set and the Nth counting subset.

[0051] In step S2411, the Nth bit of the Nth known signal set is 0. Under normal circumstances, the modulation signals contained in the Nth known signal set are all at low levels. When the Nth known signal set has a rising edge (i.e., a high level), the Nth known signal set is abnormal. When the Nth known signal set does not have a rising edge (i.e., a high level), the Nth known signal set is in a normal state. All signal sets arranged in the Nth known signal set are aligned with their corresponding counting subsets. Therefore, this embodiment of the application uses this feature to detect whether there is a misalignment between the Nth known signal set and the Nth counting subset.

[0052] In step S2412, when the Nth known signal set has a rising edge (i.e., a high level), a misalignment occurs between the Nth known signal set and the Nth counting subset.

[0053] Please see Figure 5 A rising edge occurs at the Nth known signal set 51 at 52, and a misalignment occurs between the Nth known signal set 51 and the Nth counting subset 53.

[0054] In step S2413, when the Nth known signal set does not have a rising edge, there is no misalignment between the Nth known signal set and the Nth counting subset.

[0055] In this embodiment of the application, when the bit value of the known signal set is 0, it detects whether there is a misalignment between the Nth known signal set and the Nth counting subset, so as to perform alignment correction on the subsequent signal sets and their corresponding counting subsets in advance.

[0056] ② Method for detecting misalignment when the value of the Nth bit is a natural number 1 When the value of the Nth bit is a natural number 1, this embodiment uses steps S2414 to S2416 to detect whether there is a misalignment between the Nth known signal set and the Nth counting subset based on the value of the Nth bit, as shown below: Step S2414: In response to the fact that the value of the Nth bit is of the natural number 1, detect whether the first modulation signal of the Nth known signal set is low.

[0057] Step S2415: If the first modulation signal of the Nth known signal set remains at a low level for a preset time, then it is determined that there is a misalignment between the Nth counting subset of the Nth known signal set.

[0058] Step S2416: If the first modulation signal of the Nth known signal set does not remain at a low level for a preset time, then it is determined that there is no misalignment between the Nth known signal set and the Nth counting subset.

[0059] In step S2414, the Nth known signal set includes multiple modulated signals arranged in sequence. The Nth bit of the Nth known signal set is 1. Under normal circumstances, the modulated signals included in the Nth known signal set are all PWM signals. When the first modulated signal of the Nth known signal set is continuously low for a preset time, the Nth known signal set is abnormal. When the first modulated signal of the Nth known signal set is not continuously low for a preset time, the Nth known signal set is in a normal state. All signal sets arranged in the Nth known signal set are aligned with their corresponding counting subsets. Therefore, this embodiment of the application utilizes this feature to detect whether there is a misalignment between the Nth known signal set and the Nth counting subset.

[0060] In step S2415, when the first modulation signal of the Nth known signal set remains at a low level for a preset time, a misalignment occurs between the Nth known signal set and the Nth counting subset.

[0061] Please see Figure 6 The first modulation signal 62 of the Nth known signal set 61 is at a low level, and there is a misalignment between the Nth known signal set 61 and the Nth counting subset 63.

[0062] In step S2416, if the first modulation signal of the Nth known signal set does not remain at a low level for a preset time, there is no misalignment between the Nth known signal set and the Nth counting subset.

[0063] In this embodiment of the application, when the bit value of the known signal set is 1, it detects whether there is a misalignment between the Nth known signal set and the Nth counting subset, so as to perform alignment correction on the subsequent signal sets and their corresponding counting subsets in advance.

[0064] Step S242: In response to the misalignment between the Nth known signal set and the Nth counting subset, adjust the bit period of the (N+1)th bit value so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset.

[0065] In this embodiment of the application, when a misalignment occurs between the Nth known signal set and the Nth counting subset, steps S2421 to S2422 are used to adjust the bit period of the (N+1)th bit value so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset, as detailed below: Step S2421: In response to a misalignment between the Nth known signal set and the Nth count subset, calculate the misalignment time based on the numerical type of the Nth bit value.

[0066] The value of the Nth bit can be 0 or 1. In this embodiment, the misalignment time is calculated for different value types.

[0067] ① Method for calculating the misalignment time when the value of the Nth bit is a natural number 0 When the value of the Nth bit is a natural number 0, steps S24211 to S24213 of this embodiment calculate the misalignment time based on the value of the Nth bit, as shown below: Step S24211: In response to the fact that the value of the Nth bit is of the natural number 0, record the first time when the rising edge of the Nth known signal set first appears.

[0068] Please combine Figure 5 The first time when the rising edge of the Nth known signal set first appears is recorded as t1.

[0069] Step S24212: Determine the end point of the counting period of the Nth counting subset corresponding to the Nth known signal set as the second time.

[0070] Please combine Figure 5 The second time is t2.

[0071] Step S24213: Subtract the first time from the second time to obtain the misalignment time.

[0072] Please combine Figure 5 The misalignment time t_late_0 = t2 - t1.

[0073] In this embodiment of the application, when the bit value of the known signal set is 0, the misalignment time is obtained by calculating the duration of the rising edge of the corresponding bit period.

[0074] ② Method for calculating the misalignment time when the value of the Nth bit is a natural number 1 When the value of the Nth bit is a natural number 1, steps S24214 to S24216 of this embodiment calculate the misalignment time based on the value of the Nth bit, as shown below: In step S24214, in response to the fact that the value type of the Nth bit is the natural number 1, the starting point of the counting period of the Nth counting subset corresponding to the Nth known signal set is calculated as the third time.

[0075] Please combine Figure 6 The third time corresponding to the starting point is t3.

[0076] Step S24215: Record the fourth time when the rising edge of the Nth known signal set first appears.

[0077] Please combine Figure 6 The fourth time when the rising edge first appears in the Nth known signal set is t4.

[0078] Step S24216: Subtract the third time from the fourth time to obtain the misalignment time.

[0079] The misalignment time t_pre_1 = t4 - t3.

[0080] In this embodiment of the application, when the bit value of the known signal set is 1, the misalignment time is obtained by calculating the duration of the rising edge of the corresponding bit period.

[0081] Step S2422: Adjust the bit period of the (N+1)th bit value according to the misalignment time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset.

[0082] The value of the Nth bit can be 0 or 1. In this embodiment, the misalignment time is calculated for different value types.

[0083] ① When the value of the Nth bit is a natural number 0, adjust the bit period of the (N+1)th bit. When the value of the Nth bit is a natural number 0, this embodiment uses steps S24221 to S24222 to adjust the bit period of the (N+1)th bit according to the misalignment time, so that the bit period of the (N+i)th bit is aligned with the counting period of the (N+i)th counting subset, as shown below: Step S24221: In response to the misalignment time being greater than a preset time threshold and the value of the Nth bit being a natural number 0, the bit period is subtracted from the misalignment time to obtain the first target time.

[0084] The preset time threshold is customized by the designer based on engineering experience. Considering channel interference, the Nth known signal set and the Nth counting subset are not strictly aligned and are prone to slight deviations, but these slight deviations will not cause misjudgments in bit decision-making. To improve the robustness of signal alignment correction, this embodiment sets a preset time threshold. When the misalignment time is greater than the preset time threshold, the deviation between the Nth known signal set and the Nth counting subset exceeds the allowable range; when the misalignment time is less than the preset time threshold, the deviation between the Nth known signal set and the Nth counting subset exceeds the allowable range. Please combine Figure 5 When the misalignment time exceeds the preset time threshold, the first target time tk = T - t_late_0.

[0085] Step S24222: Update the bit period of the (N+1)th bit value to the first target time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset.

[0086] Referring to point 5, the bit period of the (N+1)th bit value is set to tk, meaning the (N+1)th counting period corresponding to the (N+1)th bit value is set to tk. The bit period of the (N+2)th bit value is restored to its original bit period, or the counting period of the (N+2)th counting subset is restored to its original counting period. Therefore, not only is the (N+2)th signal set aligned with the (N+2)th counting subset according to its original bit period, but the (N+i)th signal set following the (N+2)th signal set is also aligned with the (N+i)th counting subset following the (N+2)th counting subset according to its original bit period.

[0087] In the embodiment of this application, when the value of the Nth bit is a natural number 0, the bit period of the N+1th bit can be adjusted only when the misalignment time is greater than the preset time threshold by comparing the misalignment time with the preset time threshold. This allows the subsequent signal set and the counting subset to be aligned, thus avoiding the need for excessively frequent bit alignment operations caused by minor deviations due to signal noise interference.

[0088] ② Method for detecting misalignment when the value of the Nth bit is a natural number 1 When the value of the Nth bit is a natural number 1, this embodiment uses steps S24223 to S24224 to adjust the bit period of the (N+1)th bit according to the misalignment time, so that the bit period of the (N+i)th bit is aligned with the counting period of the (N+i)th counting subset, as shown below: In step S24223, in response to the misalignment time being greater than a preset time threshold and the value of the Nth bit being of the natural number 1, the bit period is added to the misalignment time to obtain the second target time.

[0089] Please combine Figure 6 When the misalignment time exceeds the preset time threshold, the second target time tr = T + t_pre_1.

[0090] Step S24224: Update the bit period of the (N+1)th bit value to the second target time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset.

[0091] Referring to point 6, the bit period of the (N+1)th bit value is set to tr, meaning the (N+1)th counting period corresponding to the (N+1)th bit value is set to tr. The bit period of the (N+2)th bit value is restored to its original bit period, or the counting period of the (N+2)th counting subset is restored to its original counting period. Therefore, not only is the (N+2)th signal set aligned with the (N+2)th counting subset according to its original bit period, but the (N+i)th signal set following the (N+2)th signal set is also aligned with the (N+i)th counting subset following the (N+2)th counting subset according to its original bit period.

[0092] In the embodiment of this application, when the value of the Nth bit is a natural number 1, the bit period of the N+1th bit can be adjusted only when the misalignment time is greater than the preset time threshold by comparing the misalignment time with the preset time threshold. This allows the subsequent signal set and the counting subset to be aligned, thus avoiding the need for excessively frequent bit alignment operations caused by small deviations due to signal noise interference.

[0093] It should be noted that in the above embodiments, there is no necessarily a certain order between the steps. Those skilled in the art can understand from the description of the embodiments of this application that the above steps may have different execution orders in different embodiments, that is, they may be executed in parallel or in turn, etc.

[0094] As another aspect of the embodiments of this application, this application provides a bit synchronization device for a binary amplitude keying system. The bit synchronization device for the binary amplitude keying system can be a software module. This software module includes several instructions stored in a memory. A processor can access the memory, call the instructions, and execute them to complete the bit synchronization method for the binary amplitude keying system described in the various embodiments above.

[0095] In some implementations, the bit synchronization device of the binary amplitude keying (BSK) system can also be constructed from hardware devices. For example, the bit synchronization device of the BSK system can be constructed from one or more chips, which can work in coordination to complete the bit synchronization method of the BSK system described in the various implementations above. As another example, the bit synchronization device of the BSK system can also be constructed from various logic devices, such as general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), microcontrollers, ARM (Acorn RISC Machine) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components.

[0096] Please see Figure 7 The bit synchronization device 700 of the binary amplitude keying system includes a data acquisition module 71, a bit value determination module 72, a count value determination module 73, and a period adjustment module 74.

[0097] Data acquisition module 71 is used to acquire bit data and a counting sequence received by the receiver. The bit data includes a modulation signal sequence, which includes multiple modulation signal sets to be parsed and at least one known signal set that has been parsed. The known signal set is inserted between the multiple modulation signal sets, and the bit value corresponding to each known signal set is a known value. The counting sequence includes multiple counting subsets. Bit value determination module 72 is used to determine the Nth bit value of the Nth known signal set, which is the Nth signal set arranged in the modulation signal sequence. Count value determination module 73 is used to determine the Nth counting subset of the counting sequence. Period adjustment module 74 is used to adjust the bit period of the (N+1)th bit value in response to a misalignment between the Nth known signal set corresponding to the Nth bit value and the Nth counting subset, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset, where N is a natural number and i ≥ 2.

[0098] In some embodiments, the period adjustment module 74 is specifically configured to: detect whether there is a misalignment between the Nth known signal set and the Nth counting subset according to the numerical type of the Nth bit value; and adjust the bit period of the (N+1)th bit value in response to the misalignment between the Nth known signal set and the Nth counting subset, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset.

[0099] In some embodiments, the period adjustment module 74 is specifically configured to: in response to the fact that the value of the Nth bit is of the natural number 0, detect whether the Nth known signal set has a rising edge for the first time; if the Nth known signal set has a rising edge, determine that there is a misalignment between the Nth known signal set and the Nth counting subset; if the Nth known signal set does not have a rising edge, determine that there is no misalignment between the Nth known signal set and the Nth counting subset.

[0100] In some embodiments, the Nth known signal set includes a plurality of modulated signals arranged in sequence, and the period adjustment module 74 is specifically configured to: in response to the value type of the Nth bit value being a natural number 1, detect whether the first modulated signal of the Nth known signal set is low; if the first modulated signal of the Nth known signal set is continuously low for a preset time, determine that there is a misalignment between the Nth known signal set and the Nth counting subset; if the first modulated signal of the Nth known signal set is not continuously low for a preset time, determine that there is no misalignment between the Nth known signal set and the Nth counting subset.

[0101] In some embodiments, the period adjustment module 74 is specifically configured to: in response to a misalignment between the Nth known signal set and the Nth counting subset, calculate the misalignment time according to the numerical type of the Nth bit value; and adjust the bit period of the (N+1)th bit value according to the misalignment time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset.

[0102] In some embodiments, the period adjustment module 74 is specifically configured to: in response to the fact that the value of the Nth bit is of the natural number 0, record the first time when the rising edge of the Nth known signal set first appears; determine the end point of the counting period of the Nth counting subset corresponding to the Nth known signal set as the second time; and subtract the first time from the second time to obtain the misalignment time.

[0103] In some embodiments, the period adjustment module 74 is specifically configured to: in response to the fact that the value type of the Nth bit value is the natural number 1, calculate the starting point of the counting period of the Nth counting subset corresponding to the Nth known signal set as the third time; record the fourth time when the Nth known signal set first appears with a rising edge; and subtract the third time from the fourth time to obtain the misalignment time.

[0104] In some embodiments, the period adjustment module 74 is specifically configured to: in response to the misalignment time being greater than a preset time threshold and the value type of the Nth bit value being a natural number 0, subtract the bit period from the misalignment time to obtain a first target time; update the bit period of the (N+1)th bit value to the first target time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset.

[0105] In some embodiments, the period adjustment module 74 is specifically configured to: in response to the misalignment time being greater than a preset time threshold and the value type of the Nth bit value being a natural number 1, add the bit period to the misalignment time to obtain a second target time; update the bit period of the (N+1)th bit value to the second target time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset.

[0106] It should be noted that the bit synchronization device of the aforementioned binary amplitude keying system can execute the bit synchronization method of the binary amplitude keying system provided in the embodiments of this application, and has the corresponding functional modules and beneficial effects of the method. Technical details not described in detail in the embodiments of the bit synchronization device of the binary amplitude keying system can be found in the bit synchronization method of the binary amplitude keying system provided in the embodiments of this application.

[0107] See Figure 8 , Figure 8 This is a schematic diagram of a receiver provided in an embodiment of this application. The receiver 800 includes one or more processors 81 and a memory 82. The memory 82 is connected to one or more processors 81, for example, via a bus.

[0108] Processor 81 is configured to support the receiver in performing the corresponding functions in the methods described in the above method embodiments. The processor may be a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof. The aforementioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0109] Memory 82 is used to store program code, etc. Memory may include volatile memory (VM), such as random access memory (RAM); memory may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); memory may also include combinations of the above types of memory.

[0110] The memory 82 can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the bit synchronization method of the binary amplitude keying system in the embodiments of this application. The processor executes the non-volatile software programs, instructions, and modules stored in the memory to perform various functional applications and data processing of the bit synchronization method and bit synchronization device of the binary amplitude keying system, thereby realizing the functions of the various modules or units of the bit synchronization method and bit synchronization device of the binary amplitude keying system provided in the above method embodiments.

[0111] The memory may include a program storage area and a data storage area, wherein the program storage area may store the operating system and application programs required for at least one function. The data storage area may store data created based on the use of the bit synchronization device of the binary amplitude keying system. In some embodiments, the memory may optionally include memory remotely located relative to the processor, which can be connected to the bit synchronization device of the binary amplitude keying system via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0112] The one or more modules are stored in the memory. When executed by the one or more processors, they perform the bit synchronization method of the binary amplitude keying system in any of the above method embodiments. For example, they perform the method steps described in the above method embodiments to realize the functions of the modules described in the above device embodiments.

[0113] This application also provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a receiver, cause the receiver to perform the method described in the foregoing embodiments.

[0114] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0115] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A bit synchronization method for a binary amplitude keying (BSK) system, applied to the receiver of the BSK system, characterized in that, The bit synchronization method includes: The receiver receives bit data and a counting sequence. The bit data includes a modulation signal sequence, which includes multiple modulation signal sets to be parsed and at least one known signal set that has been parsed. The known signal set is inserted between the multiple modulation signal sets, and the bit value corresponding to each known signal set is a known value. The counting sequence includes multiple counting subsets. Determine the Nth bit value corresponding to the Nth known signal set, wherein the Nth known signal set is the Nth signal set arranged in the modulation signal sequence, and the bit period of the modulation signal set is the same as the bit period of the known signal set; Determine the Nth counting subset of the counting sequence, wherein the total value of each counting subset is consistent with the bit period of the known signal set; In response to the misalignment between the Nth known signal set corresponding to the Nth bit value and the Nth counting subset, the bit period of the (N+1)th bit value is adjusted so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset, where N is a natural number greater than or equal to 3 and i ≥ 2.

2. The bit synchronization method according to claim 1, characterized in that, The step of adjusting the bit period of the (N+1)th bit value to align the bit period of the (N+i)th bit value with the counting period of the (N+i)th counting subset in response to a misalignment between the Nth known signal set corresponding to the Nth bit value includes: Based on the numerical type of the Nth bit value, detect whether there is a misalignment between the Nth known signal set and the Nth count subset; In response to a misalignment between the Nth known signal set and the Nth counting subset, the bit period of the (N+1)th bit value is adjusted so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset.

3. The bit synchronization method according to claim 2, characterized in that, The step of detecting whether there is a misalignment between the Nth known signal set and the Nth count subset based on the numerical type of the Nth bit value includes: In response to the fact that the value of the Nth bit is of the natural number 0, detect whether the Nth known signal set has its first rising edge; If a rising edge appears in the Nth known signal set, then it is determined that there is a misalignment between the Nth known signal set and the Nth counting subset; If the Nth known signal set does not have a rising edge, then it is determined that there is no misalignment between the Nth known signal set and the Nth counting subset.

4. The bit synchronization method according to claim 2, characterized in that, The Nth known signal set includes multiple modulated signals arranged in sequence. The step of detecting whether there is a misalignment between the Nth known signal set and the Nth counting subset based on the numerical type of the Nth bit value includes: In response to the fact that the value of the Nth bit is of the natural number 1, it is detected whether the first modulation signal of the Nth known signal set is low. If the first modulation signal of the Nth known signal set remains at a low level for a preset time, then it is determined that there is a misalignment between the Nth known signal set and the Nth counting subset. If the first modulation signal of the Nth known signal set does not remain at a low level for a preset time, then it is determined that there is no misalignment between the Nth known signal set and the Nth counting subset.

5. The bit synchronization method according to claim 2, characterized in that, The response to a misalignment between the Nth known signal set and the Nth counting subset, adjusting the bit period of the (N+1)th bit value to align the bit period of the (N+i)th bit value with the counting period of the (N+i)th counting subset, includes: In response to a misalignment between the Nth known signal set and the Nth count subset, the misalignment time is calculated based on the numerical type of the Nth bit value; Adjust the bit period of the (N+1)th bit value according to the misalignment time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset.

6. The bit synchronization method according to claim 5, characterized in that, The calculation of the misalignment time based on the numerical type of the Nth bit value includes: In response to the fact that the value of the Nth bit is of the natural number 0, the first time when the rising edge of the Nth known signal set first appears is recorded. The end point of the counting period of the Nth counting subset corresponding to the Nth known signal set is determined as the second time. Subtracting the first time from the second time yields the misalignment time.

7. The bit synchronization method according to claim 5, characterized in that, The calculation of the misalignment time based on the numerical type of the Nth bit value includes: In response to the fact that the value of the Nth bit is of the natural number 1, the starting point of the counting period of the Nth counting subset corresponding to the Nth known signal set is the third time. Record the fourth time when the rising edge first appears in the Nth known signal set; Subtracting the third time from the fourth time yields the misalignment time.

8. The bit synchronization method according to claim 5, characterized in that, The step of adjusting the bit period of the (N+1)th bit value according to the misalignment time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset, includes: In response to the misalignment time being greater than a preset time threshold and the value of the Nth bit being of the natural number 0, the bit period is subtracted from the misalignment time to obtain the first target time; The bit period of the (N+1)th bit value is updated to the first target time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset.

9. The bit synchronization method according to claim 5, characterized in that, The step of adjusting the bit period of the (N+1)th bit value according to the misalignment time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset, includes: In response to the misalignment time being greater than a preset time threshold, and the value of the Nth bit being of the natural number 1, the bit period is added to the misalignment time to obtain the second target time; The bit period of the (N+1)th bit value is updated to the second target time, so that the bit period of the (N+i)th bit value is aligned with the counting period of the (N+i)th counting subset.

10. A receiver, characterized in that, include: A memory and a processor, the memory being connected to the processor, the processor being configured to execute one or more computer programs stored in the memory, wherein, when executing the one or more computer programs, the processor causes the receiver to implement the bit synchronization method of the binary amplitude keying system as described in any one of claims 1-9.

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