A solar cell and a photovoltaic module

Abstract

This invention relates to a solar cell and a photovoltaic module. The solar cell includes a silicon substrate, a first semiconductor layer, and a conductive layer. The first semiconductor layer is disposed on at least one surface of the silicon substrate. The conductive layer is disposed on the side of the first semiconductor layer facing away from the silicon substrate. At least a portion of the surface region of the silicon substrate has a pyramid structure. The first semiconductor layer is deposited conformally on the surface of the silicon substrate, and the conductive layer is deposited conformally on the side of the first semiconductor layer away from the silicon substrate. The thickness of the conductive layer at the ridges of the pyramid structure is greater than the thickness of the conductive layer at the slopes of the pyramid structure. This design allows for a larger proportion of the thinner conductive layer, reducing parasitic and resonant absorption phenomena, thereby improving the light utilization efficiency of the solar cell. The larger proportion of the thinner conductive layer also allows for a larger area for light to pass through, improving the optical performance of the solar cell.

Description

[0001] This application claims priority to Chinese Patent Application No. 2025115767033, filed with the Chinese Patent Office on October 30, 2025, entitled “A Solar Cell and a Photovoltaic Module”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of solar photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Technology

[0003] Solar cells are devices that directly convert light energy into electrical energy. Related technologies involve first fabricating a patterned passivation layer and a doped polycrystalline silicon layer on the surface of the solar cell, then depositing another passivation layer and a doped amorphous silicon layer on the entire back side of the solar cell. Next, the partially doped amorphous silicon layer above the doped polycrystalline silicon is opened up, and then a transparent conductive layer and electrodes are used to conduct electricity of different electrical properties, thus enabling the solar cell to generate electricity.

[0004] Currently, the conductive layer on the surface of solar cells is generally thick, which can lead to parasitic absorption defects and resonant absorption defects, affecting the performance of solar cells. Summary of the Invention

[0005] In view of this, the present invention proposes a solar cell and a photovoltaic module, which aims to partially or completely solve the technical problems of parasitic absorption defects and resonant absorption defects in existing solar cells that affect the performance of solar cells.

[0006] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0007] In a first aspect, embodiments of the present invention provide a solar cell, the solar cell comprising:

[0008] A silicon substrate, a first semiconductor layer, and a conductive layer; the first semiconductor layer is disposed on at least one surface of the silicon substrate; the conductive layer is disposed on the side of the first semiconductor layer opposite to the silicon substrate;

[0009] At least a portion of the surface region of the silicon substrate has a pyramid structure, the first semiconductor layer is conformally deposited on the surface of the silicon substrate, and the conductive layer is conformally deposited on the side of the first semiconductor layer away from the silicon substrate.

[0010] The thickness of the conductive layer located at the ridge of the pyramid structure is greater than the thickness of the conductive layer located on the slope of the pyramid structure.

[0011] In a second aspect, embodiments of the present invention provide a photovoltaic module, the photovoltaic module including a cover plate, a back plate, and a solar cell disposed between the cover plate and the back plate; the solar cell includes the solar cell described above.

[0012] In this embodiment, for a pyramid structure, the area of ​​the pyramid edges is much smaller than the area of ​​the inclined planes. Therefore, in the conductive layer of the first semiconductor layer, the proportion of the thicker conductive layer is smaller, while the proportion of the thinner conductive layer is larger. This reduces the proportion of the thicker conductive layer area on the battery. Thus, the larger proportion of the thinner conductive layer in this solution reduces parasitic and resonant absorption phenomena in the conductive layer, mitigating the parasitic and resonant absorption defects caused by the thicker conductive layer, thereby improving the light utilization rate of the solar cell and enhancing its performance. The larger proportion of the thinner conductive layer also allows for greater light penetration, improving the optical performance of the solar cell. Furthermore, the thicker conductive layer at the pyramid edges ensures the basic thickness of the conductive layer, improving its conductivity.

[0013] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0015] Figure 1 A schematic diagram of the cross-sectional structure of a solar cell according to an embodiment of the present invention is shown;

[0016] Figure 2 A schematic diagram of a pyramid structure according to an embodiment of the present invention is shown;

[0017] Figure 3 A top view of a pyramid structure according to an embodiment of the present invention is shown;

[0018] Figure 4 A schematic diagram of a partial surface structure of a conductive layer in an embodiment of the present invention is shown;

[0019] Figure 5 A partial surface magnified structural diagram of a conductive layer in an embodiment of the present invention is shown;

[0020] Figure 6 A cross-sectional schematic diagram of a portion of the surface of a conductive layer in an embodiment of the present invention is shown;

[0021] Figure 7 An enlarged schematic diagram of a cross-section of a portion of the surface of a conductive layer in an embodiment of the present invention is shown;

[0022] Figure 8 An enlarged schematic diagram of a partial surface cross-section of another conductive layer in an embodiment of the present invention is shown;

[0023] Figure 9 A schematic diagram of a partial surface structure of another conductive layer in an embodiment of the present invention is shown;

[0024] Figure 10 A schematic diagram of a partial surface structure of another conductive layer in an embodiment of the present invention is shown;

[0025] Figure 11 A schematic diagram of the surface structure of a solar cell according to an embodiment of the present invention is shown;

[0026] Figure 12 A schematic cross-sectional view of the isolation region of a solar cell according to an embodiment of the present invention is shown;

[0027] Figure 13 A schematic cross-sectional view of the isolation region of another solar cell in an embodiment of the present invention is shown;

[0028] Figure 14 A schematic cross-sectional view of the isolation region of another solar cell in an embodiment of the present invention is shown;

[0029] Figure 15 A schematic cross-sectional view of the isolation region of another solar cell according to an embodiment of the present invention is shown.

[0030] Explanation of reference numerals in the attached figures:

[0031] 10-First semiconductor layer; 20-Second semiconductor layer; 22-Passivation layer; 21-Doped polysilicon layer; 30-Silicon substrate; 40-Conductive layer; 50-Pyramid structure; 51-Pyramid edge; 52-Sloping surface; 501-First pyramid; 502-Second pyramid; 503-Third pyramid; 60-Electrode; 61-Collector electrode; 70-Isolation region; 71-First side; 72-Second side. Detailed Implementation

[0032] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0033] Reference Figure 1 The diagram shows a cross-sectional structural schematic of a solar cell provided in an embodiment of the present invention. The solar cell includes a silicon substrate 30, a first semiconductor layer 10, and a conductive layer 40. The first semiconductor layer 10 is disposed on at least one surface of the silicon substrate 30. The conductive layer 40 is disposed on the side of the first semiconductor layer 10 facing away from the silicon substrate 30. At least a portion of the surface region of the silicon substrate 30 has a pyramid structure 50. The first semiconductor layer 10 is conformally deposited on the surface of the silicon substrate 30, and the conductive layer 40 is conformally deposited on the side of the first semiconductor layer 10 away from the silicon substrate 30. Further reference... Figure 2 and Figure 3 , Figure 2 A schematic diagram of the surface structure of the plurality of pyramid structures 50 formed on the conductive layer 40 is shown. Figure 3 A top view of a pyramid structure 50 formed on the conductive layer 40 is shown. The thickness of the conductive layer 40 located at the pyramid edge 51 of the pyramid structure 50 is greater than the thickness of the conductive layer 40 located at the inclined surface 52 of the pyramid structure 50.

[0034] Among them, targeting Figure 3 The pyramid structure 50 has four edges 51: AO, BO, CO, and DO. The pyramid structure 50 also has four faces 52: AOD, BOA, COB, and DOC, formed by two adjacent edges 41 emanating from the apex O. It should be noted that the embodiments of this application do not limit the number of edges 51 and faces 52 included in a single pyramid structure 50. In some embodiments, a single pyramid structure 50 may have ≥3 edges 51 and ≥3 faces 52.

[0035] Optionally, the thickness of the conductive layer on one side of the slope of the pyramid structure 50 is greater than the thickness of the conductive layer on the other side. For example, with AC as the dividing line, the thickness of the conductive layers on the slope AOD and COD are both greater than the thickness of the conductive layers on AOB and BOC, respectively.

[0036] The technical advantage of this structure is that it optimizes the optical performance of solar cells. The pyramid structure itself enhances light trapping and reduces reflection. The different thicknesses of the conductive layers on the left and right sides of the pyramid structure further amplify this effect, achieving multiple anti-reflection measures. The ideal conductive layer thickness is optimized for a specific wavelength and incident angle. The uneven thickness of the conductive layers on the left and right sides of the pyramid structure is equivalent to integrating multiple optimal thickness points on the same microstructure. This means that for different wavelengths of light, the optimal anti-reflection wavelengths for the thick and thin regions differ, and their combination can cover a wider spectral range, thereby increasing the cell's short-circuit current. For different angles of light, sunlight primarily shines from a dominant direction throughout the day; for example, the thicker "left" side may receive more light in the morning, while the thinner "right" side receives more in the afternoon. This design ensures that, over a wider range of sunlight exposure, the thickness of the conductive layer on one side is always close to the optimal thickness for that particular incident angle, thus increasing the cell's total daily power generation, not just its midday efficiency.

[0037] In solar cells, due to the low mobility and high sheet resistance of the first semiconductor layer 10, a conductive layer 40 needs to be added between the nano-silicon thin film and the metal electrode 60. The conductive layer 40 collects charge carriers, and the electrode 60 can be disposed on the conductive layer 40. The electrode and the conductive layer 40 below each electrode together form a system for collecting and transporting charge carriers. At the contact point between the conductive layer 40 and the electrode, plasmon resonance is generated at the interface because the electrode 60 contains a large number of electrons. Under the combined effect of optical interference, this interface will generate plasmon resonance absorption, which enhances the absorption of photons in the long-wavelength band (near-infrared and infrared regions). The higher the charge carrier concentration on the conductive layer 40, the stronger the resonance absorption.

[0038] In this embodiment, at least a portion of the surface region of the silicon substrate 30 has a pyramid structure 50. The first semiconductor layer 10 is deposited conformally on the surface of the silicon substrate 30, such that at least a portion of the surface region of the first semiconductor layer 10 has a pyramid structure 50. The conductive layer 40 is deposited conformally on the side of the first semiconductor layer 10 away from the silicon substrate 30, such that at least a portion of the surface region of the conductive layer 40 has a pyramid structure 50. The function of the pyramid structure 50 is to increase the light trapping effect on the surface of the battery cell, reduce the reflection of light on the battery surface, increase the utilization rate of light by the battery, and improve the battery performance.

[0039] Among them, the pyramid structure 50 can be obtained in an alkaline bath by texturing. The required solution is a potassium hydroxide solution with a concentration of 3±0.5% and a texturing additive, the solution temperature is 82±2 degrees Celsius, the process time is 600±30 seconds, the etching amount is 0.6±0.1g, and the reflectivity is 10±1%.

[0040] In practical applications, under the same process conditions, a thinner conductive layer has a lower carrier concentration and higher sheet resistance, resulting in weaker resonant absorption of light and reduced parasitic absorption of light. A thicker conductive layer has an even higher carrier concentration and lower sheet resistance, resulting in stronger resonant absorption of light and increased parasitic absorption of light. At the same time, a thicker conductive layer has lower transmission resistance, which is beneficial for the lateral transport of carriers, and lower contact resistance, which is beneficial for electrical transport with the collector electrode, thus facilitating the collection of carriers by the collector electrode of the solar cell.

[0041] Parasitic absorption refers to the phenomenon where a transparent conductive layer, originally designed to conduct current rather than absorb photons, inevitably absorbs a portion of the incident light and converts this light energy into unusable heat energy instead of electrical energy. This process directly reduces the battery's short-circuit current and ultimately its photoelectric conversion efficiency. The thicker the conductive layer, the more it affects the layer's penetration of certain wavelengths of light, leading to an enhanced parasitic absorption phenomenon.

[0042] Resonant absorption refers to the phenomenon where, when light shines on a conductive layer, the electromagnetic field of the light wave drives the free electrons in the material to oscillate synchronously. Resonance occurs when the frequency of the incident light matches the natural frequency of the collective oscillation of the free electrons. When the resonance condition is met, the conductive layer exhibits abnormally strong absorption of light of a specific wavelength (resonant wavelength), thus blocking that wavelength of light from entering the absorption layer and causing significant current loss. The resonant absorption phenomenon is weaker when the conductive layer is thinner and stronger when the conductive layer is thicker.

[0043] In this embodiment of the invention, the thickness of the conductive layer 40 located at the ridge 51 of the pyramid structure 50 can be set to be greater than the thickness of the conductive layer 40 located at the slope 52 of the pyramid structure 50. Regarding the exposed surface of the pyramid structure 50, the area occupied by the ridge 51 is much smaller than the area occupied by the slope 52. Therefore, for a pyramid structure 50, since the area of ​​the ridge 51 on its surface is much smaller than the area of ​​the slope 52, the area of ​​the conductive layer 40 on the first semiconductor layer 10 at the ridge 51 is much smaller than the area of ​​the conductive layer 40 at the slope 52. Furthermore, since the thickness of the conductive layer 40 located at the ridge 51 is greater than the thickness of the conductive layer 40 located at the inclined surface 52 of the pyramid structure 50, the proportion of the conductive layer 40 with a larger thickness on the first semiconductor layer 10 is relatively small, while the proportion of the conductive layer 40 with a smaller thickness is relatively large. It can be understood that although the conductive layer 40 at the ridge is thicker and has the effects of resonant absorption and parasitic absorption, the relative area of ​​the ridge 51 is small, resulting in less resonant absorption and parasitic absorption of incident light. At the inclined surface 52, the resonant absorption and parasitic absorption of the conductive layer are optimized by thinning the conductive layer, and the area of ​​the inclined surface is relatively large. This setting is more conducive to the light utilization efficiency of the battery surface. Through the contact between the electrode and the conductive layer, better contact resistance and lateral transmission current are provided at the thicker ridge, making use of the selective advantages of the battery conductive layer, thereby improving the overall light utilization efficiency and current transmission efficiency of the battery.

[0044] Therefore, in the conductive region where the first semiconductor layer 10 is located, the portion of the thicker conductive layer 40 is relatively small, while the portion of the thinner conductive layer 40 is relatively large. This reduces the proportion of the thicker conductive layer 40 region on the cell. Thus, the larger proportion of the thinner conductive layer 40 in this design reduces parasitic and resonant absorption phenomena in the conductive layer 40, lowering the parasitic and resonant absorption defects caused by the thicker conductive layer 40, thereby improving the light utilization rate of the solar cell and enhancing its performance. The larger proportion of the thinner conductive layer 40 also allows for greater light penetration, improving the optical performance of the solar cell. Furthermore, the thicker conductive layer at the ridge ensures the basic thickness of the conductive layer, improving its conductivity.

[0045] Next, we will explain the experimental phenomenon that the thickness of the conductive layer 40 located at the pyramid edge 51 of the pyramid structure 50 is greater than the thickness of the conductive layer 40 located at the inclined surface 52 of the pyramid structure 50:

[0046] Reference Figure 4It shows a top view of the morphology of a conductive layer surface with a pyramid structure. It can be seen that there are a large number of pyramid structures on the conductive layer surface on the first semiconductor layer, which are connected and arranged to each other. The pyramid edges are parallel or perpendicular to each other.

[0047] Further from Figure 4 Select a region and zoom in to display it, forming a shape like... Figure 5 The morphology shown was cut along the cutting line S using a focused ion beam (FIB) to obtain... Figure 6 , Figure 7 , Figure 8 Schematic diagram, Figure 6 This is a schematic diagram of the cross-section at the cutting line. Figure 7 This is an enlarged schematic diagram of the cross-section at the cutting line. Figure 8 This is another enlarged view of the cross-section at the cutting line. Along the cutting line S, there are, in sequence, a first pyramid 501, a second pyramid 502, and a third pyramid 503. The first pyramid 501 and the third pyramid 503 are cut at the inclined plane 52, while the second pyramid (the middle pyramid) is cut at the ridge 51. Figure 7 The difference between the conductive layer thickness of 54 nm on the right slope 52 of the first pyramid 501 and the conductive layer thickness of 65 nm on the left ridge 51 of the second pyramid 502 is shown. Figure 8 The difference between the 60 nm thickness of the conductive layer on the right side 51 of the second pyramid 502 and the 55 nm thickness of the conductive layer on the left side 52 of the third pyramid 501 is shown.

[0048] Therefore, it can be deduced that the thickness of the conductive layer on the edges of adjacent pyramids is greater than the thickness of the conductive layer on the slope of the pyramid. This leads to the conclusion that the thickness of the conductive layer on the edges of the same pyramid is greater than the thickness of the conductive layer on the slope of the pyramid. In other words, for all pyramid structures distributed on the surface of the conductive layer on the first semiconductor layer, it could mean that the thickness of the conductive layer at all edges is greater than the thickness of the conductive layer at all slopes, or that the thickness of the conductive layer at the edges of a single pyramid structure is greater than the thickness of the conductive layer at the slopes of that pyramid structure.

[0049] Optional, refer to Figure 1 A collector electrode 61 is also provided on the first semiconductor layer 10; the collector electrode 61 is in contact with the conductive layer 40 at the pyramid ridge 51 of the pyramid structure 50 and forms an electrical connection.

[0050] In this embodiment of the invention, the current collector electrode 61 is typically a fine grid electrode used to extract charge carriers from the solar cell, and the current collector electrode is typically a main grid electrode used to combine the charge carriers transported by multiple current collector electrodes together. The first semiconductor layer 10 is provided with a current collector electrode 61 (i.e., a P-region fine grid) of the same polarity as the first semiconductor layer 10. The current collector electrode 61 contacts and forms an electrical connection with the conductive layer 40 at the pyramid ridge 51 of the pyramid structure 50. Because the conductive layer 40 at the pyramid ridge 51 of the pyramid structure 50 is thicker, it has better conductivity. Furthermore, the thicker conductive layer 40 at the pyramid ridge 51 can form protrusions, improving the contact performance between the thicker conductive layer 40 at the pyramid ridge 51 and the current collector electrode 61, thereby enhancing the electrical transmission performance of the current collector electrode 61.

[0051] Optional, refer to Figure 9 At least two pyramidal edges 51 extending in the same direction in the pyramidal structure 50 are on the same straight line; in the multiple pyramidal structures 50, the deviation distance between the pyramidal edges 51 extending in the same direction in the first pyramidal structure and the pyramidal edges extending in the same direction in the second pyramidal structure is 0-5nm; the first pyramidal structure and the second pyramidal structure are arranged adjacent to each other; the overlap rate between the multiple pyramidal edges extending in the first direction and the collector electrode 61 can reach 70%; the first direction is parallel to the extension direction of the collector electrode 61.

[0052] in, Figure 9 Lines L1 to L8 are shown. These lines are the same line on which at least two pyramid edges 51 extending along the first direction in the pyramid structure 40 are located. It can be that at least two pyramid edges 51 extending along the first direction in one pyramid structure 40 are located on the same line, or at least two pyramid edges 51 extending along the first direction in each of multiple pyramid structures 40 are located on the same line.

[0053] The first and second pyramid structures are two adjacent pyramid structures. The deviation distance between the pyramid edges 51 extending in the same direction in the first pyramid structure and the pyramid edges extending in the same direction in the second pyramid structure is 0-5 nm. This ensures that the pyramid edges 51 extending in the same direction in the two adjacent pyramid structures are as close to a straight line as possible. In practical applications, the deviation distance can be selected according to actual needs, for example, any value among 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, and 5 nm.

[0054] Furthermore, the first direction is the extension direction of the collector electrode 61. The overlap rate between the multiple ridges 51 extending along the first direction and the collector electrode 61 reaches 70%. This ensures a high overlap rate between the collector electrode 61 and the ridges 51 extending along the first direction, allowing the collector electrode 61 to make as much contact as possible with the ridges 51 extending along the first direction. Since the conductive layer 40 at the ridges 51 extending along the first direction has better conductivity, and the thicker conductive layer 40 at the ridges 51 extending along the first direction can form protrusions, the contact performance between the thicker conductive layer 40 at the ridges 51 and the collector electrode 61 is improved, thereby enhancing the electrical transmission performance of the collector electrode 61. Here, the overlap rate refers to the number of complete ridges 51 extending along the first direction within the area covered by the collector electrode, exceeding the number of ridges 51 extending along the first direction that are interspersed within the area covered by the collector electrode.

[0055] Optional, refer to Figure 10 At least two pyramidal ridges 51 extending in the same direction in the pyramidal structure 50 are on the same straight line; in the multiple pyramidal structures 50, the deviation distance between the pyramidal ridges 51 extending in the same direction in the first pyramidal structure and the pyramidal ridges 51 extending in the same direction in the second pyramidal structure is 0-5nm; the first pyramidal structure and the second pyramidal structure are arranged adjacent to each other; the multiple pyramidal ridges 51 extending in the second direction are arranged perpendicularly to the collector electrode 61; the second direction is perpendicular to the extension direction of the collector electrode 61.

[0056] in, Figure 10 Lines L9 to L13 are shown. These lines are the same line on which at least two pyramid edges 51 extending along the second direction in the pyramid structure 40 are located. This can be at least two pyramid edges 51 extending along the second direction in one pyramid structure 40 sharing the same line, or at least two pyramid edges 51 extending along the second direction in each of multiple pyramid structures 40 sharing the same line.

[0057] The second direction is perpendicular to the extension direction of the current collector 61. Multiple ridges 51 extending along this second direction are perpendicularly intersecting the current collector 61. This perpendicular intersection between the ridges 51 and the current collector 61 allows the thicker conductive layer on the ridges 51 along the second direction to facilitate lateral current transmission. The ridges 51 in the second direction laterally transmit nearby current to the current collector 61, which is beneficial for current collection in the solar cell and thus improves cell performance. Furthermore, this design satisfies part of the current transmission requirements of the solar cell by lateral current transmission, allowing for a larger spacing between the current collectors, reducing the number of current collectors and saving on electrode paste costs.

[0058] Optionally, the surface of the solar cell is provided with electrodes, including current collector electrodes and current collector electrodes; the electrodes are connected to conductive layers at a plurality of ridges extending along a first direction; the electrodes are also connected to conductive layers at a plurality of ridges extending along a second direction; the first direction is parallel to the extension direction of the current collector electrodes, and the second direction is perpendicular to the extension direction of the current collector electrodes.

[0059] In this embodiment of the invention, electrode 60 includes a current collecting electrode and a current collecting electrode. Electrode 60 can be connected to both the pyramidal ridge 51 extending in the first direction and the pyramidal ridge 51 extending in the second direction. This increases the contact probability between the thicker conductive layer on the pyramidal ridge and the electrode, improving the battery's current collection capability. Furthermore, the thinner conductive layer at the sloping surface of the pyramidal structure below the electrode reduces parasitic absorption and resonant absorption phenomena in the battery, thereby improving the solar cell's light utilization efficiency and enhancing its performance.

[0060] Optional, refer to Figure 9 and Figure 10 The surface of the solar cell is provided with electrodes 60, which include current collector electrodes 61 and current collector electrodes (not shown in the figure); multiple continuous ridges 51 extending along the same extension direction constitute a continuous ridge region (i.e., the region where each of the straight lines L1-L13 is located); the deviation distance between adjacent ridges 51 in the continuous ridge region is 0-5nm; multiple continuous ridge regions are arranged at intervals; each electrode 60 covers multiple continuous ridge regions at the same time.

[0061] In this embodiment of the invention, multiple consecutive tower edges 51 extending along the same extending direction constitute a continuous tower edge region, such as... Figure 9 In the middle, the tower edges 51 covered by straight lines L1-L8 are multiple consecutive tower edges 51 extending along the first direction. Figure 10 In the diagram, the ridges 51 covered by straight lines L9-L13 are multiple continuous ridges 51 extending along the second direction. The deviation distance between adjacent ridges 51 in the continuous ridge region is 0-5nm, making the multiple continuous ridges 51 form a structure similar to the "side-by-side" structure of the ridges 51. Each electrode 60 covers multiple continuous ridge regions simultaneously, which increases the contact probability between the thicker conductive layer on the ridge and the electrode, improving the cell's current collection capability. Furthermore, the thinner conductive layer at the sloping surface of the pyramid structure below the electrode reduces parasitic absorption and resonant absorption phenomena in the cell. In addition, the vertical intersection between the ridge and the electrode allows the thicker conductive layer on the ridge to achieve lateral current transmission, further facilitating the current collection of the solar cell, thereby improving the light utilization rate of the solar cell and enhancing its performance.

[0062] Optionally, the thickness difference between the conductive layer located at the tower edge and the conductive layer located on the slope is 2~10 nm. For example, the thickness difference is 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. By controlling the thickness difference of the conductive layer within the above range, the thickness requirements at the tower edge and the slope can be met, while also reducing the excessive concentration difference of charge carriers on the same surface and decreasing the probability of charge carrier recombination.

[0063] Optionally, the surface of the solar cell is provided with electrodes, including current collector electrodes and current collector electrodes; the width of the current collector electrodes is 30~70um; the width of the current collector electrodes is 100~200um.

[0064] In practical applications, the width of the collector electrode can be selected according to actual needs. For example, the width of the collector electrode can be any value among 30um, 35um, 40um, 45um, 50um, 55um, 60um, 65um, and 70um.

[0065] In practical applications, the width of the bus electrode can be selected according to actual needs. For example, the width of the bus electrode can be any value among 100um, 110um, 120um, 130um, 140um, 150um, 160um, 170um, 180um, 190um, and 200um.

[0066] In this embodiment of the invention, the solar cell can be any one of heterojunction back contact (HBC), high and low temperature composite passivated back contact (HIBC), or heterojunction technology (HJT).

[0067] Optional, refer to Figure 1 The solar cell further includes: a second semiconductor layer 20 and a current collector electrode 61; the second semiconductor layer 20 and the first semiconductor layer 10 are disposed on the same surface of the silicon substrate 30; the first semiconductor layer 10 and the second semiconductor layer 20 are alternately disposed; the first semiconductor layer 10 and the second semiconductor layer 20 have different electrical properties; a conductive layer 40 is also disposed on the side of the second semiconductor layer 20 facing away from the silicon substrate 30; the current collector electrode 61 is disposed on the conductive layer 40 of the second semiconductor layer 20 and the first semiconductor layer 10 respectively; the width of the first semiconductor layer 10 is 300~600um; the width of the current collector electrode 61 is 30~70um; the width of the area on the surface of the first semiconductor layer 10 where the current collector electrode 61 is not disposed is 120um~550um.

[0068] Reference Figure 1 This illustrates a case where the solar cell is a HIBC (High-Intensity Fiber) cell. Specifically, in this solar cell, one of the first and second surfaces is the front side of the silicon substrate 30, and the other is the back side of the silicon substrate 30. A first semiconductor layer 10 and a second semiconductor layer 20 can be disposed on either the first or second surface. One of the first semiconductor layer 10 and the second semiconductor layer 20 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, an example is given where the first semiconductor layer 10 is a P-type doped polycrystalline silicon layer and the second semiconductor layer 20 is an N-type doped amorphous silicon layer.

[0069] In this embodiment of the invention, since the first semiconductor layer 10 and the second semiconductor layer 20 have different electrical properties, alternating N-regions and P-regions can be formed on the surface of the solar cell. The N-region is the electron transport region of the solar cell, and the P-region is the hole transport region. The current collector electrode 61 is typically a fine grid electrode used to extract charge carriers from the solar cell, and the bus electrode is typically a main grid electrode used to combine the charge carriers transported by multiple current collector electrodes together.

[0070] It should be noted that the first semiconductor layer 10 and the second semiconductor layer 20 can be connected to each other (they can partially overlap in the thickness direction and be adjacent to each other in the extension direction). The first semiconductor layer 10 and the second semiconductor layer 20 can also have an isolation region (they can not be adjacent to each other in the extension direction and can be separated by an isolation structure). This embodiment of the present invention does not limit this.

[0071] The width of the first semiconductor layer 10 is 300~600um; the width of the collector electrode is 30~70um; and the width of the area on the surface of the first semiconductor layer 10 where no collector electrode is provided is 120um~550um. With such parameter range, a pyramidal ridge line perpendicular to the collector electrode can be formed on both sides of the collector electrode to improve the lateral current transmission capability. In addition, the thickness of the slope of the pyramid structure is reduced, which reduces parasitic absorption and resonant absorption, improves light utilization efficiency, and comprehensively improves battery efficiency.

[0072] In practical applications, the width of the first semiconductor layer 10 can be selected according to actual needs. For example, the width of the first semiconductor layer 10 can be any value among 300um, 350um, 400um, 450um, 500um, 550um, and 600um.

[0073] In practical applications, the width of the area on the surface of the first semiconductor layer 10 where no collector electrode is provided can be selected according to actual needs. For example, the width of the area on the surface of the first semiconductor layer 10 where no collector electrode is provided can be any value among 120um, 150um, 200um, 250um, 300um, 350um, 400um, 450um, 500um, and 550um.

[0074] Optionally, the solar cell further includes: a second semiconductor layer; a first semiconductor layer disposed on a first surface of the silicon substrate; a second semiconductor layer disposed on a second surface of the silicon substrate; the first semiconductor layer and the second semiconductor layer having different electrical properties; and a conductive layer further disposed on the side of the second semiconductor layer facing away from the silicon substrate. In the fabrication process, the silicon substrate is supported by a carrier plate, and the conductive layer is deposited through a magnetron sputtering chamber.

[0075] In another embodiment of the present invention, specifically, in the solar cell, one of the first surface and the second surface is the front side of the silicon substrate, and the other of the first surface and the second surface is the back side of the silicon substrate. A first semiconductor layer can be disposed on the first surface of the silicon substrate; a second semiconductor layer can be disposed on the second surface of the silicon substrate. One of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other of the first semiconductor layer and the second semiconductor layer is a P-type semiconductor layer. In some embodiments, an example is given where the first semiconductor layer is a P-type doped polycrystalline silicon layer and the second semiconductor layer is an N-type doped amorphous silicon layer.

[0076] Optional, refer to Figure 1 The solar cell further includes: a second semiconductor layer 20 and a current collector electrode 61; the second semiconductor layer 20 and the first semiconductor layer 10 are disposed on the same surface of the silicon substrate 30; the first semiconductor layer 10 and the second semiconductor layer 20 are alternately disposed; the first semiconductor layer 10 and the second semiconductor layer 20 have different electrical properties; a conductive layer 40 is also disposed on the side of the second semiconductor layer 20 facing away from the silicon substrate 30; further refer to Figures 11-15 An isolation region 70 is provided between adjacent first semiconductor layer 10 and second semiconductor layer 20; the thickness of the conductive layer 40 at the ridge near the first side 71 of the isolation region 70 is greater than the thickness of the conductive layer 40 at the ridge near the second side 72 of the isolation region 70; the first side 71 and the second side 72 are disposed opposite to each other; the thickness of the conductive layer 40 at the slope near the first side 71 of the isolation region 70 is greater than the thickness of the conductive layer 40 at the slope near the second side 72 of the isolation region 70.

[0077] In this embodiment of the invention, for a back-contact battery, the second semiconductor layer 20 and the first semiconductor layer 10 are disposed on the same surface of the silicon substrate. The junction of the second semiconductor layer 20 and the first semiconductor layer 10 is an isolation region 70. The width of the isolation region 70 is generally above 20 μm. The isolation region 70 is mainly used for isolation between the second semiconductor layer 20 and the first semiconductor layer 10.

[0078] Specifically, refer to Figures 11-15 The thickness of the conductive layer 40 at the ridge near the first side 71 of the isolation zone 70 is greater than the thickness of the conductive layer 40 at the ridge near the second side 72 of the isolation zone 70; the thickness of the conductive layer 40 at the slope (first slope) near the first side 71 of the isolation zone 70 is greater than the thickness of the conductive layer 40 at the slope (second slope) near the second side 72 of the isolation zone 70. This results in a thinner conductive layer 40 on one side of the isolation zone 70 and a thicker conductive layer 40 on the other side, providing greater process space for the thickness of the conductive layer 40 in the electrode area. The conductive layers 40 on both sides can be set with different thicknesses to match the processes of the P-region and the N-region. The thicker conductive layer 40 can provide better leakage current, while the thinner conductive layer 40 can provide better light absorption and reduce parasitic absorption.

[0079] Optionally, the back side of the back contact battery includes multiple P-regions and N-regions, with an isolation region 70 between adjacent P-regions and N-regions. The conductive layer 40 on the inclined surface of the isolation region 70 on both sides of the N-region has a different thickness. The conductive layer 40 on the first inclined surface of the isolation region 70 is close to the thickness of the electrode conductive layer 40, while the conductive layer 40 on the second inclined surface of the isolation region 70 is thinner. The thickness of the conductive layer 40 on the second inclined surface is 0.86 to 0.87 times that on the first inclined surface. This technology can reduce sputtering damage on the second inclined surface of the isolation region 70 of the back contact battery and improve Pff by about 0.1%. The conductive layer 40 on the first inclined surface and the conductive layer 40 on the second inclined surface of the isolation region 70 are not limited, as long as they are on the inclined surface of the isolation region 70 on both sides of the same N-region.

[0080] In the process, according to Bernoulli's principle, in the direction of advancement of the vapor deposition chamber, the conductive layer 40 on the first inclined surface facing the front has a high sputtering particle density and high bombardment energy, resulting in significant sputtering damage. Conversely, the conductive layer 40 on the second inclined surface on the back side has a low sputtering particle density and low bombardment energy, thus experiencing less sputtering damage. For a single cell, with the same total deposition time, the conductive layer 40 deposited on the second inclined surface is thinner and suffers less sputtering damage compared to the conductive layer 40 deposited on the first inclined surface. Therefore, the conductive layer 40 deposited on the second inclined surface is the thinnest, maximizing the reduction of sputtering damage.

[0081] Wherein, the carrier direction P is the direction in which the carrier carrying the solar cell moves. The carrier direction P is perpendicular to the long side of the solar cell. The first side 71 is the side that the carrier direction passes through later; the second side 72 is the side that the carrier direction passes through first.

[0082] Optional, refer to Figures 11-15 The thickness of the conductive layer 40 at the interface 80 between the inclined surfaces of the first side 71 and the second side 72 of the isolation region 70 and the surface of the isolation region 70 is 10nm~50nm.

[0083] In this embodiment of the invention, the thickness of the conductive layer 40 at the interface 80 between the inclined surfaces near the first side 71 and the second side 72 of the isolation region 70 and the surface of the isolation region 70 is 10nm~50nm. This allows the isolation trench to be set in the overlapping area of ​​the first and second semiconductor layers without extending across regions, thus forming a conformally deposited conductive layer at the cross-section of the doped semiconductor layer. This results in a suitable conductive layer thickness at this location, enabling the solar cell to both prevent hot spot effects and achieve a certain leakage current. Furthermore, due to the limited thickness of the conductive layer at this location, the leakage current is not too large, preventing efficiency reduction. Additionally, although the interface 80 is narrow, a conductive layer is still deposited there. This conformally deposited conductive layer improves the passivation effect of the cell surface.

[0084] Optional, refer to Figure 1 The first semiconductor layer 10 includes an intrinsic amorphous silicon layer and a doped amorphous silicon layer stacked sequentially; the intrinsic amorphous silicon layer is in contact with the silicon substrate 30; the second semiconductor layer 20 includes a passivation layer 22 disposed on the silicon substrate 30, a doped polycrystalline silicon layer 21 disposed on the passivation layer 22, and a portion of the first semiconductor layer 10 disposed on the doped polycrystalline silicon layer 21.

[0085] In this embodiment, the first semiconductor layer 10 and the second semiconductor layer 20 have different electrical properties. In one embodiment, the second semiconductor layer 20 includes a doped polycrystalline silicon layer, and the first semiconductor layer 10 includes a doped crystalline silicon layer. The doped crystalline silicon layer can be any one of amorphous silicon, nanocrystalline silicon, or microcrystalline silicon. The second semiconductor layer 20 forms the N-region, providing electron transport for the solar cell; the first semiconductor layer 10 forms the P-region, providing hole transport for the solar cell.

[0086] The passivation layer 22 serves a passivation function, and its thickness is 0.5nm-5nm, preferably 1.2nm-2nm. The passivation layer 22 is made of any one of silicon oxide, aluminum oxide, silicon nitride, silicon carbide, and magnesium oxide.

[0087] This application also provides a photovoltaic module, which includes a cover plate, a back sheet, and a battery string disposed between the cover plate and the back sheet. The battery string includes a plurality of solar cells connected in series by interconnecting elements. The solar cells include the aforementioned solar cells.

[0088] This application does not specifically limit whether the photovoltaic module includes other structures. For example, the photovoltaic module may also include: a first encapsulating film disposed between the cover plate and the solar cell, and a second encapsulating film disposed between the back sheet and the solar cell.

[0089] In summary, in this embodiment of the application, for a pyramid structure, the area of ​​the pyramid edges is much smaller than the area of ​​the inclined planes. Therefore, in the conductive layer of the first semiconductor layer, the proportion of the thicker conductive layer is smaller, while the proportion of the thinner conductive layer is larger. This reduces the proportion of the thicker conductive layer area on the battery. Thus, the larger proportion of the thinner conductive layer in this solution reduces parasitic absorption and resonant absorption phenomena in the conductive layer, lowering the parasitic absorption defects and resonant absorption defects caused by the thicker conductive layer, thereby improving the light utilization rate of the solar cell and enhancing its performance. The larger proportion of the thinner conductive layer also allows for greater light penetration, improving the optical performance of the solar cell. Furthermore, the thicker conductive layer at the pyramid edges ensures the basic thickness of the conductive layer, improving its conductivity.

[0090] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0091] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. For embodiments of devices, electronic devices, computer-readable storage media, and computer program products containing instructions, the descriptions are relatively simple because they are basically similar to the method embodiments; relevant parts can be referred to the descriptions of the method embodiments.

[0092] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A solar cell, characterized by, The solar cell includes a silicon substrate, a first semiconductor layer, and a conductive layer; the first semiconductor layer is disposed on at least one surface of the silicon substrate; the conductive layer is disposed on the side of the first semiconductor layer opposite to the silicon substrate. At least a portion of the surface region of the silicon substrate has a pyramid structure, the first semiconductor layer is conformally deposited on the surface of the silicon substrate, and the conductive layer is conformally deposited on the side of the first semiconductor layer away from the silicon substrate. The thickness of the conductive layer located at the ridge of the pyramid structure is greater than the thickness of the conductive layer located on the slope of the pyramid structure.

2. The solar cell according to claim 1, characterized in that, A collector electrode is also disposed on the first semiconductor layer; The current collecting electrode contacts the conductive layer at the ridge of the pyramid structure and forms an electrical connection.

3. The solar cell according to claim 2, characterized in that, At least two of the pyramidal ridges extending in the same direction are aligned in a straight line in the pyramidal structure. In the plurality of pyramid structures, the deviation distance between the pyramid ridges extending in the same direction in the first pyramid structure and the pyramid ridges extending in the same direction in the second pyramid structure is 0-5nm; the first pyramid structure and the second pyramid structure are arranged adjacent to each other; The overlap rate between the plurality of tower ridges extending along the first direction and the current collector electrode reaches 70%; the first direction is parallel to the extension direction of the current collector electrode.

4. The solar cell according to claim 2, characterized in that, At least two of the pyramidal ridges extending in the same direction are aligned in a straight line in the pyramidal structure. In the plurality of pyramid structures, the deviation distance between the pyramid ridges extending in the same direction in the first pyramid structure and the pyramid ridges extending in the same direction in the second pyramid structure is 0-5nm; the first pyramid structure and the second pyramid structure are arranged adjacent to each other; The plurality of tower ridges extending along a second direction are arranged perpendicularly to the current collector electrode; the second direction is perpendicular to the extension direction of the current collector electrode.

5. The solar cell according to claim 1, characterized in that, The surface of the solar cell is provided with electrodes, the electrodes including current collecting electrodes and current merging electrodes; The electrode is connected to a conductive layer at one of the plurality of tower ridges extending along a first direction; The electrode is also connected to a conductive layer at one of the plurality of tower ridges extending along the second direction; The first direction is parallel to the extension direction of the current collector electrode, and the second direction is perpendicular to the extension direction of the current collector electrode.

6. The solar cell according to claim 1, characterized in that, The surface of the solar cell is provided with electrodes, the electrodes including current collecting electrodes and current merging electrodes; Multiple consecutive tower edges extending along the same extension direction constitute a continuous tower edge region; the deviation distance between adjacent tower edges in the continuous tower edge region is 0-5nm; multiple continuous tower edge regions are arranged at intervals; Each of the electrodes simultaneously covers multiple continuous regions of the tower ridges.

7. The solar cell according to claim 1, characterized in that, The difference between the thickness of the conductive layer located at the tower edge and the thickness of the conductive layer located on the slope is 2~10nm.

8. The solar cell according to claim 1, characterized in that, The surface of the solar cell is provided with electrodes, the electrodes including current collecting electrodes and current merging electrodes; The width of the current collector electrode is 30~70um; The width of the bus electrode is 100~200um.

9. The solar cell according to claim 1, characterized in that, The solar cell further includes: a second semiconductor layer and a current collector electrode; the second semiconductor layer and the first semiconductor layer are disposed on the same surface of the silicon substrate; the first semiconductor layer and the second semiconductor layer are alternately disposed; the first semiconductor layer and the second semiconductor layer have different electrical properties; the conductive layer is also disposed on the side of the second semiconductor layer facing away from the silicon substrate; The current collector electrodes are respectively disposed on the conductive layers of the second semiconductor layer and the first semiconductor layer; The width of the first semiconductor layer is 300~600um; the width of the collector electrode is 30~70um; In the surface of the first semiconductor layer, the width of the region where the current collector electrode is not disposed is 120um~550um.

10. The solar cell according to claim 1, characterized in that, The solar cell further includes: a second semiconductor layer; the first semiconductor layer is disposed on a first surface of the silicon substrate; the second semiconductor layer is disposed on a second surface of the silicon substrate; the first semiconductor layer and the second semiconductor layer have different electrical properties; the conductive layer is also disposed on the side of the second semiconductor layer facing away from the silicon substrate.

11. The solar cell according to claim 1, characterized in that, The solar cell further includes: a second semiconductor layer and a current collector electrode; the second semiconductor layer and the first semiconductor layer are disposed on the same surface of the silicon substrate; the first semiconductor layer and the second semiconductor layer are alternately disposed; the first semiconductor layer and the second semiconductor layer have different electrical properties; the conductive layer is also disposed on the side of the second semiconductor layer facing away from the silicon substrate; An isolation region exists between adjacent first semiconductor layers and second semiconductor layers; The thickness of the conductive layer at the ridge near the first side of the isolation zone is greater than the thickness of the conductive layer at the ridge near the second side of the isolation zone; the first side and the second side are arranged opposite to each other; The thickness of the conductive layer at the slope near the first side of the isolation zone is greater than the thickness of the conductive layer at the slope near the second side of the isolation zone.

12. The solar cell according to claim 11, characterized in that, The thickness of the conductive layer at the interface between the inclined surfaces close to the first and second sides of the isolation region and the surface of the isolation region is 10nm~50nm.

13. The solar cell according to any one of claims 9-11, characterized in that, The first semiconductor layer includes an intrinsic amorphous silicon layer and a doped amorphous silicon layer stacked sequentially; the intrinsic amorphous silicon layer is in contact with the silicon substrate; The second semiconductor layer includes a passivation layer disposed on the silicon substrate, a doped polysilicon layer disposed on the passivation layer, and a portion of the first semiconductor layer disposed on the doped polysilicon layer.

14. A photovoltaic module, characterized in that, The photovoltaic module includes a cover plate, a back sheet, and a battery string disposed between the cover plate and the back sheet, the battery string including a plurality of solar cells connected in series by interconnecting elements; the solar cells include the solar cells as described in any one of claims 1 to 13.

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