Display device and electronic equipment

Abstract

The application discloses a display device and an electronic device, and relates to the technical field of display. The display device comprises adjacent display areas and non-display areas, and a plurality of sub-pixels are arranged at intervals in the display areas. The display device further comprises a solar cell, the solar cell is located at a part of the display area and does not overlap the plurality of sub-pixels. The solar cell comprises a first electrode, a second electrode, a P-type semiconductor layer and a first N-type semiconductor layer. The first electrode and the second electrode are located at the same level. The P-type semiconductor layer covers the first electrode, and the first N-type semiconductor layer covers the P-type semiconductor layer and the second electrode. In this way, the P-type semiconductor and the first N-type semiconductor can be combined to form a PN junction. When the PN junction is irradiated, photo-generated carriers can move to the first electrode and the second electrode under the driving of the built-in electric field of the PN junction, so that the collection of the photo-generated carriers is completed, and solar power generation is realized.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display device and electronic device. Background Technology

[0002] With the development of science and technology, electronic devices such as mobile phones, tablets, and laptops are being used more and more frequently, and the battery life problem of these devices is becoming increasingly serious. Related technologies typically improve the battery life of electronic devices by increasing the capacity of their energy storage units. However, due to the limited internal space of these devices, increasing the capacity of energy storage units has reached a bottleneck.

[0003] Solar cells are devices that convert light energy into electrical energy through the photoelectric effect. If solar cells can be applied to electronic devices to provide power, the battery life of these devices can be further improved. Therefore, there is an urgent need for an electronic device that integrates solar cells. Summary of the Invention

[0004] This application provides a display device and an electronic device. The display device is applied to an electronic device and integrates a solar cell, which can improve the battery life of the electronic device. The technical solution is as follows:

[0005] In a first aspect, a display device is provided. The display device includes adjacent display areas and non-display areas, the non-display areas being the edges of the display device. The display areas are provided with a plurality of sub-pixels. When the display device is in operation, the plurality of sub-pixels emit light to display an image. Generally, the plurality of sub-pixels are spaced apart within the display areas along the extending direction of the display device.

[0006] Here, the display device also includes a solar cell. The solar cell includes at least a first cell portion, which refers to the portion of the solar cell located in the display area. Furthermore, along the thickness direction of the display device, the first cell portion does not overlap with any of the sub-pixels. That is, along the thickness direction of the display device, the projections of the first cell portion and the multiple sub-pixels onto the same plane do not overlap. The thickness direction of the display device is perpendicular to the extension direction of the display device.

[0007] Structurally, a solar cell can include a first electrode, a second electrode, a P-type semiconductor layer, and a first N-type semiconductor layer. The first and second electrodes are located on the same layer, meaning that during the fabrication of a display device, the first and second electrodes can be formed simultaneously on the surface of a certain film layer. The P-type semiconductor layer covers the first electrode, and the first N-type semiconductor layer covers the P-type semiconductor layer and the second electrode. Thus, the P-type semiconductor layer and the first N-type semiconductor layer can be combined to form a PN junction. When this PN junction is illuminated, photogenerated charge carriers can move to the first and second electrodes respectively under the drive of the built-in electric field of the PN junction. These charge carriers include holes and electrons; holes move to the first electrode under the drive of the built-in electric field of the PN junction, and electrons move to the second electrode. Thus, with the first electrode connected to the positive terminal of the energy storage unit in the electronic device, and the second electrode connected to the negative terminal of the energy storage unit in the electronic device, the collection of photogenerated charge carriers can be completed, realizing solar power generation.

[0008] In the embodiments of this application, firstly, solar cells can be used to provide power to the energy storage unit of an electronic device, thereby improving the battery life of the electronic device. Secondly, the portion of the solar cell located in the display area does not overlap with multiple sub-pixels, thus ensuring that the solar cell does not affect the light output of multiple sub-pixels and guaranteeing the display effect of the display device. Thirdly, the first electrode and the second electrode are located on the same layer, with a P-type semiconductor layer covering the first electrode and a first N-type semiconductor layer covering the P-type semiconductor layer and the second electrode. This structural arrangement allows the solar cell to be fabricated using the same processes as other layers in the display device, such as evaporation, deposition, and photolithography, thereby facilitating the fabrication of the display device.

[0009] In some embodiments, the solar cell may further include a second cell section. The second cell section refers to the portion of the solar cell located in the non-display area. The first and second cell sections may be integrally formed; alternatively, the first and second cell sections may be separately connected to an energy storage unit.

[0010] The structure of solar cells will be further expanded below.

[0011] In some embodiments, the solar cell may further include a second N-type semiconductor layer. The second N-type semiconductor layer is located between the first N-type semiconductor layer and the second electrode. That is, the second N-type semiconductor layer covers the second electrode, and the first N-type semiconductor layer covers the P-type semiconductor layer and the second N-type semiconductor layer. Here, the doping concentration of the second N-type semiconductor layer is greater than the doping concentration of the first N-type semiconductor layer. For example, the material of the first N-type semiconductor layer may be undoped amorphous silicon; the material of the second N-type semiconductor layer may be amorphous silicon doped with phosphorus or arsenic; and the P-type semiconductor layer may be amorphous silicon doped with boron. Thus, the second N-type semiconductor layer can serve as an ohmic contact layer between the first N-type semiconductor layer and the second electrode, thereby avoiding the large potential barrier formed by direct contact between the first N-type semiconductor layer and the second electrode, and reducing the contact resistance.

[0012] In some embodiments, the solar cell may further include a third N-type semiconductor layer. The third N-type semiconductor layer covers the first N-type semiconductor layer. Here, the doping concentration of the third N-type semiconductor layer is greater than that of the first N-type semiconductor layer, and the doping concentration of the third N-type semiconductor layer is less than or equal to that of the second N-type semiconductor layer. Thus, electrons in the photogenerated charge carriers can be transported to the second electrode through the third N-type semiconductor, the first N-type semiconductor, and the second N-type semiconductor. Since the third N-type semiconductor has a higher doping concentration than the first N-type semiconductor, which is more conducive to electron transport, electron transport losses can be reduced in this embodiment, thereby improving the power generation efficiency of the solar cell.

[0013] Furthermore, the solar cell also includes a third electrode, which is covered by a third N-type semiconductor layer. Here, the third electrode can be connected to the second electrode. The third electrode is also used to collect electrons from photogenerated carriers. Collecting electrons through the third electrode improves electron collection efficiency, thereby increasing the power generation efficiency of the solar cell.

[0014] In this embodiment, the display device further includes a display panel. The display panel may be an organic light-emitting diode (OLED) display panel or a liquid crystal display (LCD) panel. The positional relationship between the display panel and the solar cell will be described below under two possible scenarios.

[0015] In the first possible scenario, the display panel is an organic light-emitting diode (OLED) display panel. In this case, the display panel includes an array substrate, a plurality of sub-pixels, and an encapsulation layer, with the plurality of sub-pixels located between the array substrate and the encapsulation layer. In this embodiment, the solar cell is located on the surface of the encapsulation layer away from the array substrate.

[0016] Furthermore, the display device also includes a first optical coating, a touch panel, and a second optical coating. The first optical coating covers the encapsulation layer and the solar cell. The touch panel is located on the surface of the first optical coating away from the encapsulation layer, and is situated between the first optical coating and the second optical coating.

[0017] In the second possible scenario, the display panel is a liquid crystal display panel. In this case, the display panel includes an array substrate, a liquid crystal layer, and a color filter substrate. The array substrate and the color filter substrate are aligned, with the liquid crystal layer located between them. The liquid crystal layer includes multiple liquid crystal cells, and the color filter substrate includes multiple color resists, with each liquid crystal cell corresponding to one color resist along the thickness direction of the display device. Each sub-pixel of the multiple sub-pixels includes a corresponding liquid crystal cell and a color resist.

[0018] In one possible embodiment, the solar cell is located on the side of the color filter substrate away from the array substrate.

[0019] In another possible embodiment, the display panel includes a substrate and multiple driving circuits. Each driving circuit corresponds one-to-one with a plurality of sub-pixels, and each driving circuit drives its corresponding sub-pixel. The multiple driving circuits and the solar cell are located on the same side of the substrate, and the first N-type semiconductor layer also serves as the channel for the transistors in the multiple driving circuits. That is, the solar cell is located on the surface of the substrate, and the first N-type semiconductor layer in the solar cell can be reused as the channel for the transistors in the multiple driving circuits.

[0020] Secondly, an electronic device is also provided. The electronic device includes an energy storage unit and a display device as described in any embodiment of the first aspect. A first electrode is connected to the positive terminal of the energy storage unit, and a second electrode is connected to the negative terminal of the energy storage unit, so that the solar cell can charge the energy storage unit.

[0021] The technical effects achieved by the second aspect are similar to those achieved by the corresponding technical means in the first aspect, and will not be repeated here. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the appearance of the first electronic device in the related technology;

[0023] Figure 2 This is a schematic diagram of the appearance of a second type of electronic device in the related technology;

[0024] Figure 3 This is a schematic diagram of the cross-sectional structure of a display device along a third direction in related technologies;

[0025] Figure 4This is a schematic cross-sectional view of a display device along its extension direction in related technologies;

[0026] Figure 5 This is a schematic diagram showing the position of the first type of solar cell provided in this application within a display device;

[0027] Figure 6 This is a schematic cross-sectional view of the first type of solar cell provided in this application embodiment along a third direction;

[0028] Figure 7 This is a schematic diagram of the carrier movement path of the first type of solar cell provided in this application when it is exposed to light;

[0029] Figure 8 This is a schematic diagram showing the positions of the first electrode and the second electrode in the display device according to the embodiments of this application;

[0030] Figure 9 This is a schematic diagram showing the positions of the second type of first electrode and second electrode in the display device according to an embodiment of this application;

[0031] Figure 10 This is a schematic diagram showing the position of the second type of solar cell provided in this application embodiment in a display device;

[0032] Figure 11 This is a schematic diagram showing the positions of the third type of first electrode and second electrode in the display device provided in the embodiments of this application;

[0033] Figure 12 This is a schematic cross-sectional view of the second type of solar cell provided in this application embodiment along a third direction;

[0034] Figure 13 This is a schematic diagram of the band structure of amorphous silicon provided in an embodiment of this application;

[0035] Figure 14 This is a schematic diagram of the cross-sectional structure of the third type of solar cell provided in the embodiments of this application along a third direction;

[0036] Figure 15 This is a schematic diagram of the carrier movement path of the second type of solar cell provided in this application when it is exposed to light;

[0037] Figure 16 This is a schematic diagram of the cross-sectional structure of the fourth type of solar cell provided in this application embodiment along a third direction;

[0038] Figure 17 This is a circuit structure diagram of a driving circuit and a sub-pixel provided in an embodiment of this application;

[0039] Figure 18This is a schematic diagram of the cross-sectional structure of the first array substrate provided in this application embodiment along a third direction;

[0040] Figure 19 This is a schematic cross-sectional view of an array substrate, a pixel limiting layer, and sub-pixels along a third direction, provided in an embodiment of this application.

[0041] Figure 20 This is a schematic cross-sectional view of a display panel along a third direction, provided in an embodiment of this application.

[0042] Figure 21 This is a schematic diagram illustrating the positional relationship between the first type of display panel and the solar cell provided in this application embodiment;

[0043] Figure 22 This is a schematic diagram illustrating the positional relationship between the second type of display panel and the solar cell provided in this application embodiment;

[0044] Figure 23 This is a schematic cross-sectional view of a display device along a third direction, provided in an embodiment of this application.

[0045] Figure 24 This is a schematic diagram illustrating the positional relationship between the third type of display panel and the solar cell provided in this application embodiment;

[0046] Figure 25 This is a schematic diagram illustrating the positional relationship between the fourth type of display panel and the solar cell provided in this application embodiment;

[0047] Figure 26 This is a schematic diagram of the structure of a backlight panel and a display panel provided in an embodiment of this application;

[0048] Figure 27 This is a circuit structure diagram of a driving circuit, pixel electrode, and common electrode provided in an embodiment of this application;

[0049] Figure 28 This is a schematic diagram of the cross-sectional structure of the second type of array substrate along a third direction provided in the embodiments of this application;

[0050] Figure 29 This is a schematic diagram illustrating the positional relationship between an array substrate and a solar cell, provided in an embodiment of this application.

[0051] The meanings of the various symbols in the attached icons are as follows:

[0052] 10. Electronic device; 20. Display device; 201. Display area; 202. Non-display area; 21. Display panel; 212. Subpixel; 214. Array substrate; 2141. First substrate; 2142. Channel; 2143. First insulating layer; 2144. Control electrode; 2145. Second insulating layer; 2146. First interlayer dielectric layer; 2147. First electrode; 2148. Second electrode; 2149. Planarization layer; 21401. Anode; 21401a. Pixel electrode; 21402. First electrode plate; 21403. Second electrode plate; 215. Color filter substrate; 2151. Second substrate; 2152. Color resist; 2153. Black matrix; 2154. Common electrode; 216. Pixel defining layer ; 217, Liquid crystal layer; 2170, Liquid crystal cell; 218, Encapsulation layer; 2182, First encapsulation layer; 2184, Second encapsulation layer; 2186, Third encapsulation layer; 22, Touch panel; 221, First metal layer; 222, Second interlayer dielectric layer; 223, Second metal layer; 23, Solar cell; 2301, First battery section; 2302, Second battery section; 231, Battery substrate; 232, First electrode; 233, Second electrode; 234, P-type semiconductor layer; 235, First N-type semiconductor layer; 236, Second N-type semiconductor layer; 237, Third N-type semiconductor layer; 238, Third electrode; 241, First optical coating; 242, Second optical coating; 25, Backlight panel. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0054] It should be understood that "multiple" as mentioned in this application refers to two or more. In the description of this application, unless otherwise stated, " / " indicates "or," for example, A / B can mean A or B; "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist, for example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, to facilitate a clear description of the technical solutions of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0055] Before providing a detailed explanation of the display device provided in the embodiments of this application, the application scenarios of the display device will be explained first.

[0056] Electronic devices 10 include mobile phones, tablets, laptops, wearable devices, etc. Wearable devices may include, for example, smartwatches, wristbands, etc. Figure 1 and Figure 2 These are schematic diagrams of the appearance of two different electronic devices 10, in which Figure 1 The electronic device 10 shown is a mobile phone. Figure 2 The electronic device 10 shown is a smartwatch.

[0057] like Figure 1 and Figure 2 As shown, the electronic device 10 includes a display device 20. Figure 3 This is a schematic cross-sectional view of a display device 20 along a third direction Z, as described in related technologies. The third direction Z refers to the thickness direction of the display device 20. For ease of description, a first direction X and a second direction Y are also defined here. Both the first direction X and the second direction Y are extension directions of the display device 20, and the first direction X, the second direction Y, and the third direction Z are perpendicular to each other. Figure 3 As shown, along the third direction Z, the display device 20 includes a stacked display panel 21 and a touch panel 22. The display panel 21 is used to display images, and the touch panel 22 is used to detect user touch operations on the display device 20.

[0058] Figure 4 This is a schematic cross-sectional view of a display device 20 along its extension direction in related technologies. For example... Figure 3 and Figure 4 As shown, along the extending direction of the display device 20, the display device 20 includes a display area 201 and a non-display area 202, which are separated by dashed lines. The display area 201 and the non-display area 202 are adjacent to each other; for example, the non-display area 202 may surround the display area 201. The display area 201 refers to the area of ​​the display panel 21 in the display device 20 used to display images. Within the display area 201, the display panel 21 is provided with multiple sub-pixels 212. When the multiple sub-pixels 212 emit light, the display panel 21 displays an image. The brightness of each sub-pixel 212 can be adjusted independently. Here, a sub-pixel 212 refers to the smallest adjustable brightness unit in the display device 20. The multiple sub-pixels 212 are spaced apart to avoid light crosstalk between adjacent sub-pixels 212 when multiple sub-pixels 212 emit light. The non-display area 202 refers to the area of ​​the display panel 21 in the display device 20 that is not used to display images. Within the non-display area 202, the display panel 21 does not have sub-pixels 212. The non-display area 202 can be, for example, the binding area of ​​the display panel 21, etc., which will not be elaborated further. It is easy to understand that... Figure 3In the display device 20 shown, the touch panel 22 only covers the display area 201 of the display device 20. In some other possible cases, the touch panel 22 may also cover the non-display area 202 of the display device 20.

[0059] With the development of science and technology, the frequency of use of electronic devices 10 is increasing, and the battery life problem of electronic devices 10 is becoming more and more serious. In related technologies, the battery life of electronic devices 10 is usually improved by increasing the capacity of the energy storage unit (e.g., a battery). However, the capacity of the energy storage unit is directly proportional to the volume of the energy storage unit. Limited by the internal space of the electronic device 10, the increase in the volume of the energy storage unit has reached a bottleneck, and therefore the increase in the capacity of the energy storage unit has also reached a bottleneck.

[0060] Solar cells are devices that convert light energy into electrical energy through the photoelectric effect, and solar energy is a sustainable and clean energy source. If solar cells can be applied to electronic device 10 to provide power to the electronic device 10, the battery life of the electronic device 10 can be further improved.

[0061] Therefore, this application provides a display device 20 and an electronic device 10. The display device 20 is applied to the electronic device 10, and the display device 20 integrates a solar cell, which can improve the battery life of the electronic device 10.

[0062] The display device 20 provided in the embodiments of this application will be explained in detail below. The display device 20 provided in the embodiments of this application can be applied to the electronic device 10, such as when applied to... Figure 1 and Figure 2 The electronic device 10 shown is integrated with a solar cell 23. Figure 5 This is a schematic diagram showing the position of a solar cell 23 in a display device 20 according to an embodiment of this application. Figure 5As shown, along the extending direction of the display device 20, a plurality of sub-pixels 212 are spaced apart within the display area 201 of the display device 20. The solar cell 23 includes at least a first battery portion 2301, which refers to the portion of the solar cell 23 located in the display area 201 of the display device 20. The first battery portion 2301 can be located on the light-emitting side or the backlight side of the plurality of sub-pixels 212. When the first battery portion 2301 is located on the light-emitting side of the plurality of sub-pixels 212, the first battery portion 2301 and the plurality of sub-pixels 212 do not overlap along the third direction Z. That is, along the third direction Z, the projections of the first battery portion 2301 and the plurality of sub-pixels 212 on the same plane do not overlap. In this way, it can be ensured that the first battery portion 2301 of the solar cell 23 does not affect the light emission rate of the plurality of sub-pixels 212, thereby ensuring the display effect of the display device 20. It is easy to understand that in some other possible embodiments, the first battery portion 2301 and the plurality of sub-pixels 212 may also overlap along the third direction Z.

[0063] Figure 6 This is a schematic cross-sectional view of a solar cell 23 along the third direction Z, provided in an embodiment of this application. Figure 6 As shown, the solar cell 23 includes a first electrode 232, a second electrode 233, a P-type semiconductor layer 234, and a first N-type semiconductor layer 235.

[0064] The materials of the first electrode 232 and the second electrode 233 can be metals, metal oxides, or other conductive materials. For example, the first electrode 232 and the second electrode 233 can be silver electrodes or indium tin oxide (ITO) electrodes. The first electrode 232 and the second electrode 233 are located at the same layer, that is, when fabricating the display device 20, the first electrode 232 and the second electrode 233 can be formed simultaneously on the surface of a certain film layer. Here, for ease of description, the film layer used to support the first electrode 232 and the second electrode 233 is referred to as the battery substrate 231, that is, the first electrode 232 and the second electrode 233 are located on the same surface of the battery substrate 231. The first electrode 232 and the second electrode 233 can be prepared by vapor deposition, by deposition (such as chemical vapor deposition), or by coating and photolithography.

[0065] P-type semiconductors, also known as hole-type semiconductors, are semiconductor materials with specific conductivity formed by doping intrinsic semiconductors with specific impurities. Their primary charge carriers are holes, i.e., positive charge carriers (P). For example, the material of the P-type semiconductor layer 234 can be amorphous silicon (a-Si) doped with boron (B). The P-type semiconductor layer 234 covers the first electrode 232. Here, coverage includes both complete and partial coverage; for example, in... Figure 6 In the illustrated embodiment, the P-type semiconductor layer 234 completely covers the first electrode 232. In some other embodiments not shown, the P-type semiconductor layer 234 may only cover a portion of the first electrode 232, which will not be described further.

[0066] N-type semiconductors, also known as electronic semiconductors, can be intrinsic semiconductors doped with specific impurities to form semiconductor materials with specific conductivity properties; alternatively, intrinsic semiconductors can also be N-type semiconductors. The primary charge carriers in N-type semiconductors are electrons, i.e., negative charge carriers (N). For example, the material of the first N-type semiconductor layer 235 can be amorphous silicon or amorphous silicon doped with phosphorus (P) or arsenic (As). The first N-type semiconductor layer 235 covers the P-type semiconductor layer 234 and the second electrode 233. Thus, the P-type semiconductor layer 234 and the first N-type semiconductor layer 235 can be combined to form a PN junction. The P-type semiconductor layer 234 constitutes the P-region of the PN junction and is connected to the first electrode 232; the first N-type semiconductor layer 235 constitutes the N-region of the PN junction and is connected to the second electrode 233. When the PN junction is illuminated, photogenerated charge carriers (including electrons and holes) can move to the first electrode 232 and the second electrode 233 respectively under the drive of the built-in electric field of the PN junction. For example, Figure 7 As shown, holes (represented by "○") move to the first electrode 232 under the drive of the built-in electric field of the PN junction, and electrons (represented by "·") move to the second electrode 233 under the drive of the built-in electric field of the PN junction. When the first electrode 232 is connected to the positive terminal of the energy storage unit in the electronic device 10, and the second electrode 233 is connected to the negative terminal of the energy storage unit in the electronic device 10, the collection of photogenerated carriers can be completed, realizing solar power generation.

[0067] The display device 20 provided in this application embodiment can use solar cells 23 to provide power to the energy storage unit of electronic device 10, thereby improving the battery life of electronic device 10. Furthermore, the first electrode 232 and the second electrode 233 are located on the same layer, with a P-type semiconductor layer 234 covering the first electrode 232 and a first N-type semiconductor layer 235 covering the P-type semiconductor layer 234 and the second electrode 233. This structural arrangement allows the solar cell 23 to be fabricated using the same processes as other layers in the display device 20, such as evaporation, deposition, and photolithography, thus facilitating the fabrication of the display device 20.

[0068] exist Figure 5 In the display device 20 shown, the solar cell 23 includes a plurality of first battery sections 2301. Based on Figure 5 In some embodiments of the display device 20 shown, the positions of the plurality of first electrodes 232 and the plurality of second electrodes 233 within the display device 20 can be as follows: Figure 8 As shown. In this case, the multiple first electrodes 232 are not connected together, and the multiple second electrodes 233 are also not connected together. That is, the multiple first battery units 2301 are independent of each other. In other embodiments, the positions of the multiple first electrodes 232 and the multiple second electrodes 233 in the display device 20 may also be as shown. Figure 9 As shown. In this case, multiple first electrodes 232 are connected together and extend into the non-display area 202 for connection to the positive electrode of the energy storage unit; multiple second electrodes 233 are connected together and extend into the non-display area 202 for connection to the negative electrode of the energy storage unit. In this case, multiple first battery units 2301 are connected together. It is readily understood that wires for connecting the multiple first electrodes 232 can also be provided in the non-display area 202; wires for connecting the multiple second electrodes 233 can also be provided in the non-display area 202.

[0069] Figure 10 This is a schematic diagram showing the position of another solar cell 23 in the display device 20 according to an embodiment of this application. Figure 10 As shown, the solar cell 23 may further include a second battery section 2302, which refers to the portion of the solar cell 23 located in the non-display area 202 of the display device 20. The second battery section 2302 and the first battery section 2301 may be integrally formed. That is, when manufacturing the display device 20, the second battery section 2302 and the first battery section 2301 are manufactured simultaneously and connected together. In some other embodiments, the second battery section 2302 and the first battery section 2301 may also be manufactured simultaneously but not connected together. In this case, the first battery section 2301 and the second battery section 2302 may be connected to the energy storage unit respectively.

[0070] based on Figure 10 The positions of the plurality of first electrodes 232 and the plurality of second electrodes 233 in the display device 20 shown can be as follows: Figure 11 As shown. In this case, in the non-display area 202 located on any side of the display area 201 (such as the upper, left, right, or lower side of the display area 201), multiple first electrodes 232 and multiple second electrodes 233 can be arranged alternately, and in the alternately arranged multiple first electrodes 232 and multiple second electrodes 233, one end of the multiple first electrodes 232 is connected together, and the other end of the multiple second electrodes 233 is connected together. In other words, in the non-display area 202 located on any side of the display area 201, the multiple first electrodes 232 and multiple second electrodes 233 are arranged in an interdigital pattern. The multiple first electrodes 232 can also be connected to the positive terminal of the energy storage unit through wires, and the multiple second electrodes 233 can be connected to the negative terminal of the energy storage unit through wires, which will not be described in detail here.

[0071] It should be noted that, in the above embodiments, for ease of understanding, an energy storage unit in the electronic device 10 is introduced to describe the solar power generation principle of the display device 20 provided in this application embodiment. In fact, the display device 20 provided in this application embodiment does not include an energy storage unit. That is to say, the energy storage unit exists as an environmental element relative to the display device 20, and its existence should not be construed as a limitation on the display device 20 provided in this application embodiment.

[0072] The structure of the solar cell 23 in the display device 20 provided in this application embodiment will be further explained below from three possible scenarios.

[0073] 1. The first possible scenario.

[0074] Figure 12 This is a schematic cross-sectional view of another solar cell 23 along the third direction Z provided in an embodiment of this application. Figure 12As shown, the solar cell 23 may further include a second N-type semiconductor layer 236. The second N-type semiconductor layer 236 is located between the first N-type semiconductor layer 235 and the second electrode 233. That is, the second N-type semiconductor layer 236 covers the second electrode 233, and the first N-type semiconductor layer 235 covers the P-type semiconductor layer 234 and the second N-type semiconductor layer 236. Here, the doping concentration of the second N-type semiconductor layer 236 is greater than the doping concentration of the first N-type semiconductor layer 235. For example, the first N-type semiconductor layer 235 can be undoped amorphous silicon, i.e., an intrinsic N-type semiconductor. The material of the second N-type semiconductor layer 236 can be amorphous silicon doped with phosphorus or arsenic. Thus, the second N-type semiconductor layer 236 can serve as an ohmic contact layer between the first N-type semiconductor layer 235 and the second electrode 233, thereby avoiding the large potential barrier formed by direct contact between the first N-type semiconductor layer 235 and the second electrode 233 and reducing the contact resistance.

[0075] The reason why undoped amorphous silicon exhibits an N-type structure is explained below.

[0076] Figure 13 This is a schematic diagram of the band structure of amorphous silicon provided in an embodiment of this application, where the horizontal axis represents the electronic state density, in units of m³ / s. -3 The vertical axis represents electron energy, measured in electron volts (eV). For example... Figure 13 As shown, in this band structure, the conduction band bottom level E C The above section represents the conduction band. The conduction band refers to the energy region where electrons possess high energy and can move relatively freely. Electrons in the conduction band can reside in extended conduction band states. Electrons in these states possess sufficient energy to escape the strong bonds of atoms and can move relatively freely within amorphous silicon materials, thus becoming charge carriers participating in electrical conduction. When external forces such as an electric field are applied, these electrons in extended conduction band states will move directionally under the influence of the electric field, forming an electric current. The bottom energy level of the conduction band, E... C The following is the mobility edge E X The above section represents the conduction band tail. The valence band top energy level E... V The following section describes the valence band. The valence band is a low-energy region filled with electrons, which are generally relatively tightly bound by the atoms. Electrons in the valence band can exist in extended valence band states. When these electrons gain sufficient energy (such as by absorbing a photon), they can potentially transition to the conduction band and become charge carriers capable of participating in electrical conduction. The valence band top energy level E... V Above, the upper boundary of the price band E Y The following section represents the valence band tail. There is a mobility gap between the conduction band and the valence band. That is, the mobility gap is the energy level E at the bottom of the conduction band. C Below, the top energy level of the valence band E VThe above section. Due to the large number of defect states in amorphous silicon, these defect states at the Fermi level E F Deep-level local states are formed nearby, capable of capturing electrons and holes.

[0077] As mentioned earlier, electrons in the extended conduction band state possess sufficient energy to escape the strong bondage of atoms and can move relatively freely within amorphous silicon. Electrons in the extended valence band state, when given sufficient energy (such as by absorbing photons), can potentially jump to the conduction band and become charge carriers capable of participating in electrical conduction. In other words, in amorphous silicon, due to its structure, electrons are more easily excited to the conduction band and become charge carriers capable of participating in electrical conduction; therefore, amorphous silicon exhibits an N-type structure.

[0078] 2. The second possible scenario.

[0079] Figure 14 This is a schematic cross-sectional view of another solar cell 23 along the third direction Z provided in the embodiments of this application. Figure 14 As shown, the solar cell 23 may further include a third N-type semiconductor layer 237. The third N-type semiconductor layer 237 covers the first N-type semiconductor layer 235. Here, the doping concentration of the third N-type semiconductor layer 237 is greater than the doping concentration of the first N-type semiconductor layer 235, and the doping concentration of the third N-type semiconductor layer 237 is less than or equal to the doping concentration of the second N-type semiconductor layer 236. The third N-type semiconductor layer 237 may also be amorphous silicon doped with phosphorus or arsenic, and the doping material of the third N-type semiconductor layer 237 may be the same as or different from the doping material of the second N-type semiconductor layer 236.

[0080] Figure 15 This is a schematic diagram of the carrier movement path when the solar cell 23 is illuminated in this embodiment. Figure 15 As shown, in this embodiment, when the PN junction is illuminated, photogenerated carriers still move to the first electrode 232 and the second electrode 233 respectively under the drive of the built-in electric field of the PN junction. Holes move to the first electrode 232 under the drive of the built-in electric field of the PN junction; some electrons can be transported to the second electrode 233 through the first N-type semiconductor and the second N-type semiconductor, while other electrons can be transported through the third N-type semiconductor, and then through the first N-type semiconductor and the second N-type semiconductor to the second electrode 233. Since the third N-type semiconductor has a higher doping concentration than the first N-type semiconductor, it is more conducive to electron transport. Therefore, in this embodiment, the transport loss of electrons transported through the third N-type semiconductor can be reduced, the transport efficiency of photogenerated carriers can be improved, and thus the power generation efficiency of the solar cell 23 can be increased.

[0081] 3. The third possible scenario.

[0082] Figure 16This is a schematic cross-sectional view of another solar cell 23 along the third direction Z provided in the embodiments of this application. Figure 16 As shown, the solar cell 23 may also include a third electrode 238. The material of the third electrode 238 can be a metal, metal oxide, or other conductive material; for example, the third electrode 238 can be a silver electrode or an ITO electrode. The third electrode 238 is covered by a third N-type semiconductor layer 237. Thus, when the PN junction is illuminated, electrons in the photogenerated carriers can be directly collected by the third electrode 238 after entering the third N-type semiconductor layer, compared to... Figure 14 In the solar cell 23 shown, electrons in the third N-type semiconductor no longer need to pass through the first N-type semiconductor and the second N-type semiconductor to reach the second electrode 233. This improves electron collection efficiency, thereby increasing the power generation efficiency of the solar cell 23. In some embodiments, the third electrode 238 and the second electrode 233 can be connected together and jointly connected to the negative electrode of the energy storage unit.

[0083] In the above embodiments, the thickness of each layer in the solar cell 23 is between 0.1 micrometers (μm) and 10 μm. For example, in a specific embodiment, the thickness of the first electrode 232 and the second electrode 233 can be 3 μm, the thickness of the P-type semiconductor layer 234 can be 2 μm, and the thickness of the first N-type semiconductor layer 235, the second N-type semiconductor layer 236, the third N-type semiconductor layer 237, and the third electrode 238 is 3 μm.

[0084] As mentioned above, the display device 20 should also include a display panel 21, in which multiple sub-pixels 212 are located. In this embodiment, the display panel 21 can be an organic light-emitting display (OLED) or a liquid crystal display (LCD). The structure of the display device 20 and the positional relationship between the display panel 21 and the solar cell 23 will be described below under two possible scenarios.

[0085] 1. The first possible scenario is that the display panel 21 is an OLED.

[0086] First, let's introduce the light-emitting principle of OLED.

[0087] When the display panel 21 is an OLED, each of the multiple sub-pixels 212 is an organic light-emitting diode (OLED). Classified by emission color, sub-pixels 212 emitting red light are designated as red (R) sub-pixels, those emitting green light as green (G) sub-pixels, those emitting blue light as blue (B) sub-pixels, and those emitting white light as white (W) sub-pixels. The display panel 21 also includes multiple driving circuits, each corresponding one-to-one with a sub-pixel 212, with each driving circuit driving the corresponding sub-pixel 212 to emit light.

[0088] Figure 17 This is a circuit structure diagram of a driving circuit and a sub-pixel 212 provided in an embodiment of this application. The sub-pixel 212 shown in the figure can be any sub-pixel 212 in the display panel 21. Figure 17 As shown, the driving circuit includes a switching transistor T1, a driving transistor T0, and an energy storage capacitor C0. The first terminal of the switching transistor T1 is used to input the data signal DATA, and the second terminal of the switching transistor T1 is connected to the control terminal of the driving transistor T0 and the first plate of the energy storage capacitor C0. The first terminal of the driving transistor T0 is connected to the second plate of the energy storage capacitor C0 and is used to input the first power signal VDD. The second terminal of the driving transistor T0 is connected to the anode of the sub-pixel 212, and the cathode of the sub-pixel 212 is used to input the second power signal VSS. The control terminal of the switching transistor T1 is used to input the scan signal SCAN. Thus, when the control terminal of the switching transistor T1 receives the scan signal SCAN, the switching transistor T1 is turned on, and the data signal DATA is transmitted through the switching transistor T1 to the control terminal of the driving transistor T0 and stored in the energy storage capacitor C0. At this time, the driving transistor T0 is turned on under the action of the data signal DATA, so that the anode of the sub-pixel 212 receives the first power signal VDD. In this case, the sub-pixel 212 can be turned on under the action of the first power signal VDD and the second power signal VSS. The data signal DATA can control the conduction level of the driving transistor T0, thereby controlling the current flowing through the sub-pixel 212, that is, controlling the brightness of the sub-pixel 212.

[0089] Understandably, the driving circuit can also include more switching transistors and capacitors to offset the turn-on threshold of the driving transistor T0. For example, in some OLEDs, the driving circuit is typically an 8T1C circuit consisting of eight transistors (including one driving transistor T0 and seven switching transistors) and one energy storage capacitor.

[0090] The structure of OLED is described below.

[0091] Based on the light-emitting principle of OLEDs, the display panel 21 needs to include multiple sub-pixels 212 and multiple driving circuits for image display. Therefore, the display panel 21 may include an array substrate 214, multiple sub-pixels 212, and an encapsulation layer 218.

[0092] Figure 18 This is a schematic diagram of a cross-sectional structure of an array substrate 214 along the third direction Z, provided in an embodiment of this application. Figure 18 As shown, the array substrate 214 includes transistors (including a driving transistor T0 and a switching transistor T1). Figure 18 Only the driving transistor T0 and the energy storage capacitor C0 are shown in the diagram, which are used to provide multiple driving circuits.

[0093] Specifically, such as Figure 18As shown, the array substrate 214 includes a first substrate 2141. The first substrate 2141 can be a flexible substrate such as a polyimide (PI) film or a rigid substrate such as glass. A transistor channel 2142 is formed on the first substrate 2141 along the third direction Z, that is, along the stacking direction of the array substrate 2144. In OLEDs, the transistor channel 2142 is typically polycrystalline silicon (p-Si). A first insulating layer 2143 covers the channel 2142 and the first substrate 2141, and a control electrode 2144 of the transistor and a first electrode 21402 of the energy storage capacitor C0 are formed on the first insulating layer 2143. That is, the control electrode 2144 of the transistor and the first electrode 21402 of the energy storage capacitor C0 are located in the same metal layer and are fabricated simultaneously. The second insulating layer 2145 covers the control electrode 2144, the first electrode plate 21402, and the first insulating layer 2143, and the first interlayer dielectric layer 2146 covers the second insulating layer 2145. Here, the first interlayer dielectric layer 2146 serves as an isolation and support layer. On the side of the first interlayer dielectric layer 2146 away from the second insulating layer 2145, the first electrode 2147 and the second electrode 2148 of the transistor are formed, and both the first electrode 2147 and the second electrode 2148 of the transistor penetrate the first interlayer dielectric layer 2146, the second insulating layer 2145, and the first insulating layer 2143 to connect to the channel 2142. On the side of the first interlayer dielectric layer 2146 away from the second insulating layer 2145, the second electrode plate 21403 of the energy storage capacitor C0 is also formed. That is, the second electrode plate 21403 of the energy storage capacitor C0 and the first electrode 2147 and the second electrode 2148 of the transistor are located in the same metal layer and are fabricated simultaneously. The planarization layer 2149 covers the first interlayer dielectric layer 2146, the second electrode 21403, and the first electrode 2147 and the second electrode 2148 of the transistor, providing a flat surface. This flat surface refers to the surface of the planarization layer 2149 that is away from the first interlayer dielectric layer 2146. The anode 21401 of the sub-pixel 212 is formed on the flat surface of the planarization layer 2149, and the anode 21401 penetrates the planarization layer 2149 and is connected to the second electrode 2148 of the driving transistor T0.

[0094] As is easily understood, the array substrate 214 includes multiple anodes 21401, each corresponding to a different driving circuit. Each anode 21401 is connected to the output terminal of its corresponding driving circuit (i.e., the second electrode 2148 of the driving transistor T0). Multiple sub-pixels 212 also correspond to multiple anodes 21401, with each sub-pixel 212 covering its corresponding anode 21401 to achieve electrical connection between the sub-pixel 212 and its corresponding anode 21401. For example, Figure 19This is a schematic cross-sectional view of an array substrate 214, a pixel defining layer 216, and a sub-pixel 212 along the third direction Z, provided in an embodiment of this application. The positional relationship between a sub-pixel 212 and its corresponding anode 21401 can be as follows: Figure 19 As shown. Here, in order to set multiple sub-pixels 212, a pixel defining layer 216 also needs to be set on the array substrate 214. Specifically, before fabricating the multiple sub-pixels 212, the pixel defining layer 216 needs to be fabricated on the array substrate 214. The pixel defining layer 216 is located on the side of the planarization layer 2149 away from the first substrate 2141, and the pixel defining layer 216 and the array substrate 214 are combined to form multiple pits. The multiple pits correspond one-to-one with multiple anodes 21401, and each pit is used to expose at least a portion of the corresponding anode 21401. The multiple sub-pixels 212 are located one-to-one in the multiple pits. In this way, the multiple sub-pixels 212 can be isolated by the pixel defining layer 216, that is, the pixel defining layer 216 is used to divide the multiple sub-pixels 212, so that the multiple sub-pixels 212 are set at intervals to avoid light crosstalk between two adjacent sub-pixels 212.

[0095] based on Figure 19 The structure shown, the cross-sectional structure of the display panel 21 along the third direction Z can be as follows: Figure 20 As shown. See also Figure 20 The display panel 21 also includes an encapsulation layer 218. The encapsulation layer 218 is located on one side of the pixel-defining layer 216 on the array substrate 214, and is combined with the pixel-defining layer 216 to encapsulate multiple sub-pixels 212 within multiple recesses. In other words, multiple sub-pixels 212 are located between the array substrate 214, the pixel-defining layer 216, and the encapsulation layer 218. The encapsulation layer 218 is used to isolate water and oxygen to prevent damage to the sub-pixels 212 from water and oxygen in the air. The encapsulation layer 218 may include a first encapsulation layer 2182, a second encapsulation layer 2184, and a third encapsulation layer 2186 stacked along a third direction Z. The first encapsulation layer 2182 and the third encapsulation layer 2186 may be made of inorganic materials, while the second encapsulation layer 2184 may be made of organic materials. It is understood that cathodes for multiple sub-pixels 212 may also be disposed between the encapsulation layer 218 and the multiple sub-pixels 212.

[0096] The structure of the display device 20 and the positional relationship between the display panel 21 and the solar cell 23 will be described below using two embodiments.

[0097] (1) First embodiment.

[0098] In the first embodiment, the first N-type semiconductor layer 235 in the solar cell 23 is phosphorus- or arsenic-doped, or undoped amorphous silicon; the transistor channel 2142 in the array substrate 214 is polycrystalline silicon (which may be p-type or n-type polycrystalline silicon doped with impurities). In this case, since the first N-type semiconductor layer 235 in the solar cell 23 is made of a different material than the transistor channel 2142 in the display panel 21, the transistor channel 2142 cannot be reused as the first N-type semiconductor layer 235 of the solar cell 23. Based on this, the solar cell 23 can be disposed on the surface of the display panel 21. In this embodiment, along the third direction Z, the first battery portion 2301 and the plurality of sub-pixels 212 may not overlap. It is readily understood that the first battery portion 2301 and the anode 21401 in the display panel 21 may partially overlap.

[0099] The structure of solar cell 23 is as follows Figure 6 Taking the example shown, in this embodiment, the positional relationship between the display panel 21 and the solar cell 23 can be as follows: Figure 21 As shown, the solar cell 23 can be located on the surface of the encapsulation layer 218 of the display panel 21 away from the array substrate 214 (light-emitting side). At this time, the first electrode 232 and the second electrode 233 can be simultaneously formed on the surface of the third encapsulation layer 2186 of the encapsulation layer 218 away from the second encapsulation layer 2184. That is, the third encapsulation layer 2186 serves as the cell substrate 231 of the solar cell 23. Similarly, the structure of the solar cell 23 is as follows... Figure 16 Taking the example shown, in this embodiment, the positional relationship between the display panel 21 and the solar cell 23 can be as follows: Figure 22 As shown. In Figure 22 In the embodiment shown, the third encapsulation layer 2186 is also used as the cell substrate 231 of the solar cell 23.

[0100] based on Figure 22 The positional relationship between the display panel 21 and the solar cell 23 is shown, and the structure of the display device 20 can be as follows: Figure 23 As shown. See also Figure 23The display device 20 also includes a first optical coating 241, a touch panel 22, and a second optical coating 242. The first optical coating 241 covers the encapsulation layer 218 of the solar cell 23 and the display panel 21, improving the light extraction efficiency of the display panel 21. The touch panel 22 is located on the surface of the first optical coating 241 away from the encapsulation layer 218, and is situated between the first optical coating 241 and the second optical coating 242. That is, the second optical coating 242 is located on the side of the touch panel 22 away from the first optical coating 241. The second optical coating 242 also reduces reflected light to improve the light extraction efficiency of the display panel 21. Here, the touch panel 22 may include a first metal layer 221, a second metal layer 223, and a second interlayer dielectric layer 222 located between the first metal layer 221 and the second metal layer 223. The first metal layer 221 and the second metal layer 223 are provided with multiple electrode strips for detecting user touch operations on the display device 20, which will not be described in detail here.

[0101] The structure of solar cell 23 is as follows Figure 6 As shown in the example, in this embodiment, the positional relationship between the display panel 21 and the solar cell 23 can also be as follows: Figure 24 As shown, the solar cell 23 can be located on the surface of the first substrate 2141 of the display panel 21 away from the plurality of sub-pixels 212 (backlight side). At this time, the first electrode 232 and the second electrode 233 can be formed simultaneously on the surface of the first substrate 2141 away from the transistor channel 2142. That is, the first substrate 2141 is used as the cell substrate 231 of the solar cell 23.

[0102] It is readily understood that those skilled in the art can extend the display device 20 based on the above embodiments to obtain embodiments in which the solar cell 23 is disposed at other locations on the display device 20. For example, in one possible embodiment, the solar cell 23 may also be located on the surface of the pixel defining layer 216 away from the first substrate 2141, that is, the solar cell 23 is located between the pixel defining layer 216 and the encapsulation layer 218. Alternatively, in another possible embodiment, the solar cell may also be located between the second insulating layer 2145 and the first interlayer dielectric layer 2146, which will not be elaborated further.

[0103] (2) Second embodiment.

[0104] In the second embodiment, the first N-type semiconductor layer 235 in the solar cell 23 is N-type polycrystalline silicon doped with phosphorus or arsenic; and the transistor channel 2142 in the array substrate 214 is N-type polycrystalline silicon. In this case, since the first N-type semiconductor layer 235 in the solar cell 23 and the transistor channel 2142 in the display panel 21 are of the same material and type, the transistor channel 2142 can be reused as the first N-type semiconductor layer 235 of the solar cell 23 (or, the first N-type semiconductor layer 235 of the solar cell 23 can be reused as the transistor channel 2142). In this embodiment, along the third direction Z, the first battery portion 2301 and the plurality of sub-pixels 212 can partially overlap or completely overlap, or they can not overlap.

[0105] The structure of solar cell 23 is as follows Figure 6 Taking the example shown, in this embodiment, the positional relationship between the display panel 21 and the solar cell 23 can be as follows: Figure 25 As shown. Figure 25 As shown, the first electrode 232 and the second electrode 233 are simultaneously formed on one surface of the first substrate 2141. That is, the first substrate 2141 serves as the cell substrate 231 of the solar cell 23. Since the first N-type semiconductor layer 235 of the solar cell 23 is reused as the transistor channel 2142, the transistor channel 2142 is also fabricated after the solar cell 23 is fabricated on the first substrate 2141. At this point, the first insulating layer 2143 can be fabricated on the side of the first substrate 2141 where the solar cell 23 is fabricated, covering the solar cell 23 and the first substrate 2141. Then, the metal layer (including the control electrode 2144 and the first electrode plate 21402 of the transistor), the second insulating layer 2145, the first interlayer dielectric layer 2146, the metal layer (including the first electrode 2147, the second electrode 2148 of the transistor, and the second electrode plate 21403), the planarization layer 2149, and the anode 21401 are fabricated in sequence to obtain the array substrate 214. In this embodiment, the first electrode 2147 and the second electrode 2148 of the transistor both penetrate the first interlayer dielectric layer 2146, the second insulating layer 2145, and the first insulating layer 2143 to connect to the first N-type semiconductor layer 235.

[0106] It is easy to understand that in the embodiment where the first N-type semiconductor layer 235 of the reused solar cell 23 is the channel 2142 of the transistor, if the structure of the solar cell 23 is as follows... Figure 14As shown, when the solar cell 23 further includes a third N-type semiconductor layer 237, the third N-type semiconductor layer 237 may be provided with through holes through which the first electrode 2147 and the second electrode 2148 of the transistor pass, so that the first electrode 2147 and the second electrode 2148 of the transistor do not need to contact the third N-type semiconductor layer 237. Similarly, if the structure of the solar cell 23 is as follows... Figure 16 As shown, when the solar cell 23 further includes a third N-type semiconductor layer 237 and a third electrode 238, both the third N-type semiconductor layer 237 and the third electrode 238 can be provided with through holes for the first electrode 2147 and the second electrode 2148 of the transistor to pass through, so that the first electrode 2147 and the second electrode 2148 of the transistor do not have to contact the third N-type semiconductor layer 237 and the third electrode 238.

[0107] It should be understood that those skilled in the art can extend the display device 20 based on the above embodiments to obtain embodiments in which the second N-type semiconductor layer 236 of the multiplexed solar cell 23 serves as the transistor channel 2142, or embodiments in which the third N-type semiconductor layer 237 of the multiplexed solar cell 23 serves as the transistor channel 2142. These extensions do not depart from the inventive concept of the display device 20 provided in the embodiments of this application, and should also be understood to be within the scope of disclosure and protection of the embodiments of this application.

[0108] 2. In the second possible scenario, the display panel 21 is an LCD.

[0109] First, let's introduce the light-emitting principle of LCD.

[0110] When the display panel 21 is an LCD, the electronic device 10 also includes a backlight panel 25. Figure 26 This is a schematic diagram of the structure of a backlight panel 25 and a display panel 21 provided in an embodiment of this application, as shown below. Figure 26 As shown, since LCDs cannot emit light themselves, a backlight panel 25 is required to provide a light source for the display panel 21. That is, the display panel 21 is located on the light-emitting side of the backlight panel 25. Here, the display panel 21 includes an array substrate 214, a liquid crystal layer 217, and a color filter substrate 215. The array substrate 214 and the color filter substrate 215 are mounted face-to-face to form a sealed space. The liquid crystal layer 217 is located between the array substrate 214 and the color filter substrate 215, and is disposed within the sealed space formed by the array substrate 214 and the color filter substrate 215.

[0111] like Figure 26As shown, the array substrate 214 includes a first substrate 2141 and a plurality of pixel electrodes 21401a, with the pixel electrodes 21401a located on the side of the first substrate 2141 closest to the liquid crystal layer 217. The liquid crystal layer 217 includes a plurality of liquid crystal cells 2170. The color filter substrate 215 includes a second substrate 2151, a plurality of color resists 2152, a black matrix 2153, and a common electrode 2154, all located on the side of the second substrate 2151 closest to the liquid crystal layer 217. The plurality of color resists 2152 includes red, green, and blue color resists. The plurality of color resists 2152 are separated by black matrices 2153. Each pixel electrode 21401a can be coupled to the common electrode 2154 to form a capacitor. Along the third direction Z, the plurality of pixel electrodes 21401a, the plurality of liquid crystal cells 2170, and the plurality of color resists 2152 correspond one-to-one. Each liquid crystal cell 2170 is located between the corresponding pixel electrode 21401a and the common electrode 2154. In this embodiment, a sub-pixel 212 includes a corresponding liquid crystal cell 2170 and a color resist 2152. Multiple sub-pixels 212 are spaced apart by a black matrix 2153 to avoid light crosstalk between adjacent sub-pixels 212.

[0112] When a pixel electrode 21401a is energized, forming an electric field with the common electrode 2154, the liquid crystal cell 2170 corresponding to that pixel electrode 21401a can rotate under the influence of this electric field. By controlling the voltage of the pixel electrode 21401a, the strength of the electric field formed between the pixel electrode 21401a and the common electrode 2154 can be controlled, thereby controlling the rotation angle of the liquid crystal cell 2170 corresponding to the pixel electrode 21401a. This allows control over the light transmittance of the liquid crystal cell 2170, and thus the brightness of the sub-pixel 212 formed by the liquid crystal cell 2170 and the corresponding color resist 2152. Based on this, the display panel 21 also includes multiple driving circuits, each corresponding to one of the multiple pixel electrodes 21401a. Each driving circuit outputs a voltage to its corresponding pixel electrode 21401a.

[0113] Figure 27 This is a circuit structure diagram of a driving circuit, pixel electrode 21401a, and common electrode 2154 provided in an embodiment of this application. The pixel electrode 21401a shown in the figure can be any pixel electrode 21401a in the display panel 21. Figure 27As shown, pixel electrode 21401a is coupled to common electrode 2154 to form a capacitor, and the liquid crystal cell 2170 corresponding to pixel electrode 21401a is located between pixel electrode 21401a and common electrode 2154. The driving circuit includes transistor T2. The first terminal of transistor T2 is used to input data signal DATA, and the second terminal of transistor T2 is connected to pixel electrode 21401a. The control terminal of transistor T2 is used to input scan signal SCAN. Thus, when the control terminal of transistor T2 receives scan signal SCAN, transistor T2 is turned on, and data signal DATA is transmitted to pixel electrode 21401a through transistor T2. That is, the voltage of data signal DATA is the voltage of pixel electrode 21401a. Therefore, data signal DATA can control the rotation angle of liquid crystal cell 2170, thereby controlling the brightness of sub-pixel 212 composed of liquid crystal cell 2170 and corresponding color resist 2152.

[0114] It is understandable that the drive circuit may include more transistors and capacitors, which will not be elaborated further.

[0115] The structure of the array substrate 214 in the LCD is described below.

[0116] Based on the light-emitting principle of LCD, it is known that in order to display images, the array substrate 214 needs to include multiple driving circuits and multiple pixel electrodes 21401a. Figure 28 This is a schematic diagram of a cross-sectional structure of another array substrate 214 along the third direction Z provided in an embodiment of this application. Figure 28 As shown, the array substrate 214 includes a first substrate 2141. The first substrate 2141 can be a flexible substrate such as a PI film or a rigid substrate such as glass. Along the third direction Z, that is, along the stacking direction of the array substrate 214, a control electrode 2144 of a transistor is formed on the first substrate 2141. A first insulating layer 2143 covers the control electrode 2144 and the first substrate 2141, and a transistor channel 2142 is formed on the first insulating layer 2143. In an LCD, the transistor channel 2142 can be amorphous silicon or polycrystalline silicon. On the side of the channel 2142 away from the first insulating layer 2143, a first electrode 2147 and a second electrode 2148 of the transistor are formed. A pixel electrode 21401a is formed on the second electrode 2148 of the transistor. It is easy to understand that... Figure 28 In the illustrated embodiment, with the third direction Z as upper, the control electrode 2144 is located below the channel 2142. In some other embodiments, the control electrode 2144 may also be located above the channel 2142, in which case the structure of the array substrate 214 is similar to... Figure 18 Similar to the diagram, the only difference is that the array substrate 214 of the LCD may not include the energy storage capacitor C0 (i.e., the first electrode plate 21402 and the second electrode plate 21403), which will not be elaborated further.

[0117] The structure of the display device 20 and the positional relationship between the display panel 21 and the solar cell 23 will be described below using two embodiments.

[0118] (1) First embodiment.

[0119] In the first embodiment, the first N-type semiconductor layer 235 in the solar cell 23 is phosphorus- or arsenic-doped, or undoped amorphous silicon; the transistor channel 2142 in the array substrate 214 is polycrystalline silicon, or boron-doped P-type amorphous silicon. In this case, since the materials of the first N-type semiconductor layer 235 in the solar cell 23 and the transistor channel 2142 in the array substrate 214 are different, the transistor channel 2142 cannot be reused as the first N-type semiconductor layer 235 of the solar cell 23. Based on this, the solar cell 23 can be disposed on the surface of the display panel 21. For example, the solar cell 23 can be disposed on the surface of the second substrate 2151 away from the array substrate 214, that is, on the side of the color filter substrate 215 away from the array substrate 214. In other words, the second substrate 2151 is used as the cell substrate 231 of the solar cell 23. Along the third direction Z, the solar cell 23 can overlap with the black matrix 2153 to avoid affecting the display effect of the display panel 21. In some other embodiments, the solar cell 23 may also be disposed on the surface of the first substrate 2141 near the backlight plate 25, that is, on the side of the array substrate 214 away from the color filter substrate 215. In this case, the first substrate 2141 serves as the cell substrate 231 of the solar cell 23.

[0120] In this embodiment, the display device 20 may also include a first optical coating 241, a touch panel 22, and a second optical coating 242. When the solar cell 23 is disposed on the surface of the second substrate 2151 away from the array substrate 214, the first optical coating 241 may cover the second substrate 2151 and the solar cell 23. The touch panel 22 is located on the surface of the first optical coating 241 away from the encapsulation layer 218, and is situated between the first optical coating 241 and the second optical coating 242; further details will not be provided here.

[0121] (2) Second embodiment.

[0122] In the second embodiment, the transistor channel 2142 in the array substrate 214 is N-type amorphous silicon (such as undoped amorphous silicon) or polycrystalline silicon, and the first N-type semiconductor layer 235 in the solar cell 23 is made of the same material and type as the transistor channel 2142 in the display panel 21. In this case, the transistor channel 2142 can be reused as the first N-type semiconductor layer 235 of the solar cell 23 (or, the first N-type semiconductor layer 235 of the solar cell 23 can be reused as the transistor channel 2142). In this embodiment, along the third direction Z, the first battery portion 2301 and the plurality of sub-pixels 212 can partially overlap or completely overlap, or they can not overlap.

[0123] The structure of solar cell 23 is as follows Figure 6 Taking the example shown, in this embodiment, the positional relationship between the array substrate 214 and the solar cell 23 can be as follows: Figure 29 As shown. Figure 29 As shown, a control electrode 2144 of a transistor is formed on a first substrate 2141. A first insulating layer 2143 covers the control electrode 2144 and the first substrate 2141, and a first electrode 232 and a second electrode 233 of a solar cell 23 are formed on the first insulating layer 2143. That is, the first insulating layer 2143 serves as the cell substrate 231 of the solar cell 23. Since the first N-type semiconductor layer 235 of the solar cell 23 is reused as the transistor channel 2142, the transistor channel 2142 is also fabricated after the solar cell 23 is fabricated on the first substrate 2141. At this point, the first electrode 2147 and the second electrode 2148 of the transistor can be fabricated on the first N-type semiconductor layer 235. After that, the pixel electrode 21401a is fabricated to obtain the array substrate 214.

[0124] As is readily understood, in some other embodiments, the structure of the solar cell 23 is as follows: Figure 6 As shown, the positional relationship between the array substrate 214 and the solar cell 23 can also be... Figure 25 Similar to the diagram, the only difference is that the array substrate 214 of the LCD may not include the energy storage capacitor C0 (i.e., the first electrode plate 21402 and the second electrode plate 21403), which will not be elaborated further.

[0125] It is easy to understand that in the embodiment where the first N-type semiconductor layer 235 of the reused solar cell 23 is the channel 2142 of the transistor, if the structure of the solar cell 23 is as follows... Figure 14As shown, when the solar cell 23 further includes a third N-type semiconductor layer 237, the third N-type semiconductor layer 237 may be provided with through holes through which the first electrode 2147 and the second electrode 2148 of the transistor pass, so that the first electrode 2147 and the second electrode 2148 of the transistor do not contact the third N-type semiconductor layer 237; and an insulating layer may also be provided between the third N-type semiconductor layer 237 and the first electrode 2147 and the second electrode 2148. Similarly, if the structure of the solar cell 23 is as follows... Figure 16 As shown, when the solar cell 23 further includes a third N-type semiconductor layer 237 and a third electrode 238, both the third N-type semiconductor layer 237 and the third electrode 238 can be provided with through holes for the first electrode 2147 and the second electrode 2148 of the transistor to pass through, so that the first electrode 2147 and the second electrode 2148 of the transistor do not have to contact the third N-type semiconductor layer 237 and the third electrode 238; and an insulating layer can also be provided between the third electrode 238 and the first electrode 2147 and the second electrode 2148 to avoid short circuit between the third electrode 238 and the first electrode 2147 and the second electrode 2148.

[0126] It should be understood that those skilled in the art can extend the display device 20 based on the above embodiments to obtain embodiments in which the second N-type semiconductor layer 236 of the multiplexed solar cell 23 serves as the transistor channel 2142, or embodiments in which the third N-type semiconductor layer 237 of the multiplexed solar cell 23 serves as the transistor channel 2142. These extensions do not depart from the inventive concept of the display device 20 provided in the embodiments of this application, and should also be understood to be within the scope of disclosure and protection of the embodiments of this application.

[0127] In this embodiment, the solar cell 23 can be fabricated using the fabrication process of the display panel 21 (or array substrate 214). That is, when the display panel 21 is obtained by evaporation using a mask, the solar cell 23 can also be obtained by evaporation using a mask; when the display panel 21 is obtained by a deposition process, the solar cell 23 can also be obtained by a deposition process; when the display panel 21 is fabricated by a coating and photolithography process, the solar cell 23 can also be fabricated by a coating and photolithography process.

[0128] This application also provides an electronic device 10. The electronic device 10 includes an energy storage unit and a display device 20 as described in any of the above embodiments. A first electrode 232 is connected to the positive terminal of the energy storage unit, and a second electrode 233 is connected to the negative terminal of the energy storage unit, so that the energy storage unit can be charged when the solar cell 23 generates electricity.

[0129] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A display device, used in electronic devices, characterized in that, The display device includes a display area and a non-display area, the display area and the non-display area being adjacent to each other; the display area is provided with a plurality of sub-pixels, and the plurality of sub-pixels are spaced apart along the extending direction of the display device; The display device further includes a solar cell, which includes a first battery section located in the display area and along the thickness direction of the display device. The first battery section does not overlap with the plurality of sub-pixels, and the thickness direction of the display device is perpendicular to the extension direction of the display device. The solar cell includes a first electrode, a second electrode, a P-type semiconductor layer, and a first N-type semiconductor layer; the first electrode and the second electrode are located on the same layer, the P-type semiconductor layer covers the first electrode, and the first N-type semiconductor layer covers the P-type semiconductor layer and the second electrode; The display device further includes a display panel, which includes a plurality of driving circuits, each of which corresponds to a plurality of sub-pixels. Each driving circuit is used to drive the corresponding sub-pixel. The driving circuit includes a transistor, and the first N-type semiconductor layer also serves as the channel of the transistor.

2. The display device as claimed in claim 1, characterized in that, The solar cell further includes a second N-type semiconductor layer; The second N-type semiconductor layer is located between the first N-type semiconductor layer and the second electrode, and the doping concentration of the second N-type semiconductor layer is greater than that of the first N-type semiconductor layer.

3. The display device as claimed in claim 2, characterized in that, The solar cell also includes a third N-type semiconductor layer; The third N-type semiconductor layer covers the first N-type semiconductor layer, the doping concentration of the third N-type semiconductor layer is greater than the doping concentration of the first N-type semiconductor layer, and the doping concentration of the third N-type semiconductor layer is less than or equal to the doping concentration of the second N-type semiconductor layer.

4. The display device as claimed in claim 3, characterized in that, The solar cell also includes a third electrode that covers the third N-type semiconductor layer.

5. The display device according to any one of claims 1 to 4, characterized in that, The solar cell further includes a second battery section located in the non-display area, and the first battery section and the second battery section are integrally formed.

6. The display device according to any one of claims 1 to 4, characterized in that, The display panel includes an array substrate, the plurality of sub-pixels, and an encapsulation layer. The array substrate includes the plurality of driving circuits, and the plurality of sub-pixels are located between the array substrate and the encapsulation layer.

7. The display device as claimed in claim 6, characterized in that, The display device further includes a first optical coating, a touch panel, and a second optical coating; The first optical coating covers the encapsulation layer; the touch panel is located on the surface of the first optical coating away from the encapsulation layer, and the touch panel is located between the first optical coating and the second optical coating.

8. The display device according to any one of claims 1 to 4, characterized in that, The display panel includes an array substrate, a liquid crystal layer, and a color filter substrate. The array substrate and the color filter substrate are disposed opposite each other, and the liquid crystal layer is located between the array substrate and the color filter substrate. The array substrate includes multiple driving circuits and multiple pixel electrodes, with each driving circuit connected to a corresponding pixel electrode. The liquid crystal layer includes multiple liquid crystal cells, and the color filter substrate includes multiple color resists. Along the thickness direction of the display device, each liquid crystal cell corresponds to a corresponding color resist. Any one of the multiple sub-pixels includes a corresponding liquid crystal cell and a color resist.

9. The display device according to any one of claims 1 to 4, characterized in that, The first N-type semiconductor layer is an amorphous silicon semiconductor layer.

10. An electronic device, characterized in that, The device includes an energy storage unit and a display device as described in any one of claims 1 to 9, wherein the first electrode is connected to the positive electrode of the energy storage unit, and the second electrode is connected to the negative electrode of the energy storage unit, so that the solar cell charges the energy storage unit.

Images