Hash implementation method, device and equipment for CPU multi-port pipeline optimization and medium

Abstract

The application relates to the computer technical field, in particular to a CPU multi-port pipeline optimization hash implementation method and device, equipment and medium. The method comprises the following steps: obtaining input data; performing hash calculation on the input data by using a target seed to obtain an abstract instruction sequence generated according to a multi-port pipeline of a CPU architecture to be optimized, wherein the abstract instruction sequence comprises a plurality of instruction types in a predefined instruction set template; and compiling the abstract instruction sequence into a machine code sequence of the CPU architecture to control the machine code sequence to run on the CPU architecture. The different instruction types supported by each port are fully utilized, too many instructions requiring the same port are avoided from being stacked together to cause a bottleneck, and the purpose of improving the performance of the CPU architecture is achieved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, device and medium for optimizing hash implementation in a CPU multi-port pipeline. Background Technology

[0002] With the development of CPU technology, CPU microarchitectures are becoming increasingly diverse. Different processor microarchitectures have different superscalar pipelines; therefore, hash-based implementations of CPU multi-port pipeline optimization have become a mainstream research direction. Multi-port pipeline optimization is mainly achieved through instruction scheduling across multiple execution ports. Since different CPU architectures have different numbers of execution ports, and the types of instructions executed on different execution ports also differ, there is an urgent need to provide a multi-port pipeline optimization method that can adapt to different CPU architectures. Summary of the Invention

[0003] In view of this, one of the technical problems solved by the embodiments of this application is to provide a hash implementation method, apparatus, device and medium for CPU multi-port pipeline optimization, which solves the problem that multi-port pipeline optimization in the prior art cannot be adapted to different CPU architectures.

[0004] The challenges include rapidly adapting to new types of attacks and effectively predicting and blocking dynamic attack chains.

[0005] According to a first aspect of the embodiments of this application, a hash implementation method for CPU multi-port pipeline optimization is provided, the method comprising:

[0006] Get the input data;

[0007] The input data is hashed using the target seed to obtain an abstract instruction sequence generated by the multi-port pipeline of the CPU architecture to be optimized. The abstract instruction sequence includes multiple instruction types from a predefined instruction set template.

[0008] The abstract instruction sequence is compiled into a machine code sequence based on the CPU architecture, and the machine code sequence is processed by a multi-port pipeline based on the CPU architecture.

[0009] A second aspect of this application discloses a hash implementation apparatus optimized for CPU multi-port pipelines, the apparatus comprising:

[0010] The input data acquisition module is configured to acquire input data;

[0011] The hash function generation module is configured to perform hash calculations on the input data using the target seed to obtain an abstract instruction sequence generated by the multi-port pipeline of the CPU architecture to be optimized. The abstract instruction sequence includes multiple instruction types in a predefined instruction set template.

[0012] The machine code compilation module is configured to compile abstract instruction sequences into machine code sequences for CPU architecture, and to process the machine code sequences in a multi-port pipeline based on the CPU architecture.

[0013] A third aspect of this application discloses an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described method.

[0014] A fourth aspect of this application discloses a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described method.

[0015] This application's embodiments introduce a seed to perform hash calculations on input data according to the CPU architecture, dynamically generating a one-time abstract instruction sequence. The abstract instruction sequence includes multiple instruction types from a predefined instruction set template. The abstract instruction sequence is compiled according to the execution port of the CPU architecture to obtain the corresponding machine code sequence, thereby controlling the machine code sequence to run on the CPU architecture. This method of generating a completely new and unique hash function based on the microarchitecture type by changing the seed accelerates hash calculation, achieves parallel acceleration, and improves the performance of specific hardware. The CPU architecture provides a basis for selecting instructions for dynamic code generation to adapt to the characteristics of different execution ports, fully utilize the different instruction types supported by each port, and avoid stacking too many instructions that require the same port together, thus creating a bottleneck and improving the performance of the CPU architecture. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] Figure 1 A flowchart illustrating a hash implementation method for CPU multi-port pipeline optimization provided in one embodiment of this application;

[0018] Figure 2 This is a schematic diagram of a hash implementation apparatus for CPU multi-port pipeline optimization provided in one embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0020] It should be noted that although functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart.

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0022] According to one embodiment of this application, a hash implementation method optimized for CPU multi-port pipelines is provided, such as... Figure 1 As shown, the method includes steps S101, S102 and S103.

[0023] Step S101: Obtain input data.

[0024] Step S102: Use the target seed to perform hash calculation on the input data to obtain an abstract instruction sequence generated by the multi-port pipeline of the CPU architecture to be optimized. The abstract instruction sequence includes multiple instruction types in the predefined instruction set template.

[0025] Specifically, a preset seed generation strategy can be used to obtain the target seed.

[0026] Specifically, different microarchitecture CPUs have different integer execution ports; for example, the Ivy Bridge architecture uses ports P0, P1, and P5. The hash function generated by the CPU architecture's multi-port pipeline identifies the instruction types included in it.

[0027] In this embodiment of the application, the instruction set template provides a variety of instruction types, including multiplication, addition, subtraction, XOR, shift and other operations.

[0028] Specifically, different microarchitecture CPUs generate different abstract instruction sequences through hash calculations. For example, if the microarchitecture CPU is Ivy Bridge or AMD, the result of instruction selection in the instruction set template will be different for these two architectures, thus generating different abstract instruction sequences.

[0029] Specifically, the SipHash algorithm can be used to transform the seed into a deterministic random stream, thereby constructing a unique hash function based on the decision points of the multi-port pipeline, such as port constraints.

[0030] Step S103: Compile the abstract instruction sequence into a machine code sequence based on the CPU architecture, and process the machine code sequence using a multi-port pipeline based on the CPU architecture.

[0031] Different manufacturers support different instruction set architectures; for example, Intel CPUs and AMD CPUs are compatible with the x64 instruction set architecture. This application generates instruction codes supported by different microarchitectures and selects the appropriate ports for execution.

[0032] Specifically, different microarchitectures have different execution port characteristics. For example, the three superscalar pipelines of the Ivy Bridge architecture CPU process integer micro-operations through ports P0, P1, and P5. Among them, P0 supports the functions of addition, subtraction, bitwise operations, shifting, and partial branching; P1 supports the functions of addition, bitwise operations, and multiplication (the only multiplication port); and P5 supports the functions of addition, bitwise operations, shifting, rotation, and branching.

[0033] Specifically, after generating the machine code sequence, the compiler writes it into the executable region of memory, allowing for direct execution later. In applications, a predefined function can be called to set the memory access permissions for writing the machine code sequence to executable.

[0034] This application's embodiments introduce a seed to perform hash calculations on input data according to the CPU architecture, dynamically generating a one-time abstract instruction sequence. The abstract instruction sequence includes multiple instruction types from a predefined instruction set template. The abstract instruction sequence is compiled according to the execution port of the CPU architecture to obtain the corresponding machine code sequence, thereby controlling the machine code sequence to run on the CPU architecture. This method of generating a completely new and unique hash function based on the microarchitecture type by changing the seed accelerates hash calculation, achieves parallel acceleration, and improves the performance of specific hardware. The CPU architecture provides a basis for selecting instructions for dynamic code generation to adapt to the characteristics of different execution ports, fully utilize the different instruction types supported by each port, and avoid stacking too many instructions that require the same port together, thus creating a bottleneck and improving the performance of the CPU architecture.

[0035] In some embodiments, the instruction type includes at least:

[0036] The operations between registers include UMULH_R, SMULH_R, MUL_R, SUB_R, XOR_R, and ADD_RS, which respectively represent multiplying unsigned 64-bit registers and taking the high 64 bits, multiplying signed 64-bit registers and taking the high 64 bits, register multiplication, register subtraction, XOR operation between registers, and adding registers after shifting bits after multiplication.

[0037] Register and constant operations, including ROR_C, ADD_C, and XOR_C, represent register and constant bit operations, register and constant addition operations, and register and constant XOR operations, respectively.

[0038] Control flow includes the conditional jump flag TARGET and the conditional branch BRANCH.

[0039] Of the instruction types mentioned above, UMULH_R and SMULH_R are not directly supported by GPU / FPGA / CPU-AVX, while TARGET and BRANCH can increase execution difficulty, and other instruction types can increase the randomness of the computation results. Therefore, by inserting a large number of conditional branches (BRANCH) into the abstract instruction sequence, the GPU's SIMT parallel model can be disrupted. Since the rarely used instructions UMULH_R and SMULH_R can cause GPU / FPGA / CPU-AVX latency to spike due to the lack of direct support for these instructions, for example, UMULH_R (unsigned multiplication with high-order bits) requires dozens of instructions to simulate on GPU / FPGA, thus GPU / FPGA does not have a parallel advantage. This application uses the above-mentioned instruction types to cover the necessary operations required by different microarchitectures, thereby achieving cross-platform applicability of instruction sets independent of architecture.

[0040] In some embodiments, step S102 further includes:

[0041] Determine the port constraint rules for the CPU architecture;

[0042] Using the target seed, instructions are selected from the instruction set template according to the port constraint rules, and dynamic code is generated based on the selection results to obtain an abstract instruction sequence.

[0043] Specifically, different microarchitecture CPUs correspond to different port constraint rules, meaning that different microarchitectures limit the number or proportion of instructions executed on different ports. For example, in the Ivy Bridge architecture, the P0 / P1 / P5 execution ports are the core of high-performance integer arithmetic, and the port constraint rule in this architecture is multiplication ≤ 33%.

[0044] In some embodiments, the step of determining the port constraint rules of the CPU architecture further includes:

[0045] The CPU architecture is matched against a pre-defined rule base, which includes rule files for each of the various microarchitectures.

[0046] If the CPU architecture does not match the rule base, the default rule generator is used to analyze the architecture-related files of the target microarchitecture, and the rule base is updated after the rule files of the target microarchitecture are obtained.

[0047] When applying this technology, if the rule base includes Ivy Bridge and ARM Cortex-X architectures, and the target microarchitecture is RISC-V, a pre-defined rule generator is needed to obtain architecture-related documents for RISC-V, such as architecture manuals. Based on the architecture manuals, the port functions are analyzed, and after benchmarking to determine instruction latency or throughput, the cell size is determined according to the chip design documentation. This analysis improves the compatibility of this application with different architectures. This application directly generates computation-related machine code from the seed and places it in contiguous memory (e.g., through EMIT_U64 / 32 / 16 / 8), which is the implementation of JIT. The JIT code is platform-dependent and requires the generation of assembly code for the corresponding platform, such as x64 or a64.

[0048] In some embodiments, step S103 further includes: using a predefined machine code compilation module to call macros of the target microarchitecture to transform the abstract instruction sequence to obtain the machine code sequence of the target microarchitecture; writing the machine code sequence into memory for execution by the multi-port pipeline of the CPU architecture.

[0049] Specifically, the machine code compilation module provides different JIT assembly instructions for different microarchitectures. For example, assuming the target microarchitecture is Ivy Bridge, the macros called include EMIT_U64 and EMIT_BYTE. Assuming the abstract instruction is UMULH_R, the corresponding JIT assembly instructions are as follows:

[0050] EMIT_U64(pos,0x8b4ce0f749c08b49|((uint64_t)instr->src)<<40)|(((uint64_t)inst r->dst)<<16)); EMIT_BYTE(pos,0xc2+8*instr->dst) indicates that the generated machine code is placed into the executable memory as a 64-bit unsigned integer.

[0051] In some embodiments, the step S103 of writing the machine code sequence into memory and executing it using a multi-port pipeline of the CPU architecture specifically includes: performing port allocation processing on the machine code sequence according to the multi-port pipeline of the CPU architecture.

[0052] Specifically, multi-port pipelines for different microarchitectures can be provided by reading port mapping tables. For example, the CPU architecture can be matched against the port mapping table, and the matched port rules can be used as the basis for port selection. For instance, instructions performing multiplication operations can be scheduled to port P1 (Ivy Bridge architecture), while other instructions are dynamically allocated according to port load to avoid port contention.

[0053] One embodiment of this application provides a hash implementation apparatus optimized for CPU multi-port pipelines, such as... Figure 2 As shown, the device 20 includes: an input data acquisition module 201, a hash function generation module 202, and a machine code compilation module 203.

[0054] The input data acquisition module 201 is configured to acquire input data;

[0055] The hash function generation module 202 is configured to perform hash calculation on the input data using the target seed to obtain an abstract instruction sequence generated according to the multi-port pipeline of the CPU architecture to be optimized. The abstract instruction sequence includes multiple instruction types in a predefined instruction set template.

[0056] Machine code compilation module 203 is configured to compile abstract instruction sequences into machine code sequences for the CPU architecture and control the execution of the machine code sequences on the CPU architecture.

[0057] This application's embodiments introduce a seed to perform hash calculations on input data according to the CPU architecture, dynamically generating a one-time abstract instruction sequence. The abstract instruction sequence includes multiple instruction types from a predefined instruction set template. The abstract instruction sequence is compiled according to the execution port of the CPU architecture to obtain the corresponding machine code sequence, thereby controlling the machine code sequence to run on the CPU architecture. This method of generating a completely new and unique hash function based on the microarchitecture type by changing the seed accelerates hash calculation, achieves parallel acceleration, and improves the performance of specific hardware. The CPU architecture provides a basis for selecting instructions for dynamic code generation to adapt to the characteristics of different execution ports, fully utilize the different instruction types supported by each port, and avoid stacking too many instructions that require the same port together, thus creating a bottleneck and improving the performance of the CPU architecture.

[0058] Furthermore, the instruction types include at least:

[0059] The operations between registers include UMULH_R, SMULH_R, MUL_R, SUB_R, XOR_R, and ADD_RS, which respectively represent multiplying unsigned 64-bit registers and taking the high 64 bits, multiplying signed 64-bit registers and taking the high 64 bits, register multiplication, register subtraction, XOR operation between registers, and adding registers after shifting bits after multiplication.

[0060] Register and constant operations, including ROR_C, ADD_C, and XOR_C, represent register and constant bit operations, register and constant addition operations, and register and constant XOR operations, respectively.

[0061] Control flow operations include the conditional jump flag TARGET and the conditional branch BRANCH.

[0062] Furthermore, the hash function generation module includes:

[0063] The rule determination submodule is used to determine the port constraint rules of the CPU architecture;

[0064] The instruction selection submodule is used to select instructions from the instruction set template according to the port constraint rules using the target seed, and generate dynamic code based on the selection result to obtain an abstract instruction sequence.

[0065] Furthermore, the rule determination submodule includes:

[0066] The rule matching unit is used to match the CPU architecture in a preset rule base, which includes rule files for each of the various microarchitectures.

[0067] The rule base update unit is used to analyze the architecture-related files of the target architecture using a preset rule generator if the target architecture does not match the rule base, and then update the rule base after obtaining the rule files of the target microarchitecture.

[0068] Furthermore, the multi-port pipeline provides multiple integer execution ports for the target microarchitecture.

[0069] Furthermore, the machine code compilation module includes:

[0070] The macro conversion submodule is used to utilize a predefined machine code compilation module to call macros of the target microarchitecture to convert the abstract instruction sequence into the machine code sequence of the target microarchitecture.

[0071] The machine code execution submodule is used to write machine code sequences into memory for execution by a multi-port pipeline based on the CPU architecture.

[0072] The hash implementation apparatus for CPU multi-port pipeline optimization in this embodiment can execute the hash implementation method for CPU multi-port pipeline optimization shown in the embodiment of this application. The implementation principle is similar and will not be described again here.

[0073] Another embodiment of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-described method.

[0074] Specifically, the processor can be a CPU, a general-purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, transistor logic device, hardware component, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0075] Specifically, the processor connects to the memory via a bus, which may include a path for transmitting information. The bus can be a PCI bus or an EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc.

[0076] The memory may be ROM or other types of static storage devices that can store static information and instructions, RAM or other types of dynamic storage devices that can store information and instructions, or EEPROM, CD-ROM or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.

[0077] Optionally, the memory stores the code of a computer program that executes the scheme of this application, and the execution is controlled by a processor. The processor executes the application code stored in the memory to implement the operation of the apparatus provided in the above embodiments.

[0078] Another embodiment of this application provides a computer-readable storage medium storing computer-executable instructions for performing the methods provided in the above embodiments.

[0079] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0080] Those skilled in the art will understand that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0081] The above is a detailed description of the preferred embodiments of this application. However, this application is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A hash implementation method optimized for CPU multi-port pipelines, characterized in that, include: Get the input data; The input data is hashed using the target seed to obtain an abstract instruction sequence generated by a multi-port pipeline according to the CPU architecture to be optimized. The abstract instruction sequence includes multiple instruction types in a predefined instruction set template. The abstract instruction sequence is compiled into a machine code sequence of the CPU architecture, and the machine code sequence is processed by a multi-port pipeline based on the CPU architecture. The instruction types include at least: The operations between registers include UMULH_R, SMULH_R, MUL_R, SUB_R, XOR_R, and ADD_RS, which respectively represent multiplying unsigned 64-bit registers and taking the high 64 bits, multiplying signed 64-bit registers and taking the high 64 bits, register multiplication, register subtraction, XOR operation between registers, and adding registers after shifting bits after multiplication. Register and constant operations, including ROR_C, ADD_C, and XOR_C, represent register and constant bit operations, register and constant addition operations, and register and constant XOR operations, respectively. Control flow operations include the conditional jump flag TARGET and the conditional branch BRANCH; The step of hashing the input data using the target seed to obtain an abstract instruction sequence generated according to the CPU architecture to be optimized includes: Determine the port constraint rules for the CPU architecture; Using the target seed, instructions are selected in the instruction set template according to the port constraint rules, and dynamic code is generated based on the selection result to obtain the abstract instruction sequence.

2. The method according to claim 1, characterized in that, The port constraint rules for determining the CPU architecture include: The CPU architecture is matched against a preset rule base, which includes rule files for each of the various microarchitectures. If the CPU architecture does not match the rule base, the architecture-related files of the CPU architecture are analyzed using a preset rule generator, and the rule base is updated after obtaining the rule files of the CPU architecture.

3. The method according to claim 1, characterized in that, The multi-port pipeline consists of multiple integer execution ports of the CPU architecture.

4. The method according to claim 1, characterized in that, The step of compiling the abstract instruction sequence into a machine code sequence for the CPU architecture and controlling the machine code sequence to run on the CPU architecture includes: Using a predefined machine code compilation module, the abstract instruction sequence is transformed by calling the macros of the CPU architecture to obtain the machine code sequence of the CPU architecture; The machine code sequence is written into memory and executed by the multi-port pipeline of the CPU architecture.

5. The method according to claim 1, characterized in that, The step of writing the machine code sequence into memory is executed by the multi-port pipeline of the CPU architecture, including: Port allocation processing is performed on the machine code sequence according to the multi-port pipeline of the CPU architecture.

6. A hash implementation device optimized for CPU multi-port pipelines, characterized in that, include: The input data acquisition module is configured to acquire input data; The hash function generation module is configured to perform hash calculation on the input data using the target seed to obtain an abstract instruction sequence generated according to the multi-port pipeline of the CPU architecture to be optimized. The abstract instruction sequence includes multiple instruction types in a predefined instruction set template. A machine code compilation module is configured to compile the abstract instruction sequence into a machine code sequence of the CPU architecture and control the machine code sequence to run on the CPU architecture. The instruction types include at least: The operations between registers include UMULH_R, SMULH_R, MUL_R, SUB_R, XOR_R, and ADD_RS, which respectively represent multiplying unsigned 64-bit registers and taking the high 64 bits, multiplying signed 64-bit registers and taking the high 64 bits, register multiplication, register subtraction, XOR operation between registers, and adding registers after shifting bits after multiplication. Register and constant operations, including ROR_C, ADD_C, and XOR_C, represent register and constant bit operations, register and constant addition operations, and register and constant XOR operations, respectively. Control flow operations include the conditional jump flag TARGET and the conditional branch BRANCH; The hash function generation module includes: The rule determination submodule is used to determine the port constraint rules of the CPU architecture; The instruction selection submodule is used to select instructions from the instruction set template according to the port constraint rules using the target seed, and generate dynamic code based on the selection result to obtain an abstract instruction sequence.

7. An electronic device, characterized in that, The device includes a processor and a memory, the memory storing computer-readable instructions, and the processor being configured to execute the computer-readable instructions, wherein the computer-readable instructions, when executed, perform the method according to any one of claims 1 to 5.

8. A computer-readable storage medium storing computer-executable instructions for performing the method according to any one of claims 1 to 5.

Images