A nonlinear matrix operation method based on memristor

Abstract

The application belongs to the technical field of signal analysis and processing, and particularly relates to a nonlinear matrix operation method based on a memristor, which comprises the following steps: obtaining an operation circuit of a nonlinear matrix operation to be executed according to a nonlinear matrix operation expression between a matrix to be operated and an operation target quantity; the operation circuit comprises a calculation circuit and a constraint circuit; the calculation circuit is obtained according to the expression and is realized by a memristor array and its input and output; the memristor array represents the matrix to be operated through the conductance values of the memristors; the input is an input for making the output the target quantity and is controlled by the constraint circuit; the constraint circuit is obtained according to a constraint relationship; the relationship is a relationship that should be met between the input and the output of the calculation circuit when the output of the calculation circuit is the target quantity, which is obtained through the nonlinear matrix operation; the input is the input and the output of the calculation circuit; and the output provides the input for the calculation circuit in a negative feedback mode. The application can reduce the complexity and the time delay of the nonlinear matrix operation.

Description

Technical Field

[0001] This invention belongs to the technical field of signal analysis and processing, and more specifically, relates to a nonlinear matrix operation method based on memristors. Background Technology

[0002] Modern communication systems increase the number of antennas and employ massive MIMO (Multiple Input Multiple Output) technology to effectively improve spectral and energy efficiency by utilizing the spatial resources of wireless channels. In massive MIMO systems, algorithms for precoding matrix solving and signal detection often require numerous nonlinear matrix operations. Taking QR decomposition as an example, this operation decomposes the target matrix into a combination of upper triangular and unitary matrices, and is one of the important methods for matrix inversion and the deployment of nonlinear precoding algorithms in massive MIMO systems.

[0003] However, nonlinear matrix operations are often highly complex. In large-scale MIMO systems, as the number of antennas increases, the dimension of the channel matrix also increases, resulting in extremely high computational complexity and latency when processing nonlinear matrix operations. Furthermore, the wireless channel environment is highly time-varying; excessively long processing times will cause channel information to become outdated, generating additional signal interference and limiting the performance of the communication system.

[0004] Current computer systems primarily employ the von Neumann architecture, which separates data storage from computation units. During computation, data is read from storage via a bus before the computation unit completes the operation. When faced with numerous complex computational tasks, this separation of data and computation units results in high latency and power consumption. In-memory computing (IMC) is a novel architecture that combines storage and computation units. By utilizing memory directly for computation, it eliminates data transfer, offering lower latency and higher power efficiency compared to the von Neumann architecture. Memristors, a novel optoelectronic device, can have their conductance state non-volatilely changed by an external signal, making them a promising candidate for deploying IMC architectures. By combining memristors into an array of cross-nodes, matrix-vector multiplication can be achieved using Ohm's law and Kirchhoff's laws. Parallel implementation. Based on this, a large amount of research has focused on accelerating deployments using memristor arrays for computation: Mohammed A. Zidan et al. transformed the Poisson equation into an iterative process of matrix-vector multiplication (MVM) deployable with memristor arrays using the Jacobi method, thus achieving the solution of the differential equation using memristors. Zhong Sun's team at Peking University designed the circuit structure and completed simulation calculations such as matrix inversion and least squares based on memristors. Shi-Jun Liang and Feng Miao's team at Nanjing University built an orthogonal frequency-division multiplexing (OFDM) transceiver with an in-memory computing architecture using memristor arrays, achieving a bit error rate of 0 / 480. Li Chen's team at the University of Science and Technology of China transformed the receiver's MMSE detection algorithm into an iterative process of matrix-vector multiplication based on the gradient descent algorithm and deployed the algorithm using a 2T1M (Two Transistors and One Memristor) memristor array.

[0005] However, the matrix operations achievable by current memristor arrays remain limited. The aforementioned research mainly utilizes combinations of operations such as matrix-vector multiplication and inversion performed by memristor arrays to implement various algorithms. Many nonlinear matrix operations, such as QR decomposition, are still difficult to implement using memristors due to their complexity, which greatly limits the application of memristor arrays in algorithms. Summary of the Invention

[0006] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention provides a nonlinear matrix operation method based on memristors, which aims to reduce the complexity and latency of nonlinear matrix operations.

[0007] To achieve the above objectives, according to one aspect of the present invention, a nonlinear matrix operation method based on memristors is provided, comprising: S1. Obtain the operation circuit for the nonlinear matrix operation to be performed based on the nonlinear matrix operation expression between the matrix to be operated on and the target quantity. The operation circuit includes a calculation circuit and a constraint circuit. The calculation circuit is constructed based on the nonlinear matrix operation expression between the matrix to be operated on and the target quantity, and is implemented by a memristor array and its inputs and outputs. The memristor array characterizes the matrix to be operated on through the conductance value of each memristor. The input is the input that makes the output the target quantity, and is controlled by the constraint circuit. The constraint circuit is constructed based on a nonlinear constraint relationship, which is the relationship that the input and output of the calculation circuit should satisfy when the output of the calculation circuit is the target quantity, obtained through nonlinear matrix operations. The input is the input and output of the calculation circuit, and the output provides input to the calculation circuit in a negative feedback manner. S2. Based on the current matrix to be operated on, assign values ​​to the conductance of each memristor array in the operation circuit, and trigger the operation circuit to perform the operation by powering on. After the output result of the operation circuit stabilizes, read the output result, which is the value of the target quantity.

[0008] Furthermore, the operational circuit is constructed in the following manner: When the result of a nonlinear matrix operation has only one target quantity, a theoretical equation containing only matrix multiplication, addition, and / or scalar multiplication is determined based on the nonlinear matrix operation expression between the matrix to be operated on and the target quantity. When the result of a nonlinear matrix operation has multiple target quantities, a target quantity substitution derivation is performed based on the nonlinear matrix operation expression between the matrix to be operated on and multiple target quantities, as well as the relationship between each target quantity or the properties of each target quantity itself, to obtain a theoretical equation containing only matrix multiplication, addition, and / or scalar multiplication between the matrix to be operated on and only one of the target quantities. In the theoretical equation, the target quantity is a matrix with n rows and m columns. A computational circuit is constructed to determine the values ​​of the target quantity in the theoretical equation to realize the theoretical equation. The computational circuit consists of m independent computational sub-circuits with identical structures. Each computational sub-circuit is implemented by a memristor array and its inputs and outputs. Furthermore, the memristor array in each computational sub-circuit represents the matrix to be computed through the conductance value of each memristor. i The input of the first calculation sub-circuit is the target quantity whose output is the first value. i The input vector, consisting of feedback from n constraint sub-circuits, is the target quantity. The constraint circuits are used to ensure that the output of the computational circuit converges to the target quantity; these constraint circuits consist of mutually independent... It consists of several constraint sub-circuits, each of which is used to characterize the corresponding constraint equation. The constraint equations are derived based on theoretical equations and the calculation of the input-output circuit relationships of the sub-circuit. There is a mathematical relationship, which is the only relationship that should be satisfied between the inputs and outputs of different or the same computational sub-circuits in the computational circuit when the output of the computational circuit is the target quantity; the input of each constraint sub-circuit is the actual value of the input and output of the computational sub-circuit involved in the corresponding constraint equation, and the output is a numerical value, which is used as an element of the input vector of the corresponding computational sub-circuit with negative feedback as the target.

[0009] Furthermore, when the result of a nonlinear matrix operation has multiple target quantities, after S2, the method also includes: determining the values ​​of other target quantities based on the current matrix to be operated on and the target quantity values ​​in the theoretical equation, combined with the nonlinear matrix operation expression.

[0010] Furthermore, when the matrix to be operated on is a non-positive real matrix or the nonlinear matrix operation to be performed involves complex number operations, the memristor array in each computational sub-circuit represents the matrix to be operated on by means of the conductance value of each memristor as follows: through a realization operation, the matrix to be operated on is expanded into two realized matrices; one realized matrix is ​​represented by one memristor array, and the conductance value of each memristor in the memristor array represents the value of the element at the corresponding position in the realized matrix; one matrix to be operated on is implemented by two memristor arrays. Furthermore, after reading the output result, the method also includes: converting the output result into a complex number according to the vector representation of the realization operation.

[0011] Furthermore, when the nonlinear matrix operation is a QR decomposition, the expression for the nonlinear matrix operation between the matrix to be operated on and the target variable is: In the formula, Indicates the target quantity. Represent the matrix to be operated on; The computing circuit comprises multiple independent computing sub-circuits with identical structures, and the input-output circuit relationships of each computing sub-circuit are as follows: In the formula, Indicates the input of the computational sub-circuit; This indicates the output of the calculation sub-circuit, the first... i The output of the computational sub-circuit converges to the objective quantity under the constraints of the constraint circuit. i List; and All are in vector form; This represents the matrix to be operated on.

[0012] Furthermore, the constraint circuits consist of mutually independent It consists of several constraint sub-circuits, each of which is used to characterize the corresponding constraint equation. The constraint equations are derived based on the nonlinear matrix operation expressions and the input-output circuit relationships of the computational sub-circuit. A mathematical relationship, The constraint equation includes two types of constraints: ,as well as ; In the formula, For the first The output vector of each computational subcircuit The first in One element; For the first The output vector of each computational subcircuit The first in One element, For the first Input vectors of each computational sub-circuit The first in The conjugate values ​​of each element.

[0013] According to another aspect of the present invention, an application of the nonlinear matrix operation method described above is provided for nonlinear matrix operations in a large-scale multi-antenna system.

[0014] According to another aspect of the present invention, an electronic device is provided, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method described above.

[0015] According to another aspect of the invention, a computer-readable storage medium is provided, the computer-readable storage medium including a stored computer program, wherein, when the computer program is run by a processor, it controls the device where the storage medium is located to perform the steps of the method described above.

[0016] According to another aspect of the invention, a computer program product is provided, comprising a computer program or instructions that, when executed by a processor, implement the steps of the method described above.

[0017] In summary, compared with the prior art, the technical solutions conceived by this invention have the following main advantages: 1. This invention proposes a nonlinear matrix operation method based on memristors. Nonlinear matrix operations, due to their nonlinear nature, exhibit computational complexity that increases dramatically with the size of the matrix. Traditional methods require multiple readings, calculations, and storage of each matrix element, resulting in unrealistic computational complexity. This invention constructs an operational circuit that implements the theoretical equation, incorporating both computational and constraint circuits, based on the nonlinear operation expression. In the computational circuit, matrix multiplication is performed using a memristor array. Based on Ohm's law and Kirchhoff's laws, the memristor array performs matrix-vector multiplication with high parallelism, enabling the computational circuit to achieve high-speed response. In the constraint circuit, analog multipliers, operational amplifiers, and other devices are used to implement the constraint equation in hardware circuitry, replacing the nonlinear calculation process required in traditional schemes. Negative feedback ensures that the output of the computational circuit converges to the target value, eliminating the need for multiple readings, calculations, and storage of matrix elements, significantly reducing computational complexity. This invention effectively reduces the complexity and latency of nonlinear matrix operations. Attached Figure Description

[0018] Figure 1 A flowchart of a nonlinear matrix operation method based on memristors provided in an embodiment of the present invention; Figure 2 This is a diagram of the complex operation structure of a memristor provided in an embodiment of the present invention; Figure 3 This is a diagram of the computational sub-circuit structure corresponding to the QR decomposition provided in an embodiment of the present invention; Figure 4 The constraint sub-circuit structure diagram provided in the embodiments of the present invention; Figure 5 The THP algorithm flowchart provided in this embodiment of the invention; Figure 6 Received signal constellation diagrams using different calculation methods provided for embodiments of the present invention; Figure 7 A comparison chart of bit error rate curves using different calculation methods provided for embodiments of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0020] Example 1 A nonlinear matrix operation method based on memristors, such as Figure 1 As shown, it includes: S1. Obtain the operation circuit for the nonlinear matrix operation to be performed based on the nonlinear matrix operation expression between the matrix to be operated on and the target quantity. The operation circuit includes a calculation circuit and a constraint circuit. The calculation circuit is constructed based on the nonlinear matrix operation expression between the matrix to be operated on and the target quantity, and is implemented by a memristor array and its inputs and outputs. The memristor array characterizes the matrix to be operated on through the conductance value of each memristor. The input is the input that makes the output the target quantity, and is controlled by the constraint circuit. The constraint circuit is constructed based on a nonlinear constraint relationship, which is the relationship that the input and output of the calculation circuit should satisfy when the output of the calculation circuit is the target quantity, obtained through nonlinear matrix operations. The input is the input and output of the calculation circuit, and the output provides input to the calculation circuit in a negative feedback manner. S2. Based on the current matrix to be operated on, assign values ​​to the conductance of each memristor array in the operation circuit, and trigger the operation circuit to perform the operation by powering on. After the output result of the operation circuit stabilizes, read the output result, which is the value of the target quantity.

[0021] This embodiment proposes a design method and application for nonlinear matrix operation circuits based on memristors. Here, "memristor" refers to a non-volatile device whose conductance state can be changed by an externally applied signal, including but not limited to resistive random access memory (RRAM) and phase-change memory (PCM). In specific implementations, it can also be replaced by a combination of multiple resistors and short-circuit switches. "Array" refers to arranging memristor devices in the form of an array of cross nodes. This arrangement is similar to the representation of a mathematical matrix, which helps memristors perform matrix operations. "Nonlinear matrix operation" refers to operations on matrices that do not satisfy additivity or homogeneity. "Acceleration" refers to the fact that, compared to traditional digital processors, this invention effectively reduces the computational complexity of nonlinear matrix operations by utilizing highly parallel memristor arrays. The design method proposed in this embodiment is a circuit design principle and framework for nonlinear matrix operations in in-memory computing architectures implemented using memristors. It has broad applicability and provides a systematic framework and guidance for the design of various nonlinear matrix operation circuits based on memristors.

[0022] The method proposed in this embodiment divides the circuit into two parts, and the circuit structure includes two parts: a calculation circuit and a constraint circuit. The computing circuit is used to store known matrices, receive input signals, and output target signals. The computing circuit is mainly implemented using a memristor array, which leverages the high parallelism of the memristor array to achieve high-speed computation and fast output.

[0023] Constraint circuits are used to establish nonlinear constraint relationships between the input and output signals of a computational circuit, ensuring that the output signal converges to the target value. Constraint circuits are mainly implemented using operational amplifiers, multipliers, and other devices. These devices create constraints on the input, output, or intermediate computational quantities, ensuring that the signals satisfy, and uniquely satisfy, the nonlinear relationships defined by the nonlinear operation, thus achieving accurate output convergence.

[0024] Note that the main circuit devices mentioned in this embodiment for constructing the computational and constraint circuits are memristors, operational amplifiers, multipliers, etc. However, when designing for actual computation, the devices are not limited to these types. The choice of devices depends on the design scheme of the computational and constraint circuits required for the target computation.

[0025] As a preferred embodiment, the above-mentioned operational circuit is constructed in the following manner: When the result of a nonlinear matrix operation has only one target quantity, a theoretical equation containing only matrix multiplication, addition, and / or scalar multiplication is determined based on the nonlinear matrix operation expression between the matrix to be operated on and the target quantity. When the result of a nonlinear matrix operation has multiple target quantities, a target quantity substitution derivation is performed based on the nonlinear matrix operation expression between the matrix to be operated on and multiple target quantities, as well as the relationship between each target quantity or the properties of each target quantity itself, to obtain a theoretical equation containing only matrix multiplication, addition, and / or scalar multiplication between the matrix to be operated on and only one of the target quantities. In the theoretical equation, the target quantity is a matrix with n rows and m columns. A computational circuit is constructed to determine the values ​​of the target quantity in the theoretical equation to realize the theoretical equation. The computational circuit consists of m independent computational sub-circuits with identical structures. Each computational sub-circuit is implemented by a memristor array and its inputs and outputs. Furthermore, the memristor array in each computational sub-circuit represents the matrix to be computed through the conductance value of each memristor. i The input of the first calculation sub-circuit is the target quantity whose output is the first value. i The input vector, consisting of feedback from n constraint sub-circuits, is the target quantity. The constraint circuits are used to ensure that the output of the computational circuit converges to the target quantity; these constraint circuits consist of mutually independent... It consists of several constraint sub-circuits, each of which is used to characterize the corresponding constraint equation. The constraint equations are derived based on theoretical equations and the calculation of the input-output circuit relationships of the sub-circuit. There is a mathematical relationship, which is the only relationship that should be satisfied between the inputs and outputs of different or the same computational sub-circuits in the computational circuit when the output of the computational circuit is the target quantity; the input of each constraint sub-circuit is the actual value of the input and output of the computational sub-circuit involved in the corresponding constraint equation, and the output is a numerical value, which is used as an element of the input vector of the corresponding computational sub-circuit with negative feedback as the target.

[0026] As a preferred implementation, when the result of the nonlinear matrix operation has multiple target quantities, after S2, the method further includes: determining the values ​​of other target quantities based on the current matrix to be operated on and the target quantity values ​​in the theoretical equation, combined with the nonlinear matrix operation expression.

[0027] As a preferred implementation, when the matrix to be operated on is a non-positive real matrix or the nonlinear matrix operation to be performed involves complex number operations, the memristor array in each computational sub-circuit represents the matrix to be operated on by means of the conductance value of each memristor as follows: through a realization operation, the matrix to be operated on is expanded into two realized matrices; one realized matrix is ​​represented by one memristor array, and the conductance value of each memristor in the memristor array represents the value of the element at the corresponding position in the realized matrix; one matrix to be operated on is implemented by two memristor arrays. Furthermore, after reading the output result, the method also includes: converting the output result into a complex number according to the vector representation of the realization operation.

[0028] Note that memristors represent values ​​using conductance, and cannot represent values ​​other than positive real numbers. In the preferred embodiment, complex matrices and vectors are transformed into positive real matrix and vector, and complex domain operations are transformed into positive real domain operations. The specific implementation method is as follows: For a single memristor array, if the matrix to be operated on stored is a complex matrix... The input target voltage vector is a complex vector. The actual operation will and They are expanded into the following forms respectively:

[0029]

[0030] in and They represent:

[0031]

[0032] Figure 2 This is a memristor circuit structure based on the complex matrix-vector multiplication operation under the realization extension of the above formula, where the complex matrix... The subtraction operation in the realization extension is implemented using an inverter.

[0033] To verify and demonstrate the effectiveness of the general design method proposed in this embodiment, a QR decomposition acceleration method based on memristors is further proposed. Here, "QR decomposition" refers to the mathematical operation of decomposing a matrix into the product of a second-unitary matrix and an upper triangular matrix. Due to symmetry, this invention can also be used to accelerate LQ decomposition, that is, decomposing a matrix into the product of a lower triangular matrix and a second-unitary matrix. Both methods share a consistent circuit architecture, which will be further explained later. The application proposed in this embodiment is applicable to any algorithm that requires QR decomposition, reducing the complexity of the high-dimensional QR decomposition operations required by the algorithm from a hardware perspective, thereby accelerating the algorithm.

[0034] As a preferred implementation, when the nonlinear matrix operation is a QR decomposition, the expression for the nonlinear matrix operation between the matrix to be operated on and the target quantity is: In the formula, Indicates the target quantity. Represent the matrix to be operated on; The computing circuit comprises multiple independent computing sub-circuits with identical structures, and the input-output circuit relationships of each computing sub-circuit are as follows: In the formula, Indicates the input of the computational sub-circuit; This indicates the output of the calculation sub-circuit, the first... i The output of the computational sub-circuit converges to the objective quantity under the constraints of the constraint circuit. i List; and All are in vector form; This represents the matrix to be operated on.

[0035] As a preferred embodiment, the constraint circuit consists of mutually independent components. It consists of several constraint sub-circuits, each of which is used to characterize the corresponding constraint equation. The constraint equations are derived based on the nonlinear matrix operation expressions and the input-output circuit relationships of the computational sub-circuit. A mathematical relationship, The constraint equation includes two types of constraints: ,as well as ; In the formula, For the first The output vector of each computational subcircuit The first in One element; For the first The output vector of each computational subcircuit The first in One element, For the first Input vectors of each computational sub-circuit The first in The conjugate values ​​of each element.

[0036] This section elaborates on the nonlinear matrix operation method based on memristors proposed in this embodiment, and further elaborates on the QR decomposition acceleration method based on memristors, as an application example of the general method proposed in this embodiment.

[0037] For matrices ( Its QR decomposition can be expressed in the following form: Among them, matrix It is a second-unitary matrix that satisfies , It is an upper triangular matrix. QR decomposition involves nonlinear matrix operations, and there is currently no implementation scheme based on memristors.

[0038] Based on the nonlinear matrix operation circuit design method proposed in this embodiment, this embodiment divides a QR decomposition acceleration circuit structure based on memristor array into two parts: a calculation sub-circuit and a constraint sub-circuit.

[0039] Calculation sub-circuit such as Figure 3 As shown, the input voltage vector is The output voltage vector is Both memristor arrays store the matrices to be operated on in the form of conductance. This circuit can perform the following operations: .

[0040] In the QR decomposition circuit architecture, integrated The aforementioned computational sub-circuits, by adding constraints, make the first... Voltage vector in each computational subcircuit equal No. A column vector consisting of columns. The constraints involve two steps: (1) Due to the voltage vector equal No. A column vector composed of columns, indicating Some elements are 0, which is achieved by grounding the voltage port corresponding to the element in the circuit. The specific grounding port is shown in the following formula: ,in column vector The Middle Each element.

[0041] (2) Construct the input voltage vector using an analog multiplier and operational amplifier. With output voltage vector Nonlinear constraint relationships between them: The corresponding constraint sub-circuit is as follows: Figure 4 As shown.

[0042] matrix By using voltage vector Input to matrix It is obtained in the matrix-vector multiplication circuit.

[0043] When using the circuit structure of this embodiment to accelerate the LQ decomposition circuit, it is only necessary to... Figure 3 The matrix stored in each memristor array in the computational sub-circuit is changed to the matrix transpose. At this point, the output vector of the sub-circuit can be calculated. equal No. The column vector formed by the columns, and the corresponding matrix By using voltage vector Transpose of input to storage matrix It is obtained in the matrix-vector multiplication circuit.

[0044] Example 2 An application of the nonlinear matrix operation method as described in Embodiment 1 is used for nonlinear matrix operations in a large-scale multi-antenna system.

[0045] Considering the need for the THP (Tomlinson-Harashima Precoding) algorithm of QR decomposition in communication systems as a circuit application scenario, the feasibility of the circuit structure based on the design method proposed in this invention is verified.

[0046] The THP algorithm is a precoding algorithm in communication systems that can effectively reduce multi-user interference. The three filters required in the THP algorithm are obtained by performing LQ decomposition (the dual form of QR decomposition) on the channel matrix. Its overall process is as follows: Figure 5 As shown.

[0047] For the channel matrix ( Its LQ decomposition is as follows: ,in, It is a lower triangular matrix. The matrix satisfies .

[0048] The three filters used in the algorithm are calculated using the following formula:

[0049]

[0050]

[0051] in, express Matrix number Line 1 Column elements, Indicates using Form a diagonal matrix with diagonal elements as .

[0052] This represents a column vector consisting of the original modulated signals transmitted to all users. In the THP algorithm, a feedforward filter and a modulator are used to generate an information column vector that eliminates inter-user interference and limits amplitude. :

[0053] in, yes The first in the matrix Line 1 Column elements, This represents the modulo operation, and the expression is: ,in, The specific value depends on the modulation category.

[0054] Subsequently, the information column vector was analyzed. Perform channel pre-equalization and generate pre-equalization vectors. , .

[0055] The above describes the computational operations required by the base station when executing the THP algorithm. Due to the use of LQ decomposition, the overall computational complexity is high, making deployment difficult. This invention replaces the traditional digital processor with a QR decomposition circuit for LQ decomposition, reducing its computational complexity to [a lower level]. .

[0056] The LQ decomposition circuit of this invention was deployed using circuit simulation software and THP operation was performed. The feasibility of the circuit of this invention was verified by constellation diagram and bit error rate curve.

[0057] With an SNR of 20dB, the constellation diagram of the received signal after constructing the circuit of this invention using a 5-bit precision memristor array is as follows: Figure 6 As shown, Figure 6 The left image shows the result obtained using a traditional processor. Figure 6 The right figure shows the result obtained using the method of this invention. By comparison, the received signal after precoding using the memristor array of this invention shows little difference from that of a traditional digital processor, demonstrating the feasibility of this invention in accelerating QR decomposition (LQ decomposition). The offset of the received signal in the figure mainly originates from thermal noise and the finite bit precision of the memristor. Improving the bit precision can further enhance the calculation accuracy of the circuit of this invention.

[0058] Figure 7 The bit error rate (BER) curves are shown for LQ decomposition operations performed using a conventional digital processor and for operations performed using the circuit of this invention deployed with multi-bit precision memristors. It is noted that when the SNR is below 30 dB, the differences in results obtained by the digital processor and the circuit of this invention are minimal; only when the SNR is sufficiently high do significant differences arise, and these differences can be further reduced by increasing the precision of the memristor array. These BER curves quantitatively demonstrate the feasibility of the QR decomposition circuit of this invention using the THP algorithm as an application scenario.

[0059] The relevant technical solutions are the same as above, and will not be repeated here.

[0060] Example 3 This application also relates to an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described above.

[0061] The electronic device can be a desktop computer, laptop, handheld computer, or cloud server, etc. The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The memory can be used to store computer programs and / or modules. The processor performs various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory, and by accessing data stored in the memory.

[0062] The relevant technical solutions are the same as above, and will not be repeated here.

[0063] Example 4 This application also relates to a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0064] Specifically, the memory may include high-speed random access memory, as well as non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart media cards (SMC), secure digital (SD) cards, flash cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.

[0065] The relevant technical solutions are the same as above, and will not be repeated here.

[0066] Example 5 This application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the steps of the method described in the above embodiments of this application.

[0067] The relevant technical solutions are the same as above, and will not be repeated here.

[0068] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A nonlinear matrix operation method based on memristors, characterized in that, include: S1. Obtain the operation circuit for the nonlinear matrix operation to be performed based on the nonlinear matrix operation expression between the matrix to be operated on and the target quantity. The operation circuit includes a calculation circuit and a constraint circuit. The calculation circuit is constructed based on the nonlinear matrix operation expression between the matrix to be operated on and the target quantity, and is implemented by a memristor array and its inputs and outputs. The memristor array characterizes the matrix to be operated on through the conductance value of each memristor. The input is the input that makes the output the target quantity, and is controlled by the constraint circuit. The constraint circuit is constructed based on a nonlinear constraint relationship, which is the relationship that the input and output of the calculation circuit should satisfy when the output of the calculation circuit is the target quantity, obtained through nonlinear matrix operations. The input is the input and output of the calculation circuit, and the output provides input to the calculation circuit in a negative feedback manner. S2. Based on the current matrix to be operated on, assign values ​​to the conductance of each memristor array in the operation circuit, and trigger the operation circuit to perform the operation by powering on. After the output result of the operation circuit stabilizes, read the output result, which is the value of the target quantity. The operational circuit is constructed in the following manner: When the result of a nonlinear matrix operation has only one target quantity, a theoretical equation containing only matrix multiplication, addition, and / or scalar multiplication is determined based on the nonlinear matrix operation expression between the matrix to be operated on and the target quantity. When the result of a nonlinear matrix operation has multiple target quantities, a target quantity substitution derivation is performed based on the nonlinear matrix operation expression between the matrix to be operated on and multiple target quantities, as well as the relationship between each target quantity or the properties of each target quantity itself, to obtain a theoretical equation containing only matrix multiplication, addition, and / or scalar multiplication between the matrix to be operated on and only one of the target quantities. In the theoretical equation, the target quantity is a matrix with n rows and m columns. A computational circuit is constructed to determine the values ​​of the target quantity in the theoretical equation to realize the theoretical equation. The computational circuit consists of m independent computational sub-circuits with identical structures. Each computational sub-circuit is implemented by a memristor array and its inputs and outputs. Furthermore, the memristor array in each computational sub-circuit represents the matrix to be computed through the conductance value of each memristor. i The input of the first calculation sub-circuit is the target quantity whose output is the first value. i The input vector, consisting of feedback from n constraint sub-circuits, is the target quantity. The constraint circuits are used to ensure that the output of the computational circuit converges to the target quantity; these constraint circuits consist of mutually independent... It consists of several constraint sub-circuits, each of which is used to characterize the corresponding constraint equation. The constraint equations are derived based on theoretical equations and the calculation of the input-output circuit relationships of the sub-circuit. There is a mathematical relationship, which is the only relationship that should be satisfied between the inputs and outputs of different or the same computational sub-circuits in the computational circuit when the output of the computational circuit is the target quantity; the input of each constraint sub-circuit is the actual value of the input and output of the computational sub-circuit involved in the corresponding constraint equation, and the output is a numerical value, which is used as an element of the input vector of the corresponding computational sub-circuit with negative feedback as the target.

2. The nonlinear matrix operation method as described in claim 1, characterized in that, When the result of a nonlinear matrix operation has multiple target quantities, after S2, the method further includes: determining the values ​​of other target quantities based on the current matrix to be operated on and the target quantity values ​​in the theoretical equation, combined with the nonlinear matrix operation expression.

3. The nonlinear matrix operation method as described in claim 1, characterized in that, When the matrix to be operated on is a non-positive real matrix or the nonlinear matrix operation to be performed involves complex number operations, the implementation of the memristor array in each calculation sub-circuit representing the matrix to be operated on through the conductance value of each memristor is as follows: through the realization operation, the matrix to be operated on is expanded into two real matrices; one real matrix is ​​represented by a memristor array, and the conductance value of each memristor in the memristor array represents the value of the element at the corresponding position of the real matrix; A matrix to be operated on is implemented by two memristor arrays; Furthermore, after reading the output result, the method also includes: converting the output result into a complex number according to the vector representation of the realization operation.

4. The nonlinear matrix operation method as described in claim 1, characterized in that, When the nonlinear matrix operation is a QR decomposition, the expression for the nonlinear matrix operation between the matrix to be operated on and the target variable is: In the formula, Indicates the target quantity. Represent the matrix to be operated on; The computing circuit comprises multiple independent computing sub-circuits with identical structures, and the input-output circuit relationships of each computing sub-circuit are as follows: In the formula, Indicates the input of the computational sub-circuit; This indicates the output of the calculation sub-circuit, the first... i The output of the computational sub-circuit converges to the objective quantity under the constraints of the constraint circuit. i List; and All are in vector form; This represents the matrix to be operated on.

5. The nonlinear matrix operation method as described in claim 4, characterized in that, The constraint circuits consist of independent It consists of several constraint sub-circuits, each of which is used to characterize the corresponding constraint equation. The constraint equations are derived based on the aforementioned nonlinear matrix operation expressions and the input-output circuit relationships of the computational sub-circuit. A mathematical relationship, The constraint equation includes two types of constraints: ,as well as ; In the formula, For the first The output vector of each computational subcircuit The first in One element; For the first The output vector of each computational subcircuit The first in One element, For the first Input vectors of each computational sub-circuit The first in The conjugate values ​​of each element.

6. A massive MIMO system, characterized in that, The nonlinear matrix operations in this system are used to implement the nonlinear matrix operation method as described in any one of claims 1 to 5.

7. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program, wherein the computer program, when executed by a processor, controls the device on which the storage medium is located to perform the steps of the method as described in any one of claims 1 to 5.

9. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by a processor, they implement the steps of the method as described in any one of claims 1 to 5.

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