High view angle non-reset pixel driving circuit

Abstract

The application discloses a high-visual-angle reset-free pixel driving circuit, which comprises a first sub-pixel and a second sub-pixel, and the first sub-pixel and the second sub-pixel each comprise a transfer transistor, a pixel capacitor and a holding capacitor, and the transfer transistor is coupled to the pixel capacitor and the holding capacitor, wherein when the first sub-pixel and the second sub-pixel share a pre-storage capacitor, the transfer transistor of the first sub-pixel and the transfer transistor of the second sub-pixel are each coupled to a first pre-storage capacitor, and the first pre-storage capacitor is coupled to a first write transistor; when the first sub-pixel and the second sub-pixel do not share a pre-storage capacitor, the transfer transistor of the first sub-pixel is coupled to a first pre-storage capacitor, the transfer transistor of the second sub-pixel is coupled to a second pre-storage capacitor, and the second pre-storage capacitor is coupled to a second write transistor.

Description

Technical Field

[0001] This invention relates to the field of pixel driving technology, and more specifically to a high-viewing-angle, resetless pixel driving circuit. Background Technology

[0002] Traditional LCD (Liquid Crystal Display) flat panel displays are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide application range, becoming the mainstream display device. Most LCD displays on the market are backlit LCDs, which include the liquid crystal display panel (TFT-LCD) and the backlight module. Currently, IPS (FFS) and VA-type LCD panels are the mainstream LCD panels on the market. VA displays have extremely high contrast compared to other types of LCD panels, making them widely used in large-size displays such as televisions.

[0003] Compared to traditional LCD designs, VA (Vertical Variable Image) displays, lacking RGB color resistivity, offer significantly improved transmittance, resulting in advantages in both brightness and power consumption. Therefore, VA-mode VA displays offer better value for money in terms of contrast, brightness, and power consumption compared to other display modes.

[0004] However, because VA-type LCD panels use vertically rotating liquid crystals, the difference in birefringence of the liquid crystal molecules is relatively large, resulting in a serious color shift problem at wide viewing angles. This causes a large difference in brightness when viewed from different angles, resulting in image distortion.

[0005] like Figure 2 Due to inherent limitations of LCD displays, the image viewed from different positions on a VA monitor will always show some differences. This causes images that appear normal when viewed directly to display abnormalities when viewed from a wide viewing angle, primarily manifested as gamma deviation at side viewing angles. Similarly, in monochrome displays, gamma differences at wide viewing angles also result in large-viewing-angle gamma deviations. To improve the viewing angle issue of VA monitors, generally... Figure 2 The design shown divides the entire display unit into a main pixel and a sub-pixel, creating a voltage difference between them. This allows the liquid crystal molecules to have two different alignment directions at the same grayscale level, which can compensate for viewing angles at wide viewing angles, thus improving viewing experience.

[0006] However, how to design pixels in field sequence displays remains a problem. Summary of the Invention

[0007] In view of this, the present invention provides a high viewing angle non-reset pixel driving circuit, which solves the problem of low viewing angle of VA field sequence pixel driving circuit by improving the circuit structure and driving timing.

[0008] To address the above problems, the technical solution of this invention is to employ a high viewing angle, resetless pixel driving circuit, including a first sub-pixel and a second sub-pixel. Both the first and second sub-pixels include a transfer transistor, a pixel capacitor, and a holding capacitor. The transfer transistor is coupled to the pixel capacitor and the holding capacitor. When the first and second sub-pixels share a pre-storage capacitor, both the transfer transistors of the first and second sub-pixels are coupled to the first pre-storage capacitor, which is then coupled to a first write transistor. When the first and second sub-pixels do not share a pre-storage capacitor, the transfer transistors of the first sub-pixel are coupled to the first pre-storage capacitor, and the transfer transistors of the second sub-pixel are coupled to a second pre-storage capacitor, which is then coupled to a second write transistor.

[0009] Optionally, when the first sub-pixel and the second sub-pixel share a pre-storage capacitor, the first source and drain of the transfer transistor of the first sub-pixel are coupled to the first pre-storage capacitor, the second source and drain are coupled to the pixel capacitor and holding capacitor of the first sub-pixel, and the gate is coupled to the first transfer signal line; the first source and drain of the transfer transistor of the second sub-pixel are coupled to the first pre-storage capacitor, the second source and drain are coupled to the pixel capacitor and holding capacitor of the second sub-pixel, and the gate is coupled to the second transfer signal line.

[0010] Optionally, the first pre-storage capacitor is coupled to the second source and drain of the first write transistor, and the first source and drain of the first write transistor are coupled to the data signal line and the gate is coupled to the control signal line.

[0011] Optionally, the end of the first pre-stored capacitor furthest from the transistor is coupled to the first coupled signal line.

[0012] Optionally, when the first sub-pixel and the second sub-pixel do not share a pre-storage capacitor, the first source-drain of the transfer transistor of the first sub-pixel is coupled to the first pre-storage capacitor, the second source-drain is coupled to the pixel capacitor and the holding capacitor of the first sub-pixel, and the gate is coupled to the first transfer signal line; the first source-drain of the transfer transistor of the second sub-pixel is coupled to the second source-drain of the second write transistor and the second pre-storage capacitor, the second source-drain is coupled to the pixel capacitor and the holding capacitor of the second sub-pixel, and the gate is coupled to the first transfer signal line.

[0013] Optionally, the first source and drain of the second write transistor are also coupled to the first pre-storage capacitor, and the second source and drain of the first write transistor are coupled to the control signal line.

[0014] Optionally, the ends of the first pre-storage capacitor and the second pre-storage capacitor furthest from the transistor are coupled to the first coupling signal line.

[0015] Optionally, the end of the second pre-stored capacitor furthest from the transistor can also be coupled to a second coupled signal line. The primary improvement of this invention is the provision of a high viewing angle non-reset pixel driving circuit. By constructing the circuit structures of the first and second sub-pixels differently, and utilizing the pre-storage capacitor and its pre-charging characteristics unique to the field-sequence pixel circuit, the first and second sub-pixels are charged differently in time and space, thus solving the problem of low viewing angle in the VA field-sequence pixel driving circuit. Attached Figure Description

[0016] Figure 1 This is a simplified circuit diagram of the pixel driving circuit of Embodiment 1 of the present invention; Figure 2 This is a simplified driving timing diagram of the pixel driving circuit of Embodiment 1 of the present invention; Figure 3 This is a simplified circuit diagram of the pixel driving circuit of Embodiment 2 of the present invention; Figure 4 This is a simplified driving timing diagram of the pixel driving circuit of Embodiment 2 of the present invention; Figure 5 This is a simplified circuit diagram of the pixel driving circuit of Embodiment 3 of the present invention; Figure 6 This is a simplified driving timing diagram of the pixel driving circuit of Embodiment 3 of the present invention. Detailed Implementation

[0017] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0022] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0024] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. Example

[0025] Specifically, such as Figure 1 As shown, a high viewing angle non-reset pixel driving circuit includes a first sub-pixel and a second sub-pixel. The first sub-pixel and the second sub-pixel each include a transfer transistor, a pixel capacitor, and a holding capacitor, wherein the transfer transistor is coupled to the pixel capacitor and the holding capacitor.

[0026] Furthermore, the first source and drain of the transfer transistor T2 of the first sub-pixel mPixel are coupled to the first pre-storage capacitor Cs1, the second source and drain are coupled to the pixel capacitor mClc and the holding capacitor mCs of the first sub-pixel mPixel, and the gate is coupled to the first transfer signal line Tran; the first source and drain of the transfer transistor T4 of the second sub-pixel sPixel are coupled to the first pre-storage capacitor Cs1, the second source and drain are coupled to the pixel capacitor sClc and the holding capacitor sCs of the second sub-pixel sPixel, and the gate is coupled to the second transfer signal line Tran2.

[0027] Furthermore, the first pre-storage capacitor Cs1 is coupled to the second source and drain of the first write transistor T1, and the first source and drain of the first write transistor T1 is coupled to the data signal line Data, and the gate is coupled to the control signal line Scan.

[0028] Furthermore, the end of the first pre-storage capacitor Cs1 furthest from the transistor is coupled to the first coupled signal line Couple.

[0029] To facilitate understanding of the working principle of the drive circuit protected in this embodiment, as follows: Figure 2 As shown, the applicable timing sequence is as follows: Starting in frame N-1, the scan sequentially opens and writes the Pre_charge pre-stored voltage, with the pre-stored capacitor being Cs1. During the transfer phase, the Couple voltage change causes a jump in the Pre_charge pre-stored voltage. Subsequently, Tran goes high (T2) to share the mPixel, then Tran1 goes low (T2) to close, and then Tran2 goes high (T3) to share the sPixel. After this, the display begins in frame N+1. This process is repeated to complete the field sequence display.

[0030] Furthermore, to facilitate understanding of the voltage difference formation mechanism between the first sub-pixel mPixel and the second sub-pixel sPixel, a quantitative analysis is now performed. We set Cs1 = 1 / m1*mCs = 1 / p1*mClc and Cs1 = 1 / m2*sCs = 1 / p2*sClc. From the principle of field-order charge sharing, we can obtain: The voltage of mPixel is mVn = Vn: [(Vdn-1+2Vo)-mVn]*Cs1=(mVn-mVn-1)*(mCs+mClc), Vdn-1= mVn*(1+m1+p1)-2Vo-mVn-1*(m1+p1) mVn=[Vdn-1+2Vo+mVn-1*(m1+p1)] / (1+m1+p1) The voltage of sPixel is sVn=Vn [(mVn)-sVn]*Cs1=(sVn-sVn-1)*(sCs+sClc), mVn= sVn*(1+m2+p2)-sVn-1*(m2+p2) sVn=[mVn+sVn-1*(m2+p2)] / (1+m2+p2) sVn=[[Vdn-1+2Vo+mVn-1*(m1+p1)] / (1+m1+p1)+sVn-1*(m2+p2)] / (1+m2+p2) =[Vdn-1+2Vo+mVn-1(m1+p1)+sVn-1(m2+p2)*(1+m1+p1)] / [(1+m1+p1)*(1+m2+p2)] To simplify the above formula, let α = m1 + p1; β = m2 + p2 Then the voltage mVn of mPixel: mVn=[Vdn-1+2Vo+mVn-1*(m1+p1)] / (1+m1+p1) =[Vdn-1+2Vo+mVn-1*α] / (1+α) sVn=[Vdn-1+2Vo+mVn-1(m1+p1)+sVn-1(m2+p2)*(1+m1+p1)] / [(1+m1+p1)*(1+m2+p2)] =[Vdn-1+2Vo+mVn-1*α+sVn-1*β*(1+α)] / [(1+α)*(1+β)] The above analysis shows that the voltage difference between mPixel and sPixel enables the display of main_pixel and sub_pixel, thereby improving the viewing angle.

[0031] It should be noted that this embodiment is not limited to settings such as Cs1=1 / m*mCs=1 / p*mClc and Cs1=1 / m*sCs=1 / p*sClc. The areas of main_pixel and sub_pixel can be different.

[0032] This embodiment constructs the circuit structure of the first sub-pixel and the second sub-pixel differently. By utilizing the pre-storage capacitor and its pre-charging characteristics unique to the field-sequence pixel circuit, and controlling the differentiated on / off times of T2 and T4, it achieves differentiated charging of the first sub-pixel and the second sub-pixel, thus solving the problem of low viewing angle in the VA field-sequence pixel driving circuit. Example

[0033] Specifically, such as Figure 3 As shown, this embodiment provides a pixel driving circuit with a high viewing angle, including a first sub-pixel mPixel and a second sub-pixel sPixel. Both the first sub-pixel mPixel and the second sub-pixel sPixel include a transfer transistor, a pixel capacitor, and a holding capacitor. The transfer transistor is coupled to the pixel capacitor and the holding capacitor.

[0034] Furthermore, the first source and drain of the transfer transistor T2 of the first sub-pixel are coupled to the first pre-storage capacitor Cs1, the second source and drain are coupled to the pixel capacitor mClc and the holding capacitor mCs of the first sub-pixel, and the gate is coupled to the first transfer signal line Tran; the first source and drain of the transfer transistor T4 of the second sub-pixel are coupled to the second source and drain of the second write transistor T3 and the second pre-storage capacitor Cs2, the second source and drain are coupled to the pixel capacitor sClc and the holding capacitor sCs of the second sub-pixel, and the gate is coupled to the first transfer signal line Tran.

[0035] Furthermore, the first source and drain of the second write transistor T3 are also coupled to the first pre-storage capacitor Cs1 and the second source and drain of the first write transistor T1, and the gate is coupled to the control signal line Scan.

[0036] Furthermore, the ends of the first pre-storage capacitor Cs1 and the second pre-storage capacitor Cs2 furthest from the transistor are coupled to the first coupling signal line Couple.

[0037] To facilitate understanding of the working principle of the drive circuit protected in this embodiment, as follows: Figure 4 As shown, the applicable timing sequence is as follows: Starting from frame N-1, the scan sequentially opens and writes the Pre_charge pre-stored voltage line by line. The circuit diagram shows that during writing, both pre-stored capacitors Cs1 and Cs2 are written with the same voltage. During the transfer phase, the Couple voltage jump causes the Pre_charge pre-stored voltage to jump. Subsequently, Tran high potential T2 and T4 are simultaneously turned on for sharing, and after completion, Tran low potential T2 and T4 are turned off. Then, the display begins in frame N. The above actions are repeated to complete the field sequence display.

[0038] Furthermore, to facilitate understanding of the voltage difference formation mechanism between the first sub-pixel mPixel and the second sub-pixel sPixel, a quantitative analysis is conducted. We set Cs1 = 1 / m1*mCs = 1 / p1*mClc, Cs2 = 1 / m2*sCs = 1 / p2*sClc, and the Couple voltage is 2Vo. Based on the principle of field-order charge sharing, we can obtain: The voltage mVn of mPixel: [(Vdn-1+2Vo)-mVn]*Cs1=(mVn-mVn-1)*(mCs+mClc), Vdn-1= mVn*(1+m1+p1)-2Vo-mVn-1*(m1+p1) mVn=[Vdn-1+2Vo+mVn-1*(m1+p1)] / (1+m1+p1) sPixel voltage sVn: [(Vdn-1+2Vo)-sVn]*Cs1=(sVn-sVn-1)*(sCs+sClc), Vdn-1= sVn*(1+m2+p2)-2Vo-mVn-1*(m2+p2) mVn=[Vdn-1+2Vo+sVn-1*(m2+p2)] / (1+m2+p2) The above analysis shows that the expression differs from that in Example 1. Similarly, the voltages of mPixel and sPixel are differentiated, thereby enabling the display of main_pixel and sub_pixel and improving the viewing angle.

[0039] This embodiment constructs the circuit structures of the first and second sub-pixels differently, utilizes the pre-storage capacitor and its pre-charging characteristics unique to the field-sequence pixel circuit, and achieves time-division difference of the pre-storage capacitor by using the Couple voltage jump, thereby realizing differentiated charging of the first and second sub-pixels, solving the problem of low viewing angle in the VA field-sequence pixel driving circuit. Example

[0040] Specifically, such as Figure 5 As shown, the improvement of this example compared to embodiment 3 is that the end of the second pre-storage capacitor Cs2 away from the transistor can also be coupled to the second coupling signal line Couple2.

[0041] To facilitate understanding of the working principle of the drive circuit protected in this embodiment, as follows: Figure 6As shown, the applicable working timing is illustrated below: Starting from frame N-1, the scan sequentially opens and writes the Pre_charge pre-stored voltage line by line. The circuit diagram shows that during writing, both pre-stored capacitors Cs1 and Cs2 are written with the same voltage. During the transfer phase, the Couple voltage jump causes the Pre_charge pre-stored voltage to jump. The difference in this embodiment is that the values ​​of Couple and Couple2 can be freely adjusted, increasing the degree of freedom in adjusting the difference between primary and secondary pixels. Subsequently, Tran high potentials T2 and T4 are simultaneously activated for sharing, and after completion, Tran low potentials T2 and T4 are deactivated. Then, the display begins in frame N. The above actions are repeated to complete the field sequence display.

[0042] Furthermore, to facilitate understanding of the voltage difference formation mechanism between the first sub-pixel mPixel and the second sub-pixel sPixel, a quantitative analysis is conducted. We set Cs1 = 1 / m1*mCs = 1 / p1*mClc, Cs2 = 1 / m2*sCs = 1 / p2*sClc, the voltage of Couple is 2sVo, and the voltage of Couple2 is 2mVo. From the principle of field order charge sharing, we can obtain The voltage mVn of mPixel: [(Vdn-1+2mVo)-mVn]*Cs1=(mVn-mVn-1)*(mCs+mClc), Vdn-1= mVn*(1+m1+p1)-2mVo-mVn-1*(m1+p1) mVn=[Vdn-1+2mVo+mVn-1*(m1+p1)] / (1+m1+p1) sPixel voltage sVn: [(Vdn-1+2sVo)-sVn]*Cs1=(sVn-sVn-1)*(sCs+sClc), Vdn-1= sVn*(1+m2+p2)-2sVo-sVn-1*(m2+p2) sVn=[Vdn-1+2sVo+sVn-1*(m2+p2)] / (1+m2+p2) The above analysis shows that the expression is different from that in Example 2. Similarly, the voltages of mPixel and sPixel are differentiated to achieve the display of main_pixel and sub_pixel, improving the viewing angle. In addition, a free adjustment factor for Couple is added in addition to the capacitor design ratio factor. The above describes a high viewing angle, resetless pixel driving circuit provided by embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0043] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can implement the described functions using different methods for each specific application, but such implementation should not be considered beyond the scope of the invention. The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be implemented directly in hardware, software modules executed by a processor, or a combination of both. Software modules can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

Claims

1. A high viewing angle, resetless pixel driving circuit, comprising a first sub-pixel and a second sub-pixel, characterized in that, Both the first sub-pixel and the second sub-pixel include a transfer transistor, a pixel capacitor, and a holding capacitor, wherein the transfer transistor is coupled to the pixel capacitor and the holding capacitor. When the first sub-pixel and the second sub-pixel share the pre-storage capacitor, the transfer transistor (T2) of the first sub-pixel and the transfer transistor (T4) of the second sub-pixel are both coupled to the first pre-storage capacitor (Cs1), and the first pre-storage capacitor (Cs1) is coupled to the first write transistor (T1). When the first sub-pixel and the second sub-pixel share the pre-storage capacitor The first source and drain of the transfer transistor (T2) of the first sub-pixel are coupled to the first pre-storage capacitor (Cs1), the second source and drain are coupled to the pixel capacitor (mClc) and the holding capacitor (mCs) of the first sub-pixel, and the gate is coupled to the first transfer signal line (Tran). The first source and drain of the transfer transistor (T4) of the second sub-pixel are coupled to the first pre-storage capacitor (Cs1), the second source and drain are coupled to the pixel capacitor (sClc) and the holding capacitor (sCs) of the second sub-pixel, and the gate is coupled to the second transfer signal line (Tran2). When the first sub-pixel and the second sub-pixel do not share a pre-storage capacitor, the transfer transistor (T2) of the first sub-pixel is coupled to the first pre-storage capacitor (Cs1), the transfer transistors (T4) of the second sub-pixel are both coupled to the second pre-storage capacitor (Cs2), and the second pre-storage capacitor (Cs2) is coupled to the second write transistor (T3). When the first sub-pixel and the second sub-pixel do not share the pre-stored capacitor The first source and drain of the transfer transistor (T2) of the first sub-pixel are coupled to the first pre-storage capacitor (Cs1), the second source and drain are coupled to the pixel capacitor (mClc) and the holding capacitor (mCs) of the first sub-pixel, and the gate is coupled to the first transfer signal line (Tran). The first source and drain of the transfer transistor (T4) of the second sub-pixel are coupled to the second source and drain of the second write transistor (T3) and the second pre-storage capacitor (Cs2). The second source and drain are coupled to the pixel capacitor (sClc) and the holding capacitor (sCs) of the second sub-pixel, and the gate is coupled to the first transfer signal line (Tran).

2. The pixel driving circuit according to claim 1, characterized in that, The first pre-storage capacitor (Cs1) is coupled to the second source and drain of the first write transistor (T1), and the first source and drain of the first write transistor (T1) is coupled to the data signal line (Data) and the gate is coupled to the control signal line (Scan).

3. The pixel driving circuit according to claim 1, characterized in that, The end of the first pre-storage capacitor (Cs1) away from the transistor is coupled to the first coupled signal line (Couple).

4. The pixel driving circuit according to claim 1, characterized in that, The first source and drain of the second write transistor (T3) are also coupled to the first pre-storage capacitor (Cs1) and the second source and drain of the first write transistor (T1), and the gate is coupled to the control signal line (Scan).

5. The pixel driving circuit according to claim 1, characterized in that, The ends of the first pre-storage capacitor (Cs1) and the second pre-storage capacitor (Cs2) furthest from the transistor are coupled to the first coupled signal line (Couple).

6. The pixel driving circuit according to claim 1, characterized in that, The end of the second pre-storage capacitor (Cs2) away from the transistor is also coupled to the second coupled signal line (Couple2).

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