FPGA-based DDR3 multi-port read-write scheduling control method and system

Abstract

This invention relates to the field of control technology, and particularly to a method and system for DDR3 multi-port read / write scheduling control based on an FPGA. The method includes: generating read / write requests for DDR3 based on custom logic within the FPGA; identifying the read / write requests; and storing them in the corresponding storage queues based on the identification results. An RR scheduler determines whether the current storage queue is not empty, and executes a read / write operation based on the result, or skips the current storage queue and jumps to the next storage queue. When executing a read / write operation, the current queue request is converted into a MIG interface signal and a command is generated. The MIG interface signal is analyzed and the MIG ready signal is checked. Based on the signal analysis and check results, the command is executed to trigger a DDR3 operation, or the command is kept valid while waiting for MIG ready. When a DDR3 operation is triggered, the operation type is identified, and corresponding timing control is executed according to the identification result to complete the data read / write operation based on the execution result. This application achieves fairness in DDR3 multi-port read / write scheduling control.

Description

Technical Field

[0001] This invention relates to the field of control technology, and in particular to a method and system for scheduling and controlling DDR3 multi-port read and write operations based on FPGA. Background Technology

[0002] FPGA (Field Programmable Gate Array) is widely used in scenarios requiring real-time data storage and interaction, such as data acquisition, image processing, and communication systems, due to its high-speed parallel processing capabilities. Among these applications, multi-port concurrent access to external memory (such as DDR3 SDRAM) is a common requirement.

[0003] In existing technologies, when multiple ports of an FPGA perform read and write operations on DDR3 simultaneously, a scheduling mechanism based on queue flags is typically used. However, due to the characteristics of hardware description languages ​​or logical design defects, priority differences are automatically generated. This causes read and write operations in other queues to be continuously blocked when a certain port frequently initiates requests. The bandwidth resources of DDR3 are monopolized by a single queue for a long time, which in turn leads to problems such as data transmission delay, data loss, and even a decrease in system stability. Summary of the Invention

[0004] To address the aforementioned issues, this disclosure provides a method and system for DDR3 multi-port read / write scheduling control based on FPGA. Through a fair polling scheduler and MIGIP core interface timing control, it enables fair and efficient access to DDR3 from multiple ports.

[0005] Firstly, this application provides a DDR3 multi-port read / write scheduling control method based on FPGA, the method comprising, Read and write requests to DDR3 are generated based on custom logic within the FPGA, the read and write requests are identified, and the identification results are stored in the corresponding storage queue. The RR scheduler determines whether the current storage queue is not empty, and performs a read / write operation based on the result, or skips the current storage queue and jumps to the next storage queue; When a read or write operation is performed, the current queue request is converted into a MIG interface signal and a command is generated; Analyze the MIG interface signals and check the MIG ready signal. Based on the signal analysis results and signal check results, execute a command to trigger DDR3 operation, or keep the command valid and wait for MIG to be ready. When a DDR3 operation is triggered, the operation type is identified, and the corresponding timing control is executed according to the identification result to complete the data read and write operation based on the execution result.

[0006] Furthermore, The steps for identifying the read / write request include: Identify the read / write request structure and extract the port identifier based on the identification result; The port identifier is matched with the storage queue port, and the read / write request is stored in the corresponding storage queue based on the matching result.

[0007] Furthermore, The steps the RR scheduler takes to determine whether the current storage queue is not empty include: The scheduling pointer moves cyclically according to a preset order to determine whether the current storage queue pointed to by the pointer is not empty based on a non-empty condition; If the current storage queue is not empty, perform a read / write operation, and immediately jump to the next queue after completion; If the current storage queue is empty, skip the current storage queue and jump directly to the next storage queue.

[0008] Furthermore, The steps for analyzing the MIG interface signals and checking the MIG ready signals include: The current queue request is converted into a MIG interface signal, wherein the MIG interface signal includes an address signal, a command signal, and an enable signal; The validity of the address signal and the command signal is detected to obtain the validity detection result; The state of the enable signal and the MIG ready signal is detected to obtain the state detection result; Based on the validity detection result and the status detection result, execute the command to trigger DDR3 operation, or keep the command valid and wait for MIG to be ready.

[0009] Furthermore, The steps for detecting the validity of the address signal and the command signal include: The address information is compared with the DDR3 memory address space range, and the validity of the address signal is determined based on the comparison result. Verify whether the command signal is a valid enumeration value, and determine the validity of the command signal based on the verification result.

[0010] Furthermore, The steps of executing a command to trigger DDR3 operation based on the validity detection result and the status detection result, or keeping the command valid and waiting for MIG to be ready, include: When the address signal and the command signal are valid and the enable signal and the MIG ready signal are high, the command is executed to trigger DDR3 operation; When the address signal and the command signal are valid and the MIG ready signal is low, the address signal, the command signal and the enable signal remain valid until the MIG ready signal is high, at which point the command is executed to trigger the DDR3 operation.

[0011] Furthermore, Write operation timing control includes: Simultaneously monitor the write enable signal, write ready signal, and write data signal; The write data signal is written only when the write enable signal and the write ready signal are synchronously high. Data signal transmission is performed based on preset transmission parameter configuration; The last data transmission is performed by setting the end-of-data flag signal.

[0012] Furthermore, Read operation timing control includes: Send a read command and wait for a fixed delay period; Monitor the signal level of the data read, and read or discard the data based on the monitoring results.

[0013] Furthermore, The steps for monitoring the read data signal level status include: When the read data signal level is high, the read data signal is considered valid. When the read data signal level is low, the read data is discarded.

[0014] Secondly, based on the same inventive concept, this application provides a DDR3 multi-port read / write scheduling and control system based on FPGA, the system comprising: The storage module is used to generate read and write requests to DDR3 based on custom logic within the FPGA, identify the read and write requests, and store them in the corresponding storage queue based on the identification results. The judgment module, connected to the storage module, is used by the RR scheduler to determine whether the current storage queue is not empty, and to perform a read / write operation based on the judgment result, or to skip the current storage queue and jump to the next storage queue; An execution module, connected to the judgment module, is used to convert the current queue request into a MIG interface signal and generate a command when a read / write operation is performed; The analysis module, connected to the execution module, is used to analyze the MIG interface signals and check the MIG ready signal. Based on the signal analysis results and signal check results, it executes a command to trigger DDR3 operation, or keeps the command valid and waits for MIG to be ready. The read / write module, connected to the analysis module, is used to identify the operation type when a DDR3 operation is triggered, and to execute the corresponding timing control according to the identification result, so as to complete the data read / write operation according to the execution result.

[0015] Compared with the prior art, this application has the following advantages: 1. This invention adopts the principles of time-division multiplexing and fair round-robin scheduling, enabling multiple ports to complete data stream reading and writing with only one DDR3 controller. This fully utilizes the high-speed advantage of DDR3 while saving space design and FPGA pins, thereby reducing the cost of the FPGA chip.

[0016] 2. By using the polling mechanism of the RR scheduler and the empty queue skipping strategy, the implicit priority problem caused by the characteristics of FPGA language is solved at the hardware level, ensuring that all port requests have an equal scheduling opportunity.

[0017] Other features and advantages of this disclosure will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating a DDR3 multi-port read / write scheduling control method based on FPGA provided in an embodiment of the present invention; Figure 2 A schematic diagram of the memory MIGIP core interface in a DDR3 multi-port read / write scheduling control method based on FPGA provided in an embodiment of the present invention; Figure 3 The RR scheduling model diagram is provided in the DDR3 multi-port read / write scheduling control method based on FPGA according to an embodiment of the present invention. Figure 4 Command timing diagram of a DDR3 multi-port read / write scheduling control method based on FPGA provided in an embodiment of the present invention; Figure 5 A data writing timing diagram in a DDR3 multi-port read / write scheduling control method based on FPGA provided in an embodiment of the present invention; Figure 6This is a timing diagram of read data in a DDR3 multi-port read / write scheduling control method based on FPGA provided in an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0021] In the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0022] Figure 1 A flowchart illustrating a multi-port read / write scheduling control method for DDR3 based on an FPGA according to an embodiment of this disclosure is shown. Figure 1 As shown in this embodiment, the DDR3 multi-port read / write scheduling control method based on FPGA includes the following steps: Step S100: Generate read / write requests for DDR3 based on custom logic within the FPGA, identify the read / write requests, and store them in the corresponding storage queue based on the identification results; In step S200, the RR scheduler determines whether the current storage queue is not empty, and performs a read / write operation based on the result, or skips the current storage queue and jumps to the next storage queue. Step S300: When performing a read / write operation, convert the current queue request into a MIG interface signal and generate a command; Step S400: Analyze the MIG interface signal and check the MIG ready signal. Based on the signal analysis results and signal check results, execute a command to trigger DDR3 operation, or keep the command valid and wait for MIG to be ready. Step S500: When a DDR3 operation is triggered, the operation type is identified, and the corresponding timing control is executed according to the identification result, so as to complete the data read and write operation according to the execution result.

[0023] In this embodiment, the MIGIP core provided by Xilinx allows users to quickly establish access connections between the internal control logic of an FPGA (Field-Programmable Gate Array) and external memory on devices such as Kintex-7 via a User Interface Block. The memory MIGIP core interface is described below. Figure 2 As shown. The user interface replaces the native interface and resides at the front end of the design, performing data read and write operations. The memory controller sits between the UI module and the PHY (physical layer), providing reordering options and handling physical layer interface requests. The physical layer interface connects to external storage devices at the back end and is responsible for the timing of storage device signals. The DDR3 SDRAM controller uses a flexible user interface to reduce redundant accesses to the DDR3 SDRAM memory bank.

[0024] MIG simplifies the design process by generating unencrypted Verilog design documents, model simulation files, and related datasheets. By designing custom read / write modules based on the MIGIP core, both design flexibility, stability, and portability are ensured.

[0025] The basic module primarily generates the user interface logic clock, the storage control layer clock, and the physical layer clock. The user interface layer connects to the user's read / write logic at the front end and to the storage control layer at the back end. The MIG interface signals are shown in Table 1 below.

[0026] Table 1 MIGIP Interface Signals In step S100, the step of identifying the read / write request includes: Identify the read / write request structure and extract the port identifier based on the identification result; The port identifier is matched with the storage queue port, and the read / write request is stored in the corresponding storage queue based on the matching result.

[0027] In this embodiment, the physical port is directly mapped to an independent queue; Logical ports are mapped after being resolved using the VLAN / TCP field.

[0028] In step S200, the step by which the RR (Round Robin) scheduler determines whether the current storage queue is not empty includes: The scheduling pointer moves cyclically according to a preset order to determine whether the current storage queue pointed to by the pointer is not empty based on a non-empty condition; If the current storage queue is not empty, perform a read / write operation, and immediately jump to the next queue after completion; If the current storage queue is empty, skip the current storage queue and jump directly to the next storage queue.

[0029] The Round Robin scheduler is a round-robin scheduling mechanism that ensures fairness by cyclically allocating time slices to multiple request sources.

[0030] In this embodiment of the application, the non-empty determination condition is that each queue has a built-in FIFO counter (fifo_data_count) to count the number of valid requests in the queue in real time. When fifo_data_count>0, queue_empty=0 (a function to determine whether the queue is empty, used to confirm whether there are no elements in the queue); otherwise, queue_empty=1.

[0031] In this embodiment of the application, the preset order is based on the queue ports being sorted from smallest to largest, for example, 0→1→2→...→N→0.

[0032] The RR scheduler has no concept of priority; each queue is scheduled fairly.

[0033] The RR scheduler always moves sequentially to the next queue with packets to send (empty queues are skipped). If every queue has data waiting to be sent, the scheduling order matches the queue order; if some queues are empty, other queues are served frequently. In extreme cases, if all other queues are empty, a single queue can utilize the entire link bandwidth. When a packet enters an empty queue, that queue is served in the next loop, thus avoiding queue starvation.

[0034] as follows Figure 3 The diagram shows the RR scheduling model. Assume packets P0~P6~P… enter different priority queues according to their classification, where classification refers to mapping packets to priority queues based on their priority. If packets enter the queues as shown in the diagram, assuming there are three queues: Q2, Q1, and Q0, the RR scheduler first serves Q2, then Q1, then Q0, and continues to cycle through the queues. After scheduling one packet in each queue, it moves on to the next. The order of the packets after they exit is P0, P6, P11, P1, P7, P12.

[0035] The RR scheduling algorithm works by having the scheduler sequentially move to the next queue with packets to send (empty queues are skipped). If every queue has packets waiting to be sent, the scheduling order matches the queue order; if some queues are empty, other queues are served frequently. In extreme cases, if all other queues are empty, a single queue can utilize the entire link bandwidth. When a packet enters an empty queue, that queue is served in the next round, thus preventing queues from going unscheduled.

[0036] Step S400, the step of analyzing the MIG interface signal and checking the MIG ready signal includes: Step S410: Convert the current queue request into a MIG interface signal, wherein the MIG interface signal includes an address signal, a command signal, and an enable signal; Step S420: Detect the validity of the address signal and the command signal, and obtain the validity detection result; Step S430: Detect the state of the enable signal and the MIG ready signal to obtain the state detection result; Step S440: Execute a command to trigger DDR3 operation based on the validity detection result and the status detection result, or keep the command valid and wait for MIG to be ready.

[0037] In this embodiment of the application, the address signal is app_addr[28:0]; Command signals app_cmd[2:0] (3'b000 indicates a write operation, 3'b001 indicates a read operation); Set the enable signal app_en to high level.

[0038] In this embodiment of the application, the MIG ready signal app_rdy is checked: If app_rdy=1, then app_rdy is high; If app_rdy=0, then app_rdy is low.

[0039] Step S420, the step of detecting the validity of the address signal and the command signal, includes: The address information is compared with the DDR3 memory address space range, and the validity of the address signal is determined based on the comparison result. Verify whether the command signal is a valid enumeration value, and determine the validity of the command signal based on the verification result.

[0040] In this embodiment of the application, it is verified whether the address signal app_addr[28:0] is within the effective address space of the DDR3 memory (e.g., not exceeding the row / column / bank address range of the DDR3 chip); Verify that the command signal app_cmd[2:0] is a valid enumeration value: 3'b000 (write operation) or 3'b001 (read operation). Other values ​​are considered invalid commands.

[0041] In step S400, the step of executing a command to trigger DDR3 operation based on the validity detection result and the status detection result, or keeping the command valid and waiting for MIG to be ready, includes: When the address signal and the command signal are valid and the enable signal and the MIG ready signal are high, the command is executed to trigger DDR3 operation; When the address signal and the command signal are valid and the MIG ready signal is low, the address signal, the command signal and the enable signal remain valid until the MIG ready signal is high, at which point the command is executed to trigger the DDR3 operation.

[0042] When app_cmd and app_addr are valid and app_en and app_rdy are high, the command will be successfully sent to the DDR3 SDRAM controller. When app_cmd, app_addr, and app_en are valid but app_rdy is low, app_cmd, app_addr, and app_en must remain valid until app_rdy is pulled high in order for the command to be successfully sent to the DDR3 SDRAM controller. The timing is as follows: Figure 4 As shown, Figure 4 This is a command timing diagram.

[0043] In step S500, the write operation timing control includes: Simultaneously monitor the write enable signal, write ready signal, and write data signal; The write data signal is written only when the write enable signal and the write ready signal are synchronously high. Data signal transmission is performed based on preset transmission parameter configuration; The last data transmission is performed by setting the end-of-data flag signal.

[0044] In this embodiment of the application, the preset transmission parameters are configured such that the amount of data written in a single transaction is fixed at 256 bits, corresponding to 8 burst transmissions of the DDR3 physical layer; The user interface clock is a 1 / 4 division of the DDR3 physical clock, and a single clock cycle completes the entire burst transmission.

[0045] When writing data, you need to pay attention to the interfaces app_wdf_data (write data signal), app_wdf_wren (write enable signal), app_wdf_end (end data flag), and app_wdf_rdy (write ready signal).

[0046] `app_wdf_data` is valid. When `app_wdf_wren` goes high, `app_wdf_rdy` must also be high to indicate that data is currently being written to the DDR3 SDRAM controller. Figure 5 As shown, Figure 5 The timing diagram for data writing is provided. Although the control timing can be implemented separately, the execution of the write data command and the execution of the write data operation are one-to-one. The DDR3 SDRAM data width in this paper is 32 bits, and the actual read / write Burst is 8. Each DDR3 read / write operation involves a continuous 32-bit × 8 data operation. On the User Interface side, the logic clock is 4 times the DDR3 clock, and the data width is 256 bits. A single clock cycle completes one read / write operation with Burst=8. app_wdf_end needs to be pulled high to 1 during the last data write.

[0047] In step S500, the read operation timing control includes: Send a read command and wait for a fixed delay period; Monitor the signal level of the data read, and read or discard the data based on the monitoring results.

[0048] In this embodiment of the application, multiple read commands (up to 4) are sent to the MIGIP core in advance during continuous reading. Data for each command is returned in the order it was sent, and the last data is read using the app_rd_data_end flag. A single read operation consumes 256 bits of data, corresponding to 8 burst transfers in the DDR3 physical layer. The user interface clock is a 1 / 4 division of the DDR3 physical clock, and a single clock cycle completes the entire burst transmission.

[0049] In this embodiment, each data read operation requires initiating a read command first. After a valid read command is initiated, several clock cycles must be waited. When app_rd_data_valid goes high, app_rd_data is valid, and only then can the user logic read valid data. If data is read continuously, a series of valid commands must first be sent continuously from the UserInterface, followed by waiting several clock cycles until app_rd_data_valid goes high to read valid data. Figure 6 As shown, Figure 6 This is a timing diagram for reading data.

[0050] In summary: When the app_rdy and app_en signals are high, the address signal app_addr and the command signal app_cmd are valid. The user logic continuously sends valid read commands. After several cycles, it waits for the app_rd_data_valid signal to go high, at which point the read data app_rd_data is valid, completing the read operation. When the app_rdy and app_en signals are high, the address signal app_addr and the command signal app_cmd are valid. When the app_wdf_rdy and app_wdf_wren signals are high, the write data app_wdf_data is valid.

[0051] Specifically, the steps for monitoring the read data signal level include: When the read data signal level is high, the read data signal is considered valid. When the read data signal level is low, the read data is discarded.

[0052] When app_rd_data_valid=1 (high level), the read data signal (app_rd_data[255:0]) is considered valid; Invalid data rejection: Data read when app_rd_data_valid=0 (low level) is discarded; Based on the same inventive concept, this disclosure also provides an FPGA-based DDR3 multi-port read / write scheduling and control system corresponding to the above-described method, the system comprising: The storage module is used to generate read and write requests to DDR3 based on custom logic within the FPGA, identify the read and write requests, and store them in the corresponding storage queue based on the identification results. The judgment module, connected to the storage module, is used by the RR scheduler to determine whether the current storage queue is not empty, and to perform a read / write operation based on the judgment result, or to skip the current storage queue and jump to the next storage queue; An execution module, connected to the judgment module, is used to convert the current queue request into a MIG interface signal and generate a command when a read / write operation is performed; The analysis module, connected to the execution module, is used to analyze the MIG interface signals and check the MIG ready signal. Based on the signal analysis results and signal check results, it executes a command to trigger DDR3 operation, or keeps the command valid and waits for MIG to be ready. The read / write module, connected to the analysis module, is used to identify the operation type when a DDR3 operation is triggered, and to execute the corresponding timing control according to the identification result, so as to complete the data read / write operation according to the execution result.

[0053] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of the present invention.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A DDR3 multi-port read / write scheduling control method based on FPGA, characterized in that, include: Read and write requests to DDR3 are generated based on custom logic within the FPGA, the read and write requests are identified, and the identification results are stored in the corresponding storage queue. The RR scheduler determines whether the current storage queue is not empty, and performs a read / write operation based on the result, or skips the current storage queue and jumps to the next storage queue; When a read or write operation is performed, the current queue request is converted into a MIG interface signal and a command is generated; Analyze the MIG interface signals and check the MIG ready signal. Based on the signal analysis results and signal check results, execute a command to trigger DDR3 operation, or keep the command valid and wait for MIG to be ready. When a DDR3 operation is triggered, the operation type is identified, and the corresponding timing control is executed according to the identification result to complete the data read and write operation based on the execution result.

2. The FPGA-based DDR3 multi-port read / write scheduling control method according to claim 1, characterized in that, The steps for identifying the read / write request include: Identify the read / write request structure and extract the port identifier based on the identification result; The port identifier is matched with the storage queue port, and the read / write request is stored in the corresponding storage queue based on the matching result.

3. The FPGA-based DDR3 multi-port read / write scheduling control method according to claim 2, characterized in that, The steps the RR scheduler takes to determine whether the current storage queue is not empty include: The scheduling pointer moves cyclically according to a preset order to determine whether the current storage queue pointed to by the pointer is not empty based on a non-empty condition; If the current storage queue is not empty, perform a read / write operation, and immediately jump to the next queue after completion; If the current storage queue is empty, skip the current storage queue and jump directly to the next storage queue.

4. The FPGA-based DDR3 multi-port read / write scheduling control method according to claim 3, characterized in that, The steps for analyzing the MIG interface signals and checking the MIG ready signals include: The current queue request is converted into a MIG interface signal, wherein the MIG interface signal includes an address signal, a command signal, and an enable signal; The validity of the address signal and the command signal is detected to obtain the validity detection result; The state of the enable signal and the MIG ready signal is detected to obtain the state detection result; Based on the validity detection result and the status detection result, execute the command to trigger DDR3 operation, or keep the command valid and wait for MIG to be ready.

5. The FPGA-based DDR3 multi-port read / write scheduling control method according to claim 4, characterized in that, The steps for detecting the validity of the address signal and the command signal include: The address signal is compared with the DDR3 memory address space range, and the validity of the address signal is determined based on the comparison result. Verify whether the command signal is a valid enumeration value, and determine the validity of the command signal based on the verification result.

6. The FPGA-based DDR3 multi-port read / write scheduling control method according to claim 5, characterized in that, The steps of executing a command to trigger DDR3 operation based on the validity detection result and the status detection result, or keeping the command valid and waiting for MIG to be ready, include: When the address signal and the command signal are valid and the enable signal and the MIG ready signal are high, the command is executed to trigger DDR3 operation; When the address signal and the command signal are valid and the MIG ready signal is low, the address signal, the command signal and the enable signal remain valid until the MIG ready signal is high, at which point the command is executed to trigger the DDR3 operation.

7. The FPGA-based DDR3 multi-port read / write scheduling control method according to claim 6, characterized in that, Write operation timing control includes: Simultaneously monitor the write enable signal, write ready signal, and write data signal; The write data signal is written only when the write enable signal and the write ready signal are synchronously high. Data signal transmission is performed based on preset transmission parameter configuration; The last data transmission is performed by setting the end-of-data flag signal.

8. The FPGA-based DDR3 multi-port read / write scheduling control method according to claim 7, characterized in that, Read operation timing control includes: Send a read command and wait for a fixed delay period; Monitor the signal level of the data read, and read or discard the data based on the monitoring results.

9. The FPGA-based DDR3 multi-port read / write scheduling control method according to claim 8, characterized in that, The steps for monitoring the read data signal level status include: When the read data signal level is high, the read data signal is considered valid. When the read data signal level is low, the read data is discarded.

10. A DDR3 multi-port read / write scheduling and control system based on FPGA, characterized in that, The system includes: The storage module is used to generate read and write requests to DDR3 based on custom logic within the FPGA, identify the read and write requests, and store them in the corresponding storage queue based on the identification results. The judgment module, connected to the storage module, is used by the RR scheduler to determine whether the current storage queue is not empty, and to perform a read / write operation based on the judgment result, or to skip the current storage queue and jump to the next storage queue; An execution module, connected to the judgment module, is used to convert the current queue request into a MIG interface signal and generate a command when a read / write operation is performed; The analysis module, connected to the execution module, is used to analyze the MIG interface signals and check the MIG ready signal. Based on the signal analysis results and signal check results, it executes a command to trigger DDR3 operation, or keeps the command valid and waits for MIG to be ready. The read / write module, connected to the analysis module, is used to identify the operation type when a DDR3 operation is triggered, and to execute the corresponding timing control according to the identification result, so as to complete the data read / write operation according to the execution result.

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