FPGA-based universal digital decimation filtering method

Abstract

The application relates to a general digital variable sampling filter method based on FPGA, which comprises the following steps: obtaining target filter parameters, wherein the target filter parameters comprise a variable sampling rate and filter coefficients; based on the target filter parameters, a general cyclic shift register array-based digital filter data path preset in FPGA is configured; based on the variable sampling rate, handshake protocol timing of input and output data streams of the configurable digital filter data path is adaptively adjusted to realize data synchronization with upstream and downstream modules; and the configured configurable digital filter data path is used for filtering processing of input data streams to obtain output data streams meeting the target filter parameters. The application solves the technical problem of deep coupling between filter hardware and specific sampling rate parameters, and realizes high reuse of single design source code.

Description

Technical Field

[0001] This application relates to the field of digital signal processing, and in particular to a general digital variable sampling filtering method based on FPGA. Background Technology

[0002] In modern communication, radar, and software-defined radio systems, digital variable sampling filters are key components for converting sampling rates between different processing modules. For example, they are often used to connect high-speed sampling rate RF front-ends with low-speed sampling rate baseband processing units, matching their data throughput through decimation or interpolation operations. In FPGA-based implementations, the design of such filters is typically static and fixed. Specifically, designers determine the filter's structure and coefficients based on a defined sampling rate conversion factor (such as decimation or interpolation) and the desired frequency response. These design parameters are fixed during the hardware description language coding phase, and after synthesis, placement, and routing, a dedicated hardware circuit for that specific sampling rate conversion function is generated on the FPGA.

[0003] However, with the evolution and diversification of communication protocols, a single device often needs to support multiple operating modes or communication standards, such as switching between 4G, 5G, and wireless local area networks (WLANs), and the corresponding RF and baseband sampling rates may differ for each mode. Under the static design approach described above, whenever the system needs to adapt to a new sampling rate, the HDL source code of the filter must be modified, and a complex and time-consuming design verification process must be re-executed. Existing verified hardware modules cannot be directly reused for new parameter requirements, resulting in a lengthy design process, high development costs, and difficulty in quickly responding to changing application needs. Summary of the Invention

[0004] To address the technical challenge of deep coupling between filter hardware and specific sampling rate parameters, and to achieve high reusability of a single design source code, this application provides a general digital variable sampling filtering method based on FPGA.

[0005] This application provides a general digital variable sampling filtering method based on FPGA, which adopts the following technical solution:

[0006] A general digital variable sampling filtering method based on FPGA includes the following steps:

[0007] S1. Obtain the target filtering parameters, which include the variable sampling rate and filter coefficients;

[0008] S2. Based on the target filtering parameters, configure a digital filtering data path pre-set in the FPGA and based on a general-purpose circular shift register array;

[0009] S3. Based on the variable sampling rate, the handshake protocol timing of the input and output data streams of the configurable digital filter data path is adaptively adjusted to achieve data synchronization with upstream and downstream modules;

[0010] S4. The input data stream is filtered using the configured configurable digital filter data path to obtain an output data stream that conforms to the target filter parameters.

[0011] By employing the above technical solution, the physical structure of the configurable digital filtering data path pre-set within the FPGA is directly reconstructed using the acquired target filtering parameters. Specifically, this data path is built upon a general-purpose circular shift register array, and its internal data path connections, register depth, and the number of branches for parallel processing are not fixed. When a new variable sampling rate parameter is acquired, this parameter serves as direct input to the `generate` statement or array instantiation in the hardware description language, guiding the FPGA synthesis tool to generate a physically optimal circuit structure. For example, an N-fold decimation rate parameter will concretize the data path into an N-phase multiphase filter structure, thereby decomposing the originally high-speed serial operation into N low-speed parallel operations. This direct mapping mechanism from parameters to hardware structure is fundamental to achieving source code reuse in a single design, enabling filters with different functions to be generated from the same set of logic.

[0012] After the data path is configured according to the parameters, a rate counter dynamically set by these parameters is built into the module's output control logic. This allows for the use of the same variable sampling rate parameter to synchronize the data flow of the control interface. Based on the system clock, this counter's count value directly determines the minimum interval between two valid assertions of the output data valid signal TVALID. For example, when the N-fold decimation rate parameter is loaded, the rate counter will ensure that the TVALID signal is only allowed to be valid once after N input sampling cycles have been processed internally. In this way, the intrinsic rate of the data processing core is precisely materialized into the timing behavior of the external interface signals. This mechanism, which intrinsically binds the internal computation rhythm to the external handshake timing, enables the module's data throughput to be automatically announced to the downstream system, thus achieving reliable data flow synchronization without external intervention.

[0013] Optionally, S2 further includes:

[0014] Before configuring the digital filter data path, the read operation on the input first-in-first-out buffer is stopped, wherein the first-in-first-out buffer is used to receive and store the input data stream;

[0015] After configuring the digital filter data path, start the read operation on the first-in-first-out buffer.

[0016] By employing the above technical solution, this method first suspends the reading operation of the input first-in-first-out buffer before performing data path configuration. This allows the buffer to continue receiving and accumulating data from the upstream data generation end during the internal reconstruction of the data path, thereby decoupling the transient configuration process of the data path from the continuity of the upstream data flow.

[0017] After the data path is configured, the method immediately initiates a read operation on the buffer, enabling previously accumulated data and subsequent real-time data to be continuously processed by the configured data path. This coordinated control process of stopping and starting ensures the integrity of the input data throughout the entire cycle of parameter switching in the filter module, avoiding data loss or upstream link blockage that may occur due to module reconstruction.

[0018] Optionally, S2 further includes:

[0019] When the read operation on the first-in-first-out buffer is terminated, the current data volume in the first-in-first-out buffer is recorded as the transition data volume;

[0020] S4 further includes:

[0021] After initiating the read operation on the first-in-first-out buffer, a preset transition state identifier is placed in the corresponding output data stream for the data samples read from the first-in-first-out buffer in quantities equal to the amount of transition data.

[0022] By employing the above technical solution, this method accurately records the amount of data stored in the buffer at the moment the buffer read operation is stopped as the transition data amount. Then, when the data path is configured and data processing resumes, the method inserts a preset transition state flag into the output of a batch of initial data samples read from the buffer, the number of which is equal to the recorded transition data amount. This coordinated operation of recording and flag insertion embeds metadata into the data stream itself, enabling data to carry its historical state information as it traverses the system. This allows downstream data receivers to unambiguously identify which data was buffered during parameter changes.

[0023] Optionally, S1 includes:

[0024] Obtain parameters for a transitional data processing mode;

[0025] S4 includes:

[0026] Based on the transition data processing mode parameters, perform one of the following preset operations on the data sample with the transition state identifier:

[0027] Output the data sample and the transition state identifier; or discard the data sample and do not output it.

[0028] By employing the above technical solution, this method first obtains a transitional data processing mode parameter for decision-making. This allows for the selective output or direct discarding of data samples identified as transitional states in subsequent filtering steps.

[0029] The principle behind this approach is to centralize the handling of transitional data within the module and make its behavior configurable. It elevates a passive state marking function to an active, policy-based data flow management function. By providing the option to discard data samples, this method allows the filter module to present a simplified, standard flow interface with no data output during reconstruction, thus relieving downstream modules of the burden of adding extra logic for parsing and processing transitional state markers. This approach fundamentally reduces the complexity of system integration and improves the compatibility and ease of use of this general-purpose module across different system architectures.

[0030] Optionally, S1 includes:

[0031] Obtain a coefficient set selection index, wherein the FPGA stores multiple sets of coefficient sets corresponding to the coefficient set selection index;

[0032] S2 further includes:

[0033] Based on the coefficient set selection index, a target coefficient set is determined from the multiple sets of stored coefficient sets, and the configurable digital filter data path is configured with the target coefficient set.

[0034] By adopting the above technical solution, S1 first obtains a coefficient set selection index with a very small data volume. The configuration process of S2 then uses this index to directly determine and retrieve a target coefficient set from multiple coefficient sets stored internally by the FPGA, which is used to configure the data path. By presetting the coefficient set and simplifying external control input to an index, the external bus communication process, which might have involved a large amount of data throughput, is transformed into a high-speed on-chip memory addressing operation. This mechanism greatly shortens the time required to reconstruct the filter, solves the problem of excessive configuration delay caused by loading a large amount of coefficient data, and thus achieves fast and deterministic switching between different preset filtering modes.

[0035] Optionally, the memory storing the multiple sets of coefficients is a read-write random access memory;

[0036] The FPGA-based general digital variable sampling filtering method also includes:

[0037] At least one set of coefficients in the random access memory is received and overwritten via a configuration interface.

[0038] By adopting the above technical solution, the static coefficient set originally fixed in the hardware logic is transformed into a software resource that can be dynamically updated externally. This allows the device to adapt to new technical standards or operating modes through software updates, without the need for complete hardware integration and deployment.

[0039] Optionally, the random access memory includes at least two independent coefficient storage areas;

[0040] The step of receiving and overwriting at least one set of coefficients in the random access memory via a configuration interface includes the following sub-steps:

[0041] Designate one of the at least two independent coefficient storage areas as an online area for the configurable digital filter data path to read coefficients, and designate the other as an offline area;

[0042] Perform an overwrite operation on the coefficient set, wherein the overwrite operation on the coefficient set is performed only in the offline area;

[0043] After the overwrite operation in the offline area is completed, the offline area is switched to the online area.

[0044] By adopting the above technical solution, the coefficient memory is first partitioned into independent online and offline areas, and the coefficient overwrite operation is strictly limited to the offline area, thereby isolating the coefficient update action from the real-time reading action of the filter in physical storage space. After the overwrite operation is safely completed, the method performs a switching operation, designating the updated offline area as the new online area. The principle behind this series of steps is to construct a conflict-free update mechanism, which ensures that the filter data path reads a complete and consistent set of coefficients at all times, eliminating the possibility of reading partial updated data. This solution solves the technical problem of data corruption and system crashes that may occur due to read-write concurrency when performing real-time updates in read-write memory.

[0045] In summary, this application includes at least one of the following beneficial technical effects:

[0046] 1. By parametrically configuring a general hardware architecture and matching adaptive interface timing control, the technical problem of deep coupling between filter hardware and specific sampling rate parameters is solved, achieving high reuse of a single design source code, significantly shortening the development cycle for different application needs, and reducing R&D costs.

[0047] 2. By introducing data buffering, transient data identification, and configurable handling mechanisms, the problems of data loss and unclear data timeliness during dynamic reconstruction are solved, ensuring the integrity of data flow and the determinism of system behavior during parameter switching.

[0048] 3. By adopting a readable and writable coefficient storage area and a secure overwrite switching mechanism, the technical problems of fixed and unexpandable pre-stored scheme functions are solved, enabling the filter's functions to be updated and upgraded online after equipment deployment, enhancing design flexibility and product technology lifecycle. Attached Figure Description

[0049] Figure 1 A flowchart illustrating a general digital variable sampling filtering method based on FPGA is shown in one embodiment of the present invention. Detailed Implementation

[0050] The present application will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the application and are not intended to limit the scope of the application.

[0051] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the inventive concept. As part of this specification, some of the accompanying drawings of this disclosure are block diagrams illustrating structures and devices to avoid complicating the disclosed principles. For clarity, not all features of the actual embodiment need to be described. Furthermore, the language used in this disclosure has been primarily chosen for readability and instructional purposes and may not have been chosen to define or limit the subject matter of the invention, thus requiring the necessary claims to determine such inventive subject matter. References to “an embodiment” or “an embodiment” in this disclosure mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment, and multiple references to “an embodiment” or “an embodiment” should not be construed as necessarily referring to the same embodiment.

[0052] Unless explicitly defined, the terms “a,” “an,” and “the” are not intended to refer to a singular entity, but rather to include a general category whose specific examples can be used for illustration. Therefore, the use of the terms “a” or “an” can mean any number of at least one, including “a,” “one or more,” “at least one,” and “one or more.” The term “or” means any of the options and any combination of the options, including all options unless explicitly indicated that the options are mutually exclusive. The phrase “at least one of” when combined with a list of items refers to a single item in the list or any combination of items in the list. The phrase does not require all items listed unless explicitly defined as such.

[0053] In modern digital communication, software-defined radio, radar signal processing, and other high-performance signal processing systems based on field-programmable gate arrays (FPGAs), digital filters are widely used to perform critical tasks such as channel selection, anti-aliasing, interference suppression, and pulse shaping. Their performance directly affects the functionality and reliability of the entire system.

[0054] Among various types of digital filters, the digital variable sampling filter is a composite functional module that combines frequency-selective filtering and sampling rate conversion. Its basic function is to change the sampling rate of the input digital signal while filtering it. This change in sampling rate includes decimation (reducing the signal's sampling rate by a certain percentage) and interpolation (increasing the signal's sampling rate by a certain percentage). Its working principle is typically based on a finite impulse response (FIR) filter structure, with the core operation being a series of multiplication-accumulation operations. Specifically, the filter multiplies a series of input digital signal sample values ​​by a set of preset filter coefficients representing the filter's frequency response characteristics, and then accumulates all the products to generate a single output sample value. During the variable sampling process, the ratio between the rate at which input samples are consumed and the rate at which output samples are generated is determined by the set variable sampling rate parameter.

[0055] Modern communication and signal processing systems typically require a single hardware platform capable of supporting multiple different communication protocols or different operating modes within the same protocol. For example, a software-defined radio base station may need to switch between different communication standards such as 5G NR, LTE, or IoT, depending on service requirements; and within the 5G NR standard, it also needs to support multiple different channel bandwidth configurations, such as 20 MHz and 100 MHz. Each communication standard or operating mode corresponds to a unique set of signal processing parameters, including but not limited to signal bandwidth, symbol rate, and sampling rate. As a core component in the signal processing link, digital variable sampling filters must be able to adapt to these changes.

[0056] However, traditional FPGA-based digital filters typically employ a fixed or hard-coded design approach. Key functional parameters, such as variable sampling rates, the filter coefficient set defining its frequency response, and the structure of internal data paths (e.g., the number of parallel processing branches), are all determined during the hardware design phase. These parameters are written directly as constants into the hardware description language code and, through synthesis and place-and-route tools, are ultimately solidified into the logic circuit connections within the FPGA. The product of this design approach is a dedicated filter hardware module, one-to-one bound to a specific application scenario, with all its resources configured to achieve optimal performance under that set of fixed parameters.

[0057] The variable sampling rate of a filter directly determines the shift register depth and the number of parallel branches in the data path, while the filter coefficients are fixed in memory cells or combinational logic. This deep coupling results in extremely low reusability of the hardware modules. In modern multimode applications, when the system needs to switch to a new communication mode with different variable sampling rates or passband characteristics, the original filter hardware modules customized for the old mode cannot adapt to the new parameter requirements. Developers must go back to the design source, modify the hardware description language code, and re-execute the complete hardware development process, including logic synthesis, implementation, timing analysis, and functional verification. This process not only consumes a lot of engineering resources and time, but also cannot meet the requirements of modern communication systems for online and dynamic reconfiguration.

[0058] Therefore, this application discloses a general digital variable sampling filtering method based on FPGA. (Refer to...) Figure 1 The method includes the following steps S1-S4.

[0059] S1. Obtain the target filtering parameters, which include the variable sampling rate and filter coefficients.

[0060] S2. Based on the target filtering parameters, configure a digital filtering data path pre-set in the FPGA and based on a general-purpose cyclic shift register array.

[0061] S3. Based on the variable sampling rate, the handshake protocol timing of the input and output data streams of the configurable digital filter data path is adaptively adjusted to achieve data synchronization with upstream and downstream modules.

[0062] S4. The input data stream is filtered using the configured configurable digital filter data path to obtain an output data stream that conforms to the target filter parameters.

[0063] This method decouples filter functional parameters from the hardware physical structure through a mechanism that coordinates parameterized data paths with adaptive interface control. The hardware structure within the configurable digital filtering data path, such as the number of parallel processing branches or data shifting logic, is adjustable and determined by the target filtering parameters obtained by S1. This allows the same set of physical hardware resources to execute core filtering operations of different specifications based on different parameter configurations. The adaptive interface controller reads information such as the variable sampling rate from the target filtering parameters and dynamically adjusts the control timing of the output data interface accordingly, such as the generation rate of the valid output data signal, ensuring that the filtered data can be smoothly transmitted to the downstream processing module at the correct data flow rate matching the current configuration.

[0064] To implement the aforementioned method in detail, this application also provides a corresponding hardware device, which includes a configuration interface module, a parameter register group, a first-in-first-out buffer, a coefficient storage module, a configurable digital filter data path, and an adaptive interface controller, etc.

[0065] The configuration interface module and parameter register group are responsible for executing S1 in the aforementioned method, i.e., acquiring the target filtering parameters. Specifically, the configuration interface module provides a standard bus interface to external systems, such as the AXI4-Lite bus interface, to receive all target filtering parameters issued by upper-layer software or the processor. Internally, this module contains a set of parameter registers, designed using a memory-mapped architecture. Each dynamically configurable parameter, such as variable sampling rate, coefficient set selection index for selecting a specific filter coefficient set, and transition data processing modes (described later), is assigned a unique, fixed bus address. When an external system writes parameter data to the specified address via a bus write operation, the configuration interface module latches the data into the corresponding parameter register. The output of the parameter register group is a set of parallel parameter signals that remain stable until a reconstruction is complete. These signals are distributed to all other modules within the device that require these parameters to function.

[0066] After obtaining new target filtering parameters through the configuration interface, the relevant modules within the hardware device, especially the configurable digital filtering data path, require a finite transient time to reconstruct their internal computational structures. During this period, the data path cannot process data correctly. To ensure the continuity and integrity of the data flow during the online reconstruction process, this application embodiment includes a first-in-first-out (FIFO) buffer. To address this data integrity issue during the online reconstruction process, in a preferred embodiment, between S1 and S2, the method further includes: during the transient process of the configurable digital filtering data path being configured according to the new target filtering parameters, using a FIFO buffer to buffer the externally input data flow to prevent data loss.

[0067] This FIFO buffer acts as a data stream reservoir during the transient process of system parameter reconstruction. Its input can be implemented as a standard AXI-Stream data stream interface for connection to the upstream standard data generation module; its output is a standard FIFO interface for reading data from the internally configurable digital filtered data path. The storage depth of the FIFO buffer needs to be set according to the longest possible reconstruction time and the highest input data rate to ensure sufficient space to buffer continuously input real-time data during reconstruction. The read enable signal of the FIFO buffer is precisely controlled by the adaptive interface controller. When the controller initiates a reconstruction process, it temporarily disables read operations on the FIFO buffer, pausing the data flow to the data path; after reconstruction is complete, the controller resumes its read operation. In this way, the continuous upstream data generation process is decoupled from the transient reconstruction process within the device, effectively preventing data loss.

[0068] The hardware device in this embodiment further includes a coefficient storage module for storing and providing one or more sets of filter coefficients required by the configurable digital filtering data path during operation. This coefficient storage module can pre-store multiple different coefficient sets to correspond to various preset filtering modes. Correspondingly, the target filtering parameters obtained in S1 include a coefficient set selection index; that is, the filter coefficients in the target filtering parameters are obtained by looking up a table from a preset coefficient storage module according to the coefficient set selection index. The input interface of this module receives the coefficient set selection index from the parameter register group as a read address and, based on the index, outputs the corresponding coefficient set data to the configurable digital filtering data path. This implementation can be based on read-only memory (ROM) or random access memory (RAM) loaded during system initialization.

[0069] To support in-situ updates or adaptive filtering, in a preferred embodiment, the coefficient storage module is designed to be online-updatable. Specifically, the coefficient storage module is a read-write random access memory (RAM), and the method further includes: updating the filter coefficients stored in the random access memory online via a configuration interface. This means that in addition to providing a coefficient read channel for the data path, the module also includes a write data channel connected to the aforementioned configuration interface module, allowing upper-layer software to write a completely new set of coefficients into the storage module via bus operations during system runtime.

[0070] To address potential read / write conflicts during online coefficient updates and ensure the instantaneous and reliable switching of coefficients, in a preferred embodiment, the random access memory includes at least two independent storage areas. The method further includes: simultaneously providing the current coefficients for the digital filter data path in one storage area and writing the updated coefficients to the other storage area via the configuration interface, thereby achieving conflict-free online coefficient updates. These two storage areas, a working area and a spare area, achieve physical isolation between read and write operations. During normal system operation, the data path always reads stable and valid coefficients from the working area. Meanwhile, the upper-layer software can securely write a new set of coefficients to the spare area via the configuration interface. After all new coefficients have been written, the controller can switch the spare area to the new working area through an atomic operation, thereby achieving uninterrupted and instantaneous switching of filter characteristics.

[0071] Furthermore, in a preferred embodiment, the hardware device further includes a configurable digital filtering data path. The input interface of this data path is connected to the output of a first-in-first-out buffer and the output of a coefficient storage module, respectively, to receive data samples and filter coefficients; its output sends the calculated filtered data to a subsequent adaptive interface controller for processing.

[0072] The physical structure of this configurable digital filtering data path is not fixed for specific parameters, but is built upon a general, parameterizable array of circular shift registers. The structural characteristics of the data path, such as the number of parallel processing branches, the logic of data shifting, and the resource allocation of multipliers and adders, are directly determined by the target filtering parameters obtained from the parameter register set, particularly parameters such as the variable sampling rate. This determination mechanism allows for the generation of optimized hardware instances for specific needs during FPGA synthesis via parameter input, and also enables the data path to be dynamically adjusted during system runtime via configuration signals.

[0073] Furthermore, in a preferred embodiment, the hardware device also includes an adaptive interface controller. This output data processing module performs final processing on the raw filtering results from the configurable digital filtered data path and formats them into a standard AXI-Stream data stream for output to downstream modules. Specifically, the adaptive interface controller reads the currently active variable sampling rate parameter from a parameter register set and dynamically controls the handshake protocol timing of the output AXI-Stream interface based on this parameter. For example, it precisely adjusts the generation rate of the output data valid signal to ensure that data samples are output at the correct time intervals that conform to the target sampling rate, thereby maintaining synchronization with downstream modules.

[0074] The adaptive interface controller also processes transitional data generated during parameter reconstruction to ensure the determinism of the data stream. In a preferred embodiment, S4 further includes: for data samples read from the FIFO buffer in quantities equal to the amount of transitional data, a preset transitional state identifier is placed in the corresponding output data stream. That is, after the transient process ends, the data cached in the FIFO buffer is output as transitional data, and a transitional state identifier is appended when the transitional data is output. To achieve this function, the controller has a built-in counter that records the amount of data cached in the FIFO buffer at the start of reconstruction. When reconstruction is complete and the cached data is processed and output sequentially, the controller appends a specific transitional state identifier to these data via a sideband signal, such as the TUSER signal in the AXI-Stream interface.

[0075] To provide flexible processing capabilities for the transition data, in a more preferred embodiment, the target filtering parameters further include a transition data processing mode, and the aforementioned method further includes: performing a preset processing operation on the transition data with the attached transition state identifier according to the transition data processing mode; the processing operation includes outputting the data sample and the transition state identifier; or discarding the data sample and not outputting it. This transition data processing mode parameter is set by the upper-layer software through a configuration interface. The adaptive interface controller performs corresponding processing operations on the marked transition data according to the set value of this parameter. For example, when the mode is set to discard, the controller will suppress the valid output of the data valid signal when outputting this part of the data; when the mode is set to normal output, it will be output normally.

[0076] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0077] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A general digital variable sampling filtering method based on FPGA, characterized in that, Includes the following steps: S1. Obtain the target filtering parameters, which include the variable sampling rate and filter coefficients; S2. Based on the target filtering parameters, configure a digital filtering data path pre-set in the FPGA and based on a general-purpose circular shift register array; wherein, the data path is built on the general-purpose circular shift register array, and the internal data path connection relationship, register depth and the number of parallel processing branches are not fixed; the number of parallel processing branches of the data path, the data shifting logic and the resource calls of multipliers and adders are all directly determined by the target filtering parameters obtained from the parameter register group; S3. Based on the variable sampling rate, the handshake protocol timing of the input and output data streams of the configurable digital filter data path is adaptively adjusted to achieve data synchronization with upstream and downstream modules; wherein, a rate counter dynamically set by the parameter is built into the output control logic of the module, and the same variable sampling rate parameter is used to synchronize the data stream of the control interface; the counter is based on the system clock, and its count value directly determines the minimum interval between two valid assertions of the output data valid signal TVALID; S4. The input data stream is filtered using the configured configurable digital filter data path to obtain an output data stream that conforms to the target filter parameters.

2. The general digital variable sampling filtering method based on FPGA according to claim 1, characterized in that, S2 further includes: Before configuring the digital filter data path, the read operation on the first-in-first-out buffer is stopped, wherein the first-in-first-out buffer is used to receive and store the input data stream; After configuring the digital filter data path, start the read operation on the first-in-first-out buffer.

3. The general digital variable sampling filtering method based on FPGA according to claim 2, characterized in that, S2 further includes: When the read operation on the first-in-first-out buffer is terminated, the current data volume in the first-in-first-out buffer is recorded as the transition data volume; S4 further includes: After initiating the read operation on the first-in-first-out buffer, a preset transition state identifier is placed in the corresponding output data stream for the data samples read from the first-in-first-out buffer in quantities equal to the amount of transition data.

4. The general digital variable sampling filtering method based on FPGA according to claim 3, characterized in that, S1 includes: Obtain parameters for a transitional data processing mode; S4 includes: Based on the transition data processing mode parameters, perform one of the following preset operations on the data sample with the transition state identifier: Output the data sample and the transition state identifier; or discard the data sample and do not output it.

5. The general digital variable sampling filtering method based on FPGA according to claim 1, characterized in that, S1 includes: obtaining a coefficient set selection index, wherein the FPGA stores multiple sets of coefficient sets corresponding to the coefficient set selection index; S2 further includes: selecting an index based on the coefficient set, determining a target coefficient set from the multiple sets of stored coefficient sets, and configuring the configurable digital filter data path with the target coefficient set; The target filtering parameters obtained in S1 include the coefficient set selection index. The filter coefficients in the target filtering parameters are obtained by looking up a table from a preset coefficient storage module according to the coefficient set selection index.

6. The general digital variable sampling filtering method based on FPGA according to claim 5, characterized in that, The memory storing the multiple sets of coefficients is a read-write random access memory; The FPGA-based general digital variable sampling filtering method also includes: At least one set of coefficients in the random access memory is received and overwritten via a configuration interface.

7. The general digital variable sampling filtering method based on FPGA according to claim 6, characterized in that, The random access memory includes at least two independent coefficient storage areas; The step of receiving and overwriting at least one set of coefficients in the random access memory via a configuration interface includes the following sub-steps: Designate one of the at least two independent coefficient storage areas as an online area for the configurable digital filter data path to read coefficients, and designate the other as an offline area; Perform an overwrite operation on the coefficient set, wherein the overwrite operation on the coefficient set is performed only in the offline area; After the overwrite operation in the offline area is completed, the offline area is switched to the online area.

Images