All two-dimensional vertical structure metal-semiconductor field effect transistor and preparation method thereof

Abstract

The application discloses a full two-dimensional vertical structure metal-semiconductor field effect transistor and a preparation method thereof. A vertical stacked source, a lower isolation layer, a drain and an upper isolation layer are formed on the surface of a substrate, an inclined side wall is formed, a channel covers the inclined side wall, a gate is self-aligned with the channel, a semimetal gate is directly contacted with a semiconductor channel to form a Schottky junction; the application is based on a full two-dimensional material system, can effectively inhibit Fermi pinning effect and unintentional doping, and can optimize device performance by optimizing gate control ability and electrical contact performance; no gate dielectric layer is used, and problems such as electrical performance deterioration under limit microscale can be avoided; the structure microscale is used to improve device integration density, and research and development and manufacturing cost control can be simultaneously realized while excellent performance is maintained; the side wall vertical structure is used to simultaneously and accurately microscale the channel length and the contact length; and the application can be applied to the industrial application fields of next-generation integrated circuit chips, high-density memories, flexible and wearable electronics and the like which break through the physical limit of silicon.

Description

Technical Field

[0001] This invention relates to the fabrication technology of field-effect transistors, specifically to a fully two-dimensional vertical structure metal-semiconductor field-effect transistor and its fabrication method. Background Technology

[0002] Field-effect transistors (FETs) are the core components of modern integrated circuits. In the post-Moore's Law era, silicon-based FETs are gradually approaching physical and semiconductor process limits, facing challenges such as short-channel effects and power consumption. Two-dimensional materials, with their atomic-level thickness and absence of dangling bonds, hold promise for overcoming the short-channel effect bottleneck and solving the power consumption problem. Furthermore, two-dimensional materials have advantages in constructing novel nanoscale devices. Current reports on two-dimensional material FETs mainly focus on traditional metal-oxide-semiconductor field-effect transistors (MOSFETs), where the source, drain, and gate still use metal and amorphous dielectric materials, and most studies only target the miniaturization of the two-dimensional material channel. Recent research indicates that the deposition process of metal and amorphous dielectrics can easily damage two-dimensional materials, affecting device performance. Moreover, increasing integration density requires simultaneous miniaturization of both channel and contact lengths. Currently, methods for achieving short channels or short contacts mainly rely on electron beam lithography, which is cumbersome and costly. Therefore, developing nanoscale FET devices based on entirely two-dimensional material systems and establishing a short-channel and short-contact fabrication process that does not rely on photolithography precision are crucial for overcoming existing technological bottlenecks and advancing further device miniaturization. Summary of the Invention

[0003] To address the problems existing in the prior art, this invention proposes a fully two-dimensional vertical structure metal-semiconductor field-effect transistor and its fabrication method.

[0004] Channel length refers to the physical length of the semiconductor channel region below the gate, from the source to the drain. Contact length refers to the length of the region outside the gate where the metal electrode connects to the semiconductor.

[0005] One object of the present invention is to propose a fully two-dimensional vertical structure metal-semiconductor field-effect transistor.

[0006] The fully two-dimensional vertical structure metal-semiconductor field-effect transistor of the present invention includes: a substrate, a source, a drain, a lower isolation layer, an upper isolation layer, a two-dimensional semiconductor channel, and a gate; wherein, the substrate is made of an insulating material; a first electrode, a lower isolation layer, a second electrode, and an upper isolation layer are vertically stacked sequentially from bottom to top on the surface of the substrate, and the two electrodes insulated and isolated by the lower isolation layer serve as the source and drain, respectively. The stacking order of the source and drain can be interchanged, and the thickness of the source is greater than that of the drain to mitigate the current crowding effect; the source and drain are made of a few-layer half-metal phase two-dimensional material; the lower isolation layer and the upper isolation layer are made of a few-layer insulator. Two-dimensional semiconductor phase material; photolithography and etching are performed on the stacked region to form inclined sidewalls with an inclination angle of 30° to 90°; a few layers or a single layer of semiconductor phase two-dimensional material are covered on part of the upper isolation layer surface and the inclined sidewalls to form a channel; multiple layers of half-metal phase two-dimensional material are coated on the surface of part of the channel as gate, the area of ​​the half-metal phase two-dimensional material is smaller than the area of ​​the semiconductor phase two-dimensional material; using the gate as a mask, the excess part of the semiconductor phase two-dimensional material serving as the channel is removed to achieve self-alignment of the gate and the channel, and the channel is completely covered by the gate; for n-type channels, the gate is a high work function half-metal phase two-dimensional material. For p-type channels, the gate is a two-dimensional half-metallic material with a low work function. There is a significant difference between the electron affinity of the channel and the work function of the gate. Charge transfer occurs after direct contact between the semiconductor channel and the half-metallic gate until the Fermi level aligns. At this point, band bending forms a depletion region and a Schottky barrier. A Schottky junction is formed by the direct contact between the half-metallic gate and the semiconductor channel. The channel length depends on the thickness of the lower isolator, and the contact length depends on the thickness of the source and drain. The source, drain, and lower isolator are all two-dimensional materials. This is achieved by simultaneously reducing the thickness of the lower isolator and the source and drain. This design achieves a high degree of miniaturization, reducing both channel and contact lengths. A fully two-dimensional vertical heterostructure combining a double-insulating layer with edge contacts and a fully covered self-aligned gate allows for simultaneous miniaturization to sub-10nm levels without relying on high-precision photolithography. Three mutually insulated metal electrodes are formed on the substrate surface. The gate electrode is connected to an external control voltage source via the corresponding metal electrode. The source and drain electrodes are connected to an external constant voltage source via corresponding metal electrodes. A Schottky junction is formed between the semi-metallic gate and the semiconductor channel for gate control. The channel conductivity is controlled by modulating the barrier width using the gate voltage, thereby achieving FET functionality.

[0007] The substrate material is silicon / silicon oxide (Si / SiO2), sapphire, or quartz. The source and drain electrodes are made of graphene (FLG) with a thickness of 5–20 nm. The lower and upper barrier layers are made of hexagonal boron nitride (hBN) with a thickness of 5–15 nm. The channel material is made of molybdenum sulfide (MoS2), tungsten sulfide (WS2), molybdenum telluride (MoTe2), or tungsten selenide (WSe2) with a thickness of 0.7–5 nm. The gate material is made of titanium disulfide (TiS2) or niobium disulfide (NbS2) with a thickness of 50–120 nm.

[0008] The gate of the semi-metal directly contacts the channel of the semiconductor to form a Schottky junction, without a gate dielectric layer, thus avoiding problems such as the deterioration of electrical performance under extreme miniaturization; in terms of processing, it can completely avoid the deposition of metal and dielectric on two-dimensional materials.

[0009] Another objective of this invention is to provide a method for fabricating a fully two-dimensional vertical structure metal-semiconductor field-effect transistor.

[0010] The method for fabricating a fully two-dimensional vertical structure metal-semiconductor field-effect transistor of the present invention includes the following steps:

[0011] 1) Provide an insulating substrate, on which three mutually insulated metal electrodes are formed respectively;

[0012] 2) Two-dimensional materials for the first electrode, lower insulating layer, second electrode, upper insulating layer, and gate are obtained from bulk layered materials by chemical vapor deposition (CVD) or mechanical exfoliation. Materials with thicknesses matching the design thickness are screened by optical microscopy and atomic force microscopy (AFM) and stored for later use. The first and second electrodes are made of few-layer semi-metallic phase two-dimensional materials, and the lower and upper insulating layers are made of few-layer insulating phase two-dimensional materials.

[0013] 3) The first electrode, the lower insulating layer, the second electrode, and the upper insulating layer are stacked vertically from bottom to top on the surface of the substrate;

[0014] 4) Low-pressure hot annealing treatment to obtain a four-layer vertical heterostructure; the two electrodes, which are insulated and isolated by the lower insulating layer, serve as the source and drain respectively. The thickness of the source is greater than that of the drain to reduce the current crowding effect.

[0015] 5) Ultraviolet lithography and etching processes are used to expose the inclined sidewalls of the four-layer vertical heterostructure in step 4).

[0016] 6) Obtain few-layer or monolayer semiconductor phase two-dimensional materials by chemical vapor deposition (CVD) or mechanical exfoliation;

[0017] 7) Transfer the semiconductor phase two-dimensional material to the surface of the four-layer vertical heterostructure with inclined sidewalls obtained in step 5), covering part of the upper insulating layer surface and the inclined sidewalls; transfer the half-metal phase two-dimensional material as the gate onto the semiconductor phase two-dimensional material, the area of ​​the half-metal phase two-dimensional material as the gate is smaller than the area of ​​the semiconductor phase two-dimensional material, use the gate as a mask and use etching technology to remove the semiconductor phase two-dimensional material not covered by the gate to form a channel, so that the gate and the channel are precisely self-aligned and the channel is completely covered by the gate;

[0018] The channel length depends on the thickness of the lower isolation layer, and the contact length depends on the thickness of the source and drain. The source, drain, and lower isolation layer materials are all two-dimensional materials. By simultaneously reducing the thickness of the lower isolation layer and the source and drain, the channel length and contact length are reduced.

[0019] 8) Perform low-pressure thermal annealing to complete the fabrication of a fully two-dimensional vertical structure MESFET with both nanoscale channel length and contact length;

[0020] 9) Gate control:

[0021] The gate is connected to an external control voltage source through a corresponding metal electrode; the source and drain are connected to an external constant voltage source through corresponding metal electrodes.

[0022] When no gate voltage is applied, i.e., V G When V = 0, the Schottky junction formed by the half-metal-semiconductor contact is in thermal equilibrium. Its built-in barrier generates a depletion region of a certain width in the channel, which has channel carriers but a low concentration, and is in a partially pinch-off state. This is manifested by the source-drain current being at the off-state current level on the order of nanoamperes (nA). When a positive gate voltage, V = 0, is applied to the gate, the Schottky junction is in thermal equilibrium. G When the voltage is greater than 0, the depletion region narrows, the Schottky barrier decreases, the channel carrier concentration increases, and the channel is in a conducting state, manifested as a significant increase in source-drain current to the microampere (μA) level; when a negative gate voltage is applied to the gate, i.e., V0 G <

[0023] At 0, the depletion region widens, the Schottky barrier increases, and the channel carrier concentration decreases, resulting in a completely pinch-off state. This manifests as a reduction in source-drain current to an extremely low off-state current level on the order of picoamperes (pA). This allows for gate control by forming a Schottky junction between the half-metal gate and the semiconductor channel. The channel conductivity is controlled by modulating the barrier width through the gate voltage, thereby achieving the FET function.

[0024] In step 1), the metal evaporation method employs common deposition processes such as electron beam evaporation (EBE), thermal evaporation (TE), and magnetron sputtering. After ultraviolet lithography development and stripping, oxygen plasma is used to remove photoresist residue to reduce the surface roughness of the pre-fabricated electrode. The metal material is usually a combination of titanium / gold (Ti / Au), chromium / gold (Cr / Au), or palladium / gold (Pd / Au) adhesion layer metal material / conductive layer metal material.

[0025] In step 3), the transfer method is the polydimethylsiloxane (PDMS) stamp-assisted dry transfer method or other commonly used dry transfer methods; one end of the source / drain material is in contact with the pre-fabricated metal electrode and the two are separated by the lower isolation layer material; if the lower isolation layer cannot completely isolate the source and drain, the part in direct contact between the two is removed simultaneously in the photolithography and etching process in step 5).

[0026] In step 4), annealing is typically performed in a tube furnace under an argon / hydrogen (Ar / H2) atmosphere at a temperature of 180–300°C for 1–3 hours. This step reduces the density of bubbles and impurities in vertical heterostructures, contributing to a cleaner interface.

[0027] In step 5), after UV lithography development, oxygen plasma is used to remove residual photoresist at the window position; etching is performed using reactive ion etching (RIE), inductively coupled plasma-reactive ion etching (ICP-RIE), or ion beam sputtering etching; the obtained sidewall tilt angle range is 30° to 90°; the environmental atmosphere for RIE is oxygen (O2) and trifluoromethane (CHF3); the environmental atmosphere for ion beam sputtering etching is Ar; after etching is completed, oxygen plasma is used to remove some of the carbonized photoresist, and then the sample is immersed in acetone heated in a water bath to achieve complete removal of the photoresist.

[0028] In step 7), if it is a large-area monolayer film grown by CVD, a polymethyl methacrylate (PMMA)-assisted wet transfer method or other commonly used wet transfer methods are adopted; if it is a mechanically exfoliated nanosheet, a PDMS stamp-assisted dry transfer method or other commonly used dry transfer methods are adopted. The self-aligned etching method for the gate material and the channel material can be RIE or oxygen plasma etching.

[0029] In step 8), the annealing conditions are the same as in step 4).

[0030] In step 9), the voltage range of the voltage source is adjusted to -5 to 5V; the voltage range of the constant voltage source is 0.01 to 2V.

[0031] Advantages of this invention:

[0032] This invention is based on a fully two-dimensional material system, and its significant advantages stem from its unique process and structural design: it can form a clean van der Waals interface, and the entire process avoids the direct deposition of metals or amorphous dielectrics on the two-dimensional material. The semiconductor channel is completely covered by the gate, and no additional patterning process is required. It is self-aligned, effectively suppressing the Fermi pinning effect and unintentional doping, allowing the intrinsic properties of the material to be fully utilized. Furthermore, it optimizes device performance by optimizing gate control capability and electrical contact performance. It utilizes the direct contact between the semi-metallic gate and the semiconductor channel to form a Schottky junction, with no gate dielectric layer in the structure. This avoids problems such as electrical performance degradation under extreme miniaturization, and avoids the deposition of metals and dielectrics on the two-dimensional material. Gate control is achieved by forming a Schottky junction between the gate and the semiconductor. It achieves structural miniaturization and cost control: the interface of the fully two-dimensional stacked structure is superior to that of traditional MOSFETs, and it can maintain excellent performance while miniaturizing. It does not require electron beam exposure and cleverly utilizes the vertical sidewall structure to simultaneously and accurately miniaturize the channel length and contact length, which significantly reduces the R&D and manufacturing costs of miniaturized devices while increasing device integration density. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of an embodiment of the all-two-dimensional vertical structure metal-semiconductor field-effect transistor of the present invention;

[0034] Figure 2 The Raman spectral characterization diagrams of an embodiment of the all-two-dimensional vertical structure metal-semiconductor field-effect transistor of the present invention are shown below. (a) is the Raman spectral characterization diagram of the MoS2-TiS2 heterojunction, and (b) is the Raman spectral characterization diagram of the FLG-hBN-FLG-hBN-MoS2 heterojunction.

[0035] Figure 3 This is an AFM characterization diagram of an embodiment of the all-two-dimensional vertical structure metal-semiconductor field-effect transistor of the present invention;

[0036] Figure 4 The following are electrical performance diagrams of an embodiment of the all-two-dimensional vertical structure metal-semiconductor field-effect transistor of the present invention, wherein (a) is a transfer characteristic curve of the device; (b) is a subthreshold swing, on / off ratio and threshold voltage of the device under different source-drain voltages extracted from (a); (c) is a curve showing the relationship between the subthreshold swing and source-drain current of the device under different source-drain voltages; and (d) is a curve showing the output characteristic of the device. Detailed Implementation

[0037] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0038] like Figure 1 As shown, the fabrication method of the fully two-dimensional vertical structure metal-semiconductor field-effect transistor in this embodiment includes the following steps:

[0039] 1) An insulating silicon / silicon oxide (Si / SiO2) substrate is provided and sequentially placed in acetone, anhydrous ethanol, and deionized water, and ultrasonicated in an ultrasonic bath for 10 / 10 / 20 minutes respectively to thoroughly clean the substrate surface. Subsequently, three independent Ti / Au metal electrodes (thickness of 5 / 25nm) required for electrical testing are prefabricated on the cleaned substrate using ultraviolet lithography, EBE, and lift-off processes. In this process, after development and lift-off, oxygen plasma is used to treat the substrate in a low-pressure environment of 1 Torr for 10 minutes to further remove photoresist residue and other impurities, thereby reducing electrode surface roughness and contact resistance. The use of prefabricated electrodes can effectively suppress negative effects such as Fermi pinning and unintentional doping.

[0040] 2) Under an optical microscope, FLG materials with a thickness of 5-20 nm were mechanically peeled off from commercial bulk materials using adhesive tape. These materials served as the source and drain, respectively; hBN materials with a thickness of 5-15 nm were used as the lower and upper isolation layers, respectively; and TiS2 nanosheets with a thickness of 50-120 nm were used as the gate material. The thickness of the nanosheets was measured by atomic force microscopy (AFM).

[0041] 3) The first electrode, the lower isolation layer, the second electrode and the upper isolation layer are vertically stacked from bottom to top on the surface of the substrate using the PDMS stamp-assisted dry transfer method to form a source-lower isolation layer-drain-upper isolation layer vertical heterostructure.

[0042] 4) Placed in a tube furnace, low-pressure hot annealing is performed to remove PDMS residues, reduce bubble density, and improve contact. The annealing atmosphere is an Ar / H2 mixture with a flow rate of 10 / 40 sccm, a pressure of 0.45 Torr, a temperature of 200℃, and a time of 2 hours. A four-layer vertical heterostructure is obtained. The thickness of the source electrode is greater than that of the drain electrode to mitigate the current crowding effect.

[0043] 5) Ultraviolet lithography is performed to define the etching window. After photolithography and development, the sample needs to be cleaned with oxygen plasma to remove photoresist residue at the edge of the etching window. The etching process is RIE. Since it is a partially anisotropic etching process, the etching angle can be controlled by controlling the etching atmosphere, flow rate and time to obtain tilted sidewalls. The RIE ambient atmosphere is O2 / CHF3 and the flow rate is 20 / 1 sccm. A higher oxygen flow rate is used to avoid drilling into the thinner hBN. After RIE, the carbonized photoresist on the surface is removed again by dry oxygen plasma. Then the sample is immersed in acetone heated in a water bath at ~50°C to achieve complete removal of the photoresist.

[0044] 6) Using high-purity molybdenum trioxide powder (MoO3, 130 mg) and sulfur powder (S, sufficient amount) as reaction sources, and perylene-3,4,9,10-tetrapotassium tetracarboxylate (PTAS) as seed source, a large-area monolayer MoS2 film was grown on a Si / SiO2 substrate by CVD. The growth atmosphere was Ar, the flow rate was 15 sccm, and the pressure was atmospheric pressure. The S powder was placed in the upstream temperature zone at 150 °C, and the MoO3 powder, PTAS and substrate were placed in the downstream temperature zone at 650 °C. The growth time was 5 minutes to obtain a few-layer or monolayer semiconductor phase two-dimensional material.

[0045] 7) The large-area monolayer MoS2 film prepared in step 6) is transferred to the inclined sidewall in a deionized water environment using a PMMA-assisted wet transfer method. Subsequently, the TiS2 obtained in step 2) is transferred onto the MoS2 using a PDMS stamp-assisted dry transfer method. At this time, the MoS2 completely covers the target area. Using TiS2 as a mask, the gate and channel are precisely self-aligned using an RIE. The ambient atmosphere of the RIE is O2. The FLG obtained in step 2) is transferred onto the TiS2 using a PDMS stamp-assisted dry transfer method. The area of ​​the two-dimensional material of the half-metal phase as the gate is smaller than the area of ​​the two-dimensional material of the semiconductor phase. Using the gate as a mask, the semiconductor phase two-dimensional material not covered by the gate is removed by etching technology to form a channel, so that the gate and the channel are precisely self-aligned and the channel is completely covered by the gate.

[0046] 8) Perform low-pressure thermal annealing under the same conditions as in step 4) to further remove PDMS and PMMA residues, reduce bubble density, improve contact, and complete the fabrication of a fully two-dimensional vertical structure MESFET with both nanoscale channel length and contact length.

[0047] 9) Gate control:

[0048] The gate is connected to an external control voltage source through a corresponding metal electrode; the source and drain are connected to an external constant voltage source through corresponding test electrodes.

[0049] When no gate voltage is applied, i.e., V G When V = 0, the Schottky junction formed by the half-metal-semiconductor contact is in thermal equilibrium. Its built-in barrier generates a depletion region of a certain width in the channel, which has channel carriers but a low concentration, and is in a partially pinch-off state. This is manifested by the source-drain current being at the off-state current level on the order of nanoamperes (nA). When a positive gate voltage, V = 0, is applied to the gate, the Schottky junction is in thermal equilibrium. G When the voltage is greater than 0, the depletion region narrows, the Schottky barrier decreases, the channel carrier concentration increases, and the channel is in a conducting state, manifested as a significant increase in source-drain current to the microampere (μA) level; when a negative gate voltage is applied to the gate, i.e., V0 G <

[0050] At 0, the depletion region widens, the Schottky barrier increases, and the channel carrier concentration decreases, resulting in a completely pinch-off state. This manifests as a reduction in source-drain current to an extremely low off-state current level on the order of picoamperes (pA). This allows for gate control by forming a Schottky junction between the half-metal gate and the semiconductor channel. The channel conductivity is controlled by modulating the barrier width through the gate voltage, thereby achieving the FET function.

[0051] Raman spectroscopy characterization was performed on the fully two-dimensional vertical structure MESFET prepared using the method of this embodiment. Figure 2 As shown in (a), two characteristic peaks of TiS2 were observed at the MoS2-TiS2 heterostructure: 231.5 cm⁻¹. -1 and 333.1cm -1 And two characteristic peaks of MoS2: 385.1 cm⁻¹ -1 and 405.8cm -1 Furthermore, the distance between the two peaks of MoS2 is 20.7 cm. -1 This indicates its single-layer characteristics; such as Figure 2 As shown in (b), at the FLG-hBN-FLG-hBN-MoS2 heterostructure, the values ​​at 383.8 cm⁻¹ are respectively... -1 404.1cm -1 1368.2cm -1 1584.7cm -1 and 2724.3cm -1 Raman characteristic peaks of MoS2, hBN, and FLG were observed at the location. Here, the peak position of MoS2 is slightly different from that in (a), indicating that the strain and charge transfer of MoS2 are different in the two heterostructures.

[0052] The fully two-dimensional vertical structure MESFET prepared using the method of this embodiment was characterized by AFM, such as... Figure 3 As shown, the thickness of the source FLG-lower isolation layer hBN-drain FLG-upper isolation layer hBN is 8.5 / 8.1 / 7.3 / 12.9 nm, and the thickness of the channel MoS2 is 0.8 nm, confirming that it is a single layer, and the channel length and contact length are both miniaturized to the sub-10 nm level.

[0053] Electrical tests were performed on the fully two-dimensional vertical structure MESFET prepared using the method of this embodiment. Figure 4 (a) shows the transfer characteristic curve of the device, exhibiting n-type transfer behavior, and the device can achieve a transfer rate greater than 10 ohms within an operating voltage window of only 1.4V. 6 Even 10 7 The high switching ratio indicates its excellent gate control capability; Figure 4 (b) is from Figure 4(a) The subthreshold swing, on / off ratio and threshold voltage of the device under different source and drain voltages are extracted. The subthreshold swing of the device is as low as 68mV / Dec, which is close to the thermodynamic theoretical limit. The drain-induced barrier reduction (DIBL) parameter can be calculated based on the threshold voltage. The DIBL of the device is as low as 50mV / V, indicating that it has significant immunity to short-channel effects. Figure 4 (c) shows the relationship between the subthreshold swing and the source-drain current of the device under different source-drain voltages, indicating that the subthreshold swing of the device can be kept at a low level within a current window of 4 orders of magnitude. Figure 4 (d) shows the output characteristic curve of the device, exhibiting both linear and saturation regions. It achieves an on-state current density of 194 μA / μm at a source-drain voltage of 2V, indicating good contact. These electrical test results demonstrate that the present invention can achieve extreme miniaturization of the device while maintaining good overall performance.

[0054] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

Claims

1. A method for fabricating a full two-dimensional vertical structure metal- semiconductor field effect transistor, characterized in that, The preparation method includes the following steps: 1) Provide an insulating substrate; 2) Obtain two-dimensional materials for the first electrode, lower insulating layer, second electrode, upper insulating layer, and gate from bulk layered materials; the first and second electrodes are made of few-layer semi-metallic phase two-dimensional materials, and the lower and upper insulating layers are made of few-layer insulating phase two-dimensional materials. 3) The first electrode, the lower insulating layer, the second electrode, and the upper insulating layer are stacked vertically from bottom to top on the surface of the substrate; 4) Low-pressure hot annealing treatment to obtain a four-layer vertical heterostructure; the two electrodes, which are insulated and isolated by the lower insulating layer, serve as the source and drain, respectively; 5) Ultraviolet lithography and etching processes are used to expose the inclined sidewalls of the four-layer vertical heterostructure in certain areas; 6) Obtain two-dimensional materials with few-layer or single-layer semiconductor phases; 7) Transfer the two-dimensional semiconductor phase material to the surface of a four-layer vertical heterostructure with inclined sidewalls; transfer the two-dimensional half-metal phase material as a gate onto the two-dimensional semiconductor phase material, use the gate as a mask and etch away the two-dimensional semiconductor phase material not covered by the gate to form a channel, so that the gate and the channel are precisely self-aligned and the channel is completely covered by the gate. By simultaneously reducing the thickness of the lower isolation layer as well as the source and drain electrodes, the channel length and contact length are also reduced. 8) Perform low-pressure thermal annealing to obtain a fully two-dimensional vertical structure MESFET with both nanoscale channel length and contact length; 9) The gate is connected to an external regulating voltage source; the source and drain are connected to external constant voltage sources respectively; A Schottky junction is formed by a half-metal gate and a semiconductor channel for gate control. The conductivity of the channel is controlled by modulating the barrier width through the gate voltage, thereby realizing the function of a field-effect transistor.

2. The production method according to claim 1, wherein When no gate voltage is applied, the Schottky junction formed by the half-metal-semiconductor contact is in thermal equilibrium. Its built-in barrier generates a depletion region in the channel, which has channel carriers and is in a partially pinch-off state. When a positive gate voltage is applied, the depletion region narrows, the Schottky barrier decreases, the channel carrier concentration increases, and it is in a conducting state. When a negative gate voltage is applied, the depletion region widens, the Schottky barrier increases, the channel carrier concentration decreases, and it is in a completely pinch-off state.

3. The preparation method according to claim 1, characterized in that, In step 2), two-dimensional materials are obtained from bulk layered materials by chemical vapor deposition or mechanical exfoliation; materials with thicknesses matching the design thickness are screened by optical microscopy and atomic force microscopy.

4. The preparation method according to claim 1, characterized in that, In step 4), the annealing atmosphere is argon or hydrogen, the annealing temperature is 180–300°C, and the annealing time is 1–3 hours.

5. The preparation method according to claim 1, characterized in that, In step 5), after UV lithography development, oxygen plasma is used to remove residual resist at the window position; etching is performed using reactive ion etching, inductively coupled plasma-reactive ion etching, or ion beam sputtering etching; the obtained sidewall tilt angle ranges from 30° to 90°.

6. The preparation method according to claim 1, characterized in that, In step 6), a few-layer or single-layer semiconductor phase two-dimensional material is obtained by chemical vapor deposition or mechanical exfoliation.

7. The preparation method according to claim 1, characterized in that, In step 7), a wet transfer method is used for large-area monolayer films grown by chemical vapor deposition; a dry transfer method is used for mechanically exfoliated nanosheets.

8. A fully two-dimensional vertical structure metal-semiconductor field-effect transistor, characterized in that, The field-effect transistor includes: a substrate, a source, a drain, a lower isolation layer, an upper isolation layer, a two-dimensional semiconductor channel, and a gate; wherein, the substrate is made of an insulating material; a first electrode, a lower isolation layer, a second electrode, and an upper isolation layer are vertically stacked sequentially from bottom to top on the surface of the substrate, with the two electrode layers insulated and isolated by the lower isolation layer serving as the source and drain, respectively; the source and drain are made of a few-layer half-metal phase two-dimensional material; the lower isolation layer and the upper isolation layer are made of a few-layer insulating phase two-dimensional material; the stacked region is photolithographically and etched to form inclined sidewalls; a few-layer or single-layer semiconductor phase two-dimensional material is used to cover part of the surface of the upper isolation layer and the inclined sidewalls. A channel is formed on the sidewall; a multilayer of two-dimensional half-metallic material is coated on the surface of part of the channel as a gate, the gate and the channel are self-aligned, and the channel is completely covered by the gate; a Schottky junction is formed by direct contact between the half-metallic gate and the semiconductor channel; the channel length and contact length are reduced by simultaneously reducing the thickness of the lower isolation layer and the source and drain; the gate is connected to an external control voltage source; the source and drain are respectively connected to an external constant voltage source; gate control is achieved by forming a Schottky junction between the half-metallic gate and the semiconductor channel, and the channel conductivity is controlled by modulating the barrier width through the gate voltage, thereby realizing the function of a field-effect transistor.

9. The field-effect transistor as claimed in claim 8, characterized in that, The channel is made of molybdenum sulfide, tungsten sulfide, molybdenum telluride, or tungsten selenide, with a thickness of 0.7–5 nm.

10. The field-effect transistor as claimed in claim 8, characterized in that, The gate is made of titanium disulfide or niobium disulfide, with a thickness of 50–120 nm.

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