A silicon pixel detector arrival time measurement circuit and measurement method

Abstract

This invention relates to a silicon pixel detector arrival time measurement circuit and method. The circuit includes a pulse control module, a delay chain module, a first counting module, and a second counting module. The pulse control module responds to rising edge signals from an external circuit by outputting a logic high level and a rising edge signal to the delay chain module and the first counting module, respectively; and outputs a logic low level based on the logic high level after multiple delays. The delay chain module delays the input logic high and low levels multiple times; and outputs a periodic square wave to the first counting module based on the logic levels after multiple delays. The first counting module counts the rising edges of the periodic square wave. The second counting module determines the arrival position of the rising edge of the periodic square wave based on all received logic levels. This invention decouples time measurement accuracy from clock frequency by combining pulse width control and the delay chain module, achieving high-precision time measurement at low clock frequencies.

Description

Technical Field

[0001] This invention belongs to the field of silicon pixel detector technology, specifically relating to a silicon pixel detector arrival time measurement circuit and measurement method. Background Technology

[0002] Silicon pixel detectors possess excellent position resolution and are widely used in accelerator particle physics experiments for track reconstruction. With the development of pixel detectors, they have found applications in fields such as X-ray imaging. For different applications, silicon pixel detectors require not only high position resolution but also high-precision energy and time measurements. Typically, energy measurement is achieved using time overthreshold techniques, which necessitate high-precision measurement of the arrival times of the rising and falling edges. Therefore, high-precision arrival time measurement is one of the important research directions for silicon pixel detectors.

[0003] Traditional methods for measuring the arrival time of silicon pixel detectors employ a combination of coarse and fine time-to-digital conversion (CTDC) techniques. Coarse counting uses a counter to time the system clock, while fine counting uses a ring voltage-controlled oscillator (VCO) to generate a high-frequency clock for more precise timing. The time accuracy of this method is determined by the high-frequency clock of the fine counting; the higher the frequency, the higher the accuracy. However, high clock frequencies lead to high power consumption, affecting lifespan. Furthermore, detector integration requires more cables and water-cooling systems, increasing the mass of the integrated detector and further exacerbating ion scattering problems. Summary of the Invention

[0004] To address the issues of high clock frequency and high power consumption in traditional time measurement methods without compromising time measurement accuracy, a silicon pixel detector arrival time measurement circuit is provided in a first aspect of this invention. The circuit includes a pulse control module, a delay chain module, a first counting module, and a second counting module. The pulse control module responds to rising edge signals from an external circuit by outputting a logic high level and a rising edge signal to the delay chain module and the first counting module, respectively; and outputs a logic low level based on the logic high level after multiple delays. The delay chain module delays the input logic high and low levels multiple times; and outputs a periodic square wave with a constant frequency to the first counting module based on the logic levels after multiple delays. The first counting module counts the rising edges of the periodic square wave based on the rising edge signal and the logic levels after multiple delays. The second counting module latches the delayed logic levels of the delay chain module in response to an external signal; and determines the arrival position of the rising edge of the periodic square wave based on all received logic levels.

[0005] In some embodiments of the present invention, the pulse control module includes a multiplexer, a first D flip-flop, and an inverter; the multiplexer is used to respond to the rising edge signal of an external circuit and output to the clock terminal of the first D flip-flop and the first counting module, respectively; the first D flip-flop is used to output a logic high level to the delay chain module based on the input rising edge signal; and to output a logic low level to the delay chain module based on the input signal of the inverter; the inverter is used for signal polarity reversal of the delay chain module and timing adjustment of the delay chain.

[0006] Furthermore, the inverter is used to invert the logic level after multiple delays.

[0007] In some embodiments of the present invention, the delay chain module includes 2N delay units connected in sequence, the output terminal of the Nth delay unit is connected to the input terminal of the pulse control module, and the 2Nth delay unit is connected to the first counting module, wherein N≥1.

[0008] Furthermore, the second counting module includes 2N+1 latches and a rising edge detection circuit. The 2N+1 latches are used to respond to external signals and latch the logic level of the pulse control module and the logic level of the 2N delay units. The rising edge detection circuit is used to determine the arrival position of the rising edge of the periodic square wave based on the logic level of each delay unit.

[0009] Preferably, the rising edge detection circuit includes 2N+1 second D flip-flops; the clock terminal of the first second D flip-flop receives the logic level of the pulse control module through a latch; the clock terminal and input terminal of the N+1th second D flip-flop respectively receive the logic level of the Nth delay unit and the inverted logic level of the N+1th delay unit.

[0010] A second aspect of the present invention provides a measurement method for the silicon pixel detector arrival time measurement circuit provided in the first aspect, comprising: a pulse control module responding to a rising edge signal from an external circuit, outputting a logic high level and a rising edge signal to a delay chain module and a first counting module, respectively; outputting a logic low level based on a logic high level after multiple delays; the delay chain module delaying the input logic high level and logic low level multiple times; outputting a periodic square wave with a constant frequency to the first counting module based on the logic level after multiple delays; the first counting module counting the rising edges of the periodic square wave based on the rising edge signal and the logic level after multiple delays; a second counting module responding to an external signal, latching each delayed logic level of the delay chain module; and determining the arrival position of the rising edge of the periodic square wave based on all received logic levels.

[0011] A third aspect of the present invention provides an electronic device comprising: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the measurement method of the silicon pixel detector arrival time measurement circuit provided in the second aspect of the present invention.

[0012] In a fourth aspect, the present invention provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the measurement method of the silicon pixel detector arrival time measurement circuit provided in the second aspect of the present invention.

[0013] The beneficial effects of this invention are: This invention employs a combination of pulse width control and delay chain module technology, eliminating the relationship between time measurement accuracy and clock frequency. It also solves the problem that traditional delay chain modules cause the signal pulse width to expand or contract after multiple cycles, enabling high-precision time measurement even at low clock frequencies, thereby achieving low power consumption without affecting time measurement accuracy. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the basic structure of the silicon pixel detector arrival time measurement circuit in some embodiments of the present invention; Figure 2 This is a schematic diagram of the rising edge detection circuit in some embodiments of the present invention; Figure 3 This is a schematic diagram of the measurement method of the silicon pixel detector arrival time measurement circuit in some embodiments of the present invention; Figure 4 This is a schematic diagram of the structure of an electronic device in some embodiments of the present invention. Detailed Implementation

[0015] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0016] refer to Figure 1 and Figure 2In a first aspect of the present invention, a silicon pixel detector arrival time measurement circuit is provided, comprising a pulse control module, a delay chain module, a first counting module, and a second counting module. The pulse control module is configured to respond to a rising edge signal from an external circuit by outputting a logic high level and a rising edge signal to the delay chain module and the first counting module, respectively; and output a logic low level based on a logic high level after multiple delays. The delay chain module is configured to delay the input logic high level and logic low level multiple times; and output a periodic square wave with a constant frequency to the first counting module based on the logic level after multiple delays. The first counting module is configured to count the rising edges of the periodic square wave based on the rising edge signal and the logic level after multiple delays. The second counting module is configured to respond to an external signal by latching each delayed logic level of the delay chain module; and determine the arrival position of the rising edge of the periodic square wave based on all received logic levels.

[0017] Specifically, the arrival time measurement circuit of the silicon pixel detector includes pulse width control (module), delay chain, coarse counting (first counting module), and fine counting (second counting module). The digital pulse signal undergoes preprocessing before entering the arrival time measurement circuit, extracting its rising edge as the Start signal. Its working principle is as follows: Before the Start signal enters the arrival time measurement circuit, all delay units are in the initial state (S0~S1). n (When the level is low, the D flip-flop is in the ready-to-trigger state). When the selector MUX receives the Start signal, it will automatically select the other end after a delay of one delay unit, connecting it to the output of the last delay unit in the delay chain. At this point, the delay chain is closed, forming a closed loop.

[0018] The Start signal generates a high-level signal in the delay chain through a D flip-flop and is transmitted. When the high level reaches S... N / 2 During transmission, a feedback loop is sent to the reset pin of the D flip-flop, resetting it and changing S0 from high to low to continue transmission until a low level is reached at S0. N / 2 The D flip-flop then returns to its ready-to-trigger state. This process converts the Start signal into a periodic square wave with a constant frequency. The period is equal to the total delay of the delay chain. The longer the total delay of the delay chain, the longer the period, and the lower the power consumption of the circuit. The counter toggles once every time the rising edge of the square wave passes the end of the delay chain, completing the coarse counting.

[0019] It can be understood that the top signal is generated by an external timing circuit and synchronized with its clock. When the Stop signal arrives, the D flip-flops mounted below the delay units immediately lock the state of each delay unit and send the data to the rising edge detection circuit to complete fine counting. Subsequently, the delay chain is reset, and the entire measurement process ends. By combining coarse and fine counting, the arrival time measurement circuit achieves high-precision measurement of the arrival time of the rising edge of Start.

[0020] For example, the delay unit includes an FPGA-based internal delay chain unit, a clock phase interpolation unit, an application-specific integrated circuit (ASIC) delay unit, or a digital logic gate delay unit; the delay chain is constructed using the inherent propagation delay of digital logic gates (such as inverters and buffers), and its resolution is close to the delay of a single gate circuit (about 0.5ns). Accuracy needs to be improved by cascading or calibration.

[0021] In some embodiments of the present invention, the pulse control module includes a multiplexer, a first D flip-flop, and an inverter; the multiplexer is used to respond to the rising edge signal of an external circuit and output to the clock terminal of the first D flip-flop and the first counting module, respectively; the first D flip-flop is used to output a logic high level to the delay chain module based on the input rising edge signal; and to output a logic low level to the delay chain module based on the input signal of the inverter; the inverter is used for signal polarity reversal of the delay chain module and timing adjustment of the delay chain.

[0022] Specifically, the pulse width control module consists of a MUX, a D flip-flop, and an inverter, and is used to control the cyclic pulse width. It controls the pulse width and eliminates the problem that the pulse width will expand or contract after the pulse has been cycled multiple times in the delay chain.

[0023] In some embodiments of the present invention, the delay chain module includes 2N delay units connected in sequence, the output terminal of the Nth delay unit is connected to the input terminal of the pulse control module, and the 2Nth delay unit is connected to the first counting module, wherein N≥1.

[0024] Furthermore, the second counting module includes 2N+1 latches and a rising edge detection circuit. The 2N+1 latches are used to respond to external signals and latch the logic level of the pulse control module and the logic level of the 2N delay units. The rising edge detection circuit is used to determine the arrival position of the rising edge of the periodic square wave based on the logic level of each delay unit.

[0025] Preferably, the rising edge detection circuit includes 2N+1 second D flip-flops; the clock terminal of the first second D flip-flop receives the logic level of the pulse control module through a latch; the clock terminal and input terminal of the N+1th second D flip-flop respectively receive the logic level of the Nth delay unit and the inverted logic level of the N+1th delay unit.

[0026] Specifically, the fine counter (second counting module) consists of a D flip-flop and a rising edge detection circuit. The D flip-flop latches the output data of each delay unit in the delay chain, and the rising edge detection circuit is used to solve the problem that multiple D flip-flops output high levels at the same time, making it impossible to directly determine which delay unit the rising edge of the Start signal is transmitted to.

[0027] It is understood that the rising edge detection circuit used in this invention can directly indicate which delay unit the rising edge of the Start signal will propagate to. The rising edge detection circuit is as follows: Figure 2 As shown (taking a delay chain consisting of 4 delay units as an example), it is composed of multiple D flip-flops and inverters. An inverter is connected to the input of the D flip-flops to form a rising edge discrimination circuit. Connecting adjacent signals (e.g., Q1-Q0) from the fine count to the clock port and input port of the discrimination circuit respectively achieves the discrimination output. The output waveform clearly shows the specific location of the signal delay, such as... Figure 2 The display shows that the signal delay has reached the second delay unit (Q_S2), thus realizing fine counting measurement of the signal delay.

[0028] Example 2 refer to Figure 3 A second aspect of the present invention provides a measurement method for the silicon pixel detector arrival time measurement circuit provided in the first aspect, comprising: S100. The pulse control module responds to the rising edge signal from the external circuit and outputs a logic high level and a rising edge signal to the delay chain module and the first counting module, respectively; based on the logic high level after multiple delays, it outputs a logic low level; S200. The delay chain module delays the input logic high level and logic low level multiple times; based on the logic level after multiple delays, it outputs a periodic square wave with a constant frequency to the first counting module; S300. The first counting module counts the rising edges of the periodic square wave based on the rising edge signal and the logic level after multiple delays; S400. The second counting module responds to the external signal and latches the logic level of each delay from the delay chain module; based on all received logic levels, it determines the arrival position of the rising edge of the periodic square wave.

[0029] Furthermore, in step S100, the step of outputting a logic low level based on a logic high level after multiple delays includes: resetting the logic high level after the second delay and outputting a logic low level.

[0030] Example 3 refer to Figure 4 A third aspect of the present invention provides an electronic device comprising: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method of the second aspect of the present invention.

[0031] Electronic device 500 may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 501, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 502 or a program loaded from storage device 508 into random access memory (RAM) 503. The RAM 503 also stores various programs and data required for the operation of electronic device 500. The processing unit 501, ROM 502, and RAM 503 are interconnected via bus 504. An input / output (I / O) interface 505 is also connected to bus 504.

[0032] Typically, the following devices can be connected to I / O interface 505: input devices 506 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 507 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 508 including, for example, hard disks; and communication devices 509. Communication device 509 allows electronic device 500 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 4 An electronic device 500 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively. Figure 4 Each box shown can represent a device or multiple devices as needed.

[0033] Specifically, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 509, or installed from a storage device 508, or installed from a ROM 502. When the computer program is executed by a processing device 501, it performs the functions defined in the methods of embodiments of this disclosure. It should be noted that the computer-readable medium described in embodiments of this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In embodiments of this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In embodiments of this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0034] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device. The aforementioned computer-readable medium carries one or more computer programs, which, when executed by the electronic device, cause the electronic device to: Computer program code for performing the operations of embodiments of this disclosure can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages—such as Java, Smalltalk, C++, and Python—and conventional procedural programming languages—such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0035] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0036] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A silicon pixel detector arrival time measurement circuit, comprising a pulse control module, a delay chain module, a first counting module, and a second counting module, characterized in that, The pulse control module is used to respond to the rising edge signal of the external circuit, and output logic high level and rising edge signal to the delay chain module and the first counting module respectively; based on the logic high level after multiple delays, it outputs logic low level. The delay chain module is used to delay the input logic high level and logic low level multiple times; based on the logic level after multiple delays, it outputs a periodic square wave with a constant frequency to the first counting module; the delay chain module includes 2N delay units connected in sequence, the output terminal of the Nth delay unit is connected to the input terminal of the pulse control module, and the 2Nth delay unit is connected to the first counting module, where N≥1; The first counting module is used to count the rising edges of the periodic square wave based on the rising edge signal and the logic level after multiple delays. The second counting module is used to respond to external signals and latch the delay logic level of each delay in the delay chain module; based on all received logic levels, it determines the arrival position of the rising edge of the periodic square wave; the second counting module includes 2N+1 latches and a rising edge detection circuit. The 2N+1 latches are used to respond to external signals and latch the logic level of the pulse control module and the logic level of the 2N delay units. The rising edge detection circuit is used to determine the arrival position of the rising edge of the periodic square wave based on the logic level of each delay unit; the rising edge detection circuit includes 2N+1 second D flip-flops. The clock input of the first second D flip-flop receives the logic level of the pulse control module through a latch; the clock input and input of the (N+1)th second D flip-flop receive the logic level of the Nth delay unit and the inverted logic level of the (N+1)th delay unit, respectively.

2. The silicon pixel detector time-of-arrival measurement circuit of claim 1, wherein, The pulse control module includes a multiplexer, a first D flip-flop, and an inverter; The multiplexer is used to respond to the rising edge signal of the external circuit and output to the clock terminal of the first D flip-flop and the first counting module respectively. The first D flip-flop is used to output a logic high level to the delay chain module based on the rising edge signal of the input; and to output a logic low level to the delay chain module based on the input signal of the inverter. The inverter is used for signal polarity reversal and timing adjustment of the delay chain module.

3. The silicon pixel detector time-of-arrival measurement circuit of claim 2, wherein, The inverter is used to invert the logic level after multiple delays.

4. A measurement method based on the silicon pixel detector arrival time measurement circuit of claim 1, characterized in that, include: The pulse control module responds to the rising edge signal of the external circuit and outputs a logic high level and a rising edge signal to the delay chain module and the first counting module, respectively; Based on a logic high level after multiple delays, output a logic low level; The delay chain module delays the input logic high and logic low levels multiple times; based on the logic levels after multiple delays, it outputs a periodic square wave with a constant frequency to the first counting module. The first counting module counts the rising edges of the periodic square wave based on the rising edge signal and the logic level after multiple delays. The second counting module responds to external signals and latches the delay logic level of each delay in the delay chain module; based on all received logic levels, it determines the arrival position of the rising edge of the periodic square wave.

5. The measurement method of the silicon pixel detector arrival time measurement circuit according to claim 4, characterized in that, The output logic low level based on the logic high level after multiple delays includes: The logic high level after multiple delays is reset, and a logic low level is output.

6. An electronic device, comprising: One or more processors; A storage device for storing one or more programs that, when executed by one or more processors, cause the one or more processors to implement the measurement method of the silicon pixel detector arrival time measurement circuit as described in any one of claims 4 to 5.

7. A computer-readable medium having a computer program stored thereon, wherein, When the computer program is executed by the processor, it implements the measurement method of the silicon pixel detector arrival time measurement circuit as described in any one of claims 4 to 5.

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