A total dose radiation resistant bandgap voltage reference source circuit

Abstract

The application relates to the field of anti-radiation reinforcement technology in integrated circuits, in particular to a band gap voltage reference source circuit resisting total dose radiation, which comprises a starting circuit, a biasing circuit and a reference core circuit. The starting circuit is used for helping the circuit to get rid of abnormal degenerate points and quickly enter a normal working state at the initial stage of power-on of the circuit; the biasing circuit is connected with the starting circuit and is used for providing a biasing signal for the reference core circuit; the reference core circuit is connected with the biasing circuit and is used for outputting a high-precision reference voltage; a base current compensation circuit is connected with the reference core circuit and the biasing circuit and is used for reducing the influence of the base current change of a bipolar transistor after radiation on the output of the reference core circuit; and the band gap voltage reference source circuit output is compensated and corrected by the base current compensation circuit.

Description

Technical Field

[0001] This invention relates to the field of radiation hardening technology in integrated circuits, and specifically to a bandgap voltage reference source circuit resistant to total dose radiation. Background Technology

[0002] Bandgap reference voltage source circuits have been widely used in analog and mixed signal systems due to their excellent robustness to power supply voltage fluctuations, process parameter deviations and ambient temperature changes. Typical applications include DC / DC converters, low dropout linear regulators (LDOs), analog-to-digital / digital-to-analog converters (ADCs / DACs) and various sensor interface circuits.

[0003] In aerospace and satellite electronic systems, integrated circuits must withstand complex radiation environments, among which total irradiation dose (TID) is one of the most representative radiation damage mechanisms. As semiconductor processes evolve towards submicron BCD (Bipolar-CMOS-DMOS) technology nodes (typical feature sizes ≤180nm), significant changes have occurred in device structure: on the one hand, the gate oxide layer thickness continues to decrease; on the other hand, traditional SiO2 gate dielectrics are gradually being replaced by high-k materials. These technological advancements have substantially improved the intrinsic resistance to total irradiation of MOS devices, and their reliability can be further enhanced through optimized layout design (such as employing radiation-hardened layout techniques).

[0004] However, under total dose irradiation, the performance of conventional bipolar junction transistors (BJTs) exhibits significant degradation. The long-term cumulative irradiation effect is mainly manifested in: enhanced base carrier recombination leading to an abnormally large increase in base current (I_B), and a continuous decay in the common-emitter current gain (β). This degradation directly affects the core performance parameters of the bandgap reference source, specifically manifested as a decrease in the long-term stability of the reference voltage and a shift in the temperature characteristic curve, ultimately reducing the reliability of the entire circuit system. Summary of the Invention

[0005] This invention addresses the issues of output center value drift and temperature drift degradation in normal bandgap voltage reference source circuits under total dose irradiation. It proposes a bandgap voltage reference source circuit resistant to total dose irradiation, comprising a startup circuit, a reference core circuit, a bias circuit, and a base current compensation circuit, wherein:

[0006] The startup circuit is used to help the circuit get out of the abnormal degeneracy point and quickly enter the normal working state in the initial stage of power-on.

[0007] The bias circuit is connected to the startup circuit and is used to provide a bias signal to the reference core circuit;

[0008] The reference core circuit is connected to the bias circuit to output a high-precision reference voltage;

[0009] The base current compensation circuit is connected to the reference core circuit and the bias circuit to reduce the impact of base current changes after bipolar transistor irradiation on the output of the reference core circuit.

[0010] The beneficial effects of this invention are:

[0011] This invention compensates and corrects the output of the bandgap voltage reference source circuit by using a base current compensation circuit. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a normal bandgap voltage reference source circuit;

[0013] Figure 2 Simulation results of the output accuracy and temperature coefficient of a normal reference source under total dose irradiation;

[0014] Figure 3 This is a schematic diagram of a bandgap voltage reference source circuit resistant to total dose irradiation according to the present invention;

[0015] Figure 4 The simulation results show the output accuracy and temperature coefficient of the radiation-resistant reference source under total dose irradiation according to this invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] Typically, the core of a voltage-mode bandgap voltage reference circuit can be divided into a startup circuit, a reference core circuit, and a bias circuit. These three components have clearly defined functions, including:

[0018] The main function of the startup circuit is to force the system to leave the zero-current degenerate state in the early stage of power-up and guide it into the normal bias operating point. At the same time, it ensures that the startup circuit automatically shuts down after the reference core circuit enters a stable state, so as not to affect the subsequent normal operation.

[0019] The reference core circuit is the "heart" of the bandgap reference source. Its essence is to use two "voltages with opposite temperature coefficients" for compensation, and finally output a reference voltage with "zero temperature coefficient (or extremely low temperature coefficient)".

[0020] The bias circuit provides a stable bias current to the reference core circuit, ensuring that its operating point is not affected by process fluctuations and temperature changes. It is usually implemented using a current mirror or bandgap bias technology.

[0021] Figure 1 A typical voltage-mode bandgap reference source circuit is shown, including a startup circuit 001, a reference core circuit 002, and a bias circuit 003. The circuit design aims to ensure that the system can quickly and reliably enter a stable operating state after power-on, avoiding falling into an abnormal degenerate operating point due to initial condition mismatch.

[0022] The startup circuit consists of transistors Q1, M1~M2, and resistor R1. The processing flow can be divided into the following stages:

[0023] Initial state (abnormal degeneracy point): At the instant of power-on, without intervention from the startup circuit, the reference core circuit and bias circuit may enter a zero-current operating state (I=0) due to initial condition mismatch, i.e. Figure 1 The voltage at points A and C is 0V, while the voltage at point B is equal to the power supply voltage (VDD). At this time, the reference core circuit cannot start automatically, causing the output reference voltage to fail.

[0024] Startup process: The startup circuit turns on the startup transistor M2, pulling down the voltage at point B, thereby turning on the cascode current mirror (composed of transistors M3 and M5). Subsequently, transistors M4 and M6 mirror the current, gradually raising the potential at point C, and then turning on transistors M7 and M8 to provide the initial bias current for the reference core circuit.

[0025] Transistor activation: At the same time, the voltage at point A is pulled high by M2, causing transistors Q2~Q5 to conduct, further pushing the circuit away from the abnormal degeneracy point and into normal working state.

[0026] Startup complete: When the voltage at point A rises to the reference voltage (VREF), the starter transistor M2 automatically turns off, the starter circuit stops working, the reference circuit enters a stable operating mode, and the power-on start-up process is completed.

[0027] The reference core circuit 002 uses transistors (Q3 / Q4) with a 1:8 ratio as the reference core. Transistors M3-M6 form a cascode current mirror structure to provide highly stable bias current to the reference core transistors. Transistors M7 and M8 clamp the collector voltages of transistors Q2 and Q5 to prevent the Earliest effect from affecting the bandgap reference output. Positive temperature coefficient voltage ΔV be A PTAT current I is generated across resistor R6. PTAT Its expression is as follows:

[0028] (1)

[0029] Where k is the Boltzmann constant, and the positive temperature coefficient voltage ΔV is... be This is the emitter junction voltage difference between transistors Q3 and Q4, where T represents the operating temperature. From equation (1), it can be seen that R6 determines the magnitude of the PTAT current. The PTAT current generates a positive temperature coefficient voltage drop across resistors R3~R5. Simultaneously, the emitter junction voltage V of transistor Q3... be3 The two are negative temperature coefficient voltages; their superposition yields a zero temperature coefficient reference voltage, V. BGR As shown in the formula below:

[0030] (2)

[0031] The first-order temperature compensation condition is given by the following formula:

[0032] (3)

[0033] By adjusting the ratio of R4, R3, and R6 to satisfy the above formula, the low-temperature drift bandgap reference output can be obtained.

[0034] In aerospace applications, bandgap voltage reference circuits, in addition to having a low temperature drift coefficient, also need to be resistant to ionizing radiation. Under total dose irradiation, the performance of bipolar transistors degrades, leading to increased base current and decreased current gain, thus affecting the reference output performance. When the increase in base current of Q2 and Q3 after total dose irradiation is not negligible, the reference voltage output is corrected using the following formula:

[0035] (4)

[0036] Among them, I b This represents the base currents of Q2 and Q3.

[0037] As can be seen from equation (4), the base current will gradually increase due to the total dose irradiation effect, and the reference output center value will also increase accordingly. Furthermore, the temperature characteristics of the base current introduced will cause the reference output temperature drift performance to deteriorate. Figure 2 The results show the changes in the reference output and temperature coefficient under total dose irradiation. Under total dose irradiation, when the current gain of the bipolar transistor drops to a maximum of 20%, the maximum change in the reference output is 22.18 mV, and the maximum change in the temperature coefficient is 164 ppm / ℃, which is 38.5 times the original value.

[0038] To address the impact of total dose irradiation on bandgap voltage reference circuits, traditional solutions primarily involve two approaches: The first is to develop radiation-resistant dedicated process lines specifically optimized for the irradiation effects on devices, minimizing changes in the current gain of bipolar transistors (BPTs) under irradiation conditions. However, developing custom processes is time-consuming, requires significant investment, and is extremely challenging. The second approach involves biasing the BPTs at a higher current, where the current gain is less affected by irradiation. However, biasing the BPTs at a higher current deviates from the optimal operating region for the device, resulting in higher system power consumption. Therefore, traditional methods for addressing the impact of total dose irradiation on bandgap voltage references have limitations.

[0039] Therefore, this invention discloses a bandgap voltage reference source circuit resistant to total dose radiation. It employs base current compensation technology to reduce the impact of bipolar transistor base current changes on the reference output after irradiation. The bandgap voltage reference source circuit is hardened to resist total dose radiation at the circuit level. This technology can be used in the field of radiation hardening technology in analog integrated circuits.

[0040] Figure 3 This is a schematic diagram of a bandgap voltage reference source circuit resistant to total dose radiation, as shown in some embodiments of the present invention.

[0041] In some embodiments, the present invention provides a bandgap voltage reference source circuit resistant to total dose radiation, such as... Figure 3 As shown, it includes: a startup circuit, a reference core circuit, a bias circuit, and a base current compensation circuit, wherein:

[0042] The startup circuit is used to help the circuit get out of the abnormal degeneracy point and quickly enter the normal working state in the initial stage of power-on.

[0043] The bias circuit is connected to the startup circuit and is used to provide a bias signal to the reference core circuit;

[0044] The reference core circuit is connected to the bias circuit to output a high-precision reference voltage;

[0045] The base current compensation circuit is connected to the reference core circuit and the bias circuit to reduce the impact of base current changes after bipolar transistor irradiation on the output of the reference core circuit.

[0046] Specifically, the base current compensation circuit includes transistors M10~M23, transistors Q6~Q7, resistors R7~R8, and capacitor C2, wherein:

[0047] The sources of transistors M10, M15, M17, and M19 are connected to the power supply voltage VDD; the gates of transistors M10, M11, M15, and M16 are connected to the bias circuit; the drain of transistor M10 is connected to the source of transistor M11; the drain of transistor M15 is connected to the source of transistor M16; the drain of transistor M11 is connected to the gate and drain of transistor M12, and the gate of transistor M13; the drain of transistor M13 is connected to the source of transistor M14; the gate of transistor M14 is connected to the drain of transistor M16; the drain of transistor M14 is connected to the drain of transistor M18; the sources of transistors M12, M13, M21, and M22 are grounded.

[0048] The gate of transistor M17 is connected to the gate of transistor M19, and the drain of transistor M17 is connected to the source of transistor M18. The gate and drain of transistor M17 are connected together. The gate of transistor M18 is connected to the gate of transistor M20, and the gate and drain of transistor M18 are connected together. The drain of transistor M19 is connected to the source of transistor M20, and the drain of transistor M20 is connected to the drain of transistor M21. The gate of transistor M21 is connected to its own drain and the gate of transistor M22.

[0049] The drain of transistor M22 is connected to the emitter of transistor Q7; the base of transistor Q7 is connected to one end of capacitor C2 and one end of resistor R7; the collector of transistor Q7 is connected to the source of transistor M23; the other end of capacitor C2 is grounded, and the other end of resistor R7 is connected to the reference core circuit and the bias circuit; the gate of transistor M23 is connected to the bias circuit, the drain of transistor M23 is connected to one end of resistor R8, and the other end of resistor R8 is connected to the power supply voltage VDD; the emitter of transistor Q6 is grounded, the base of transistor Q6 is connected to the drain of transistor M13, and the collector of transistor Q6 is connected to the gate of transistor M14.

[0050] The reference voltage is drawn from the base of transistor Q7.

[0051] Specifically, the bias circuit includes transistors M3~M9 and resistor R2, wherein:

[0052] The sources of transistors M3 and M4 are connected to the power supply voltage VDD; the gate of transistor M3 is connected to the gate of transistor M4, the drain of transistor M3 is connected to the source of transistor M5, and the gate and drain of transistor M3 are connected; the gate of transistor M5 is connected to the gate of transistor M6; the drain of transistor M5 is connected to the startup circuit and the drain of transistor M7, and this connection point is denoted as point B; the gate and drain of transistor M5 are connected.

[0053] The gate of transistor M4 is also connected to the gate of transistor M10 and the gate of transistor M15, and the drain of transistor M4 is connected to the source of transistor M6; the gate of transistor M6 is also connected to the gate of transistor M11 and the gate of transistor M16, and the drain of transistor M6 is connected to the drain of transistor M8 and the gate of transistor M9.

[0054] The source of transistor M7 is connected to the reference core circuit, and the gate of transistor M7 is connected to the gate of transistor M8, the gate of transistor M9, and the base current compensation circuit.

[0055] The gates of transistors M8 and M9 are also connected to the gate of transistor M23, and this connection point is denoted as point C. The source of transistor M8 is connected to the reference core circuit, and the source of transistor M9 is connected to the startup circuit and resistor R7. The drain of transistor M9 is connected to one end of resistor R2, and the other end of resistor R2 is connected to the power supply voltage VDD.

[0056] Specifically, the startup circuit includes transistors Q1, M1~M2, and resistor R1, wherein:

[0057] One end of resistor R1 is connected to the power supply voltage VDD; the other end of resistor R1 is connected to the drain and gate of transistor M1, and the gate of transistor M2; the source of transistor M1 is connected to the collector and base of transistor Q1, and the emitter of transistor Q1 is grounded; the drain of transistor M2 is connected to the drain of transistor M5, and the source of transistor M2 is connected to the source of transistor M9.

[0058] Specifically, the reference core circuit includes transistors Q2~Q5, resistors R3~R6, and capacitor C1, wherein:

[0059] The emitter of transistor Q2 is grounded, the base of transistor Q2 is connected to the base of transistor Q3, and the collector of transistor Q2 is connected to the emitter of transistor M7.

[0060] The emitter of transistor Q3 is grounded. The collector of transistor Q3 is connected to the base of transistor Q4 and one end of resistor R6. The other end of resistor R6 is connected to one end of resistor R4 and the base of transistor Q3. The other end of resistor R4 is connected to one end of resistor R3 and one end of resistor R5. The other end of resistor R3 is connected to the emitter of transistor M9, and the connection point is denoted as point A. The other end of resistor R5 is connected to the collector of transistor Q4. The emitter of transistor Q4 is grounded.

[0061] The emitter of transistor Q5 is grounded, the base of transistor Q5 is connected to the collector of transistor Q4, and the collector of transistor Q5 is connected to the emitter of transistor M8; one end of capacitor C1 is connected to the base of transistor Q5, and the other end of capacitor C1 is connected to the base of transistor M8.

[0062] Specifically, base current compensation technology is used in the base current compensation circuit 004 to reduce the impact of base current changes after bipolar transistor irradiation on the reference output. For example... Figure 3 As shown, the currents in M3 and M5 are equal to the collector current I of Q2. c2 The current I of M13 can be controlled by the mirror current of M10~M13. M13 equals I c2 Simultaneously, M15 and M16 mirror the currents of M3 and M5, making the collector current of Q6 equal to the collector current of Q2, and ensuring that the base currents of Q6 and Q2 are equal, both being I. b From this, the current I of M17 and M18 can be obtained. com As shown in the following formula:

[0063]

[0064] Among them, I e2 The emitter current of Q2 is such that the current mirrored by transistors M19 to M22 makes the emitter current of Q7 equal to the current I. com That is, the emitter current of Q7 is equal to the emitter current of Q2. Therefore, the base current of Q7 is equal to the base currents I of Q2 and Q3. b Through current I b The bandgap reference output is compensated by flowing through R7, and the compensated reference output is as follows:

[0065] (6)

[0066] As can be seen from the formula, satisfying the following equation (7) can compensate for the influence of total dose irradiation on the bandgap reference output.

[0067] (7)

[0068] The revised bandgap reference output is given by the following formula:

[0069] (8)

[0070] As can be seen from equation (8), after the base current compensation circuit is used to correct the reference output, the performance degradation of the bipolar transistor under total dose irradiation will greatly reduce the impact on the reference output, thus improving the anti-total dose performance of the bandgap voltage reference source circuit.

[0071] Figure 4 The simulation results of the output accuracy and temperature coefficient of the radiation-resistant reference source under total dose irradiation are shown. Under total dose irradiation, when the current gain of the bipolar transistor drops to a maximum of 20%, the maximum change in the reference output is only 1.78mV, and the maximum change in the temperature coefficient is 3.17ppm / ℃. Compared with the original bandgap voltage reference source circuit, the circuit's resistance to total dose is greatly improved.

[0072] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "setting," "connection," "fixing," "rotation," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Unless otherwise explicitly limited, those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0073] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A bandgap voltage reference source circuit resistant to total dose radiation, characterized in that, It includes a startup circuit, a reference core circuit, a bias circuit, and a base current compensation circuit, wherein: The startup circuit is used to help the circuit get out of the abnormal degeneracy point and quickly enter the normal working state in the initial stage of power-on. The bias circuit is connected to the startup circuit and is used to provide a bias signal to the reference core circuit; The reference core circuit is connected to the bias circuit to output a high-precision reference voltage; The base current compensation circuit is connected to the reference core circuit and the bias circuit to reduce the impact of base current changes after bipolar transistor irradiation on the output of the reference core circuit. The base current compensation circuit includes transistors M10~M23, transistors Q6~Q7, resistors R7~R8, and capacitor C2, wherein: The sources of transistors M10, M15, M17, and M19 are connected to the power supply voltage VDD; the gates of transistors M10, M11, M15, and M16 are connected to the bias circuit; the drain of transistor M10 is connected to the source of transistor M11; the drain of transistor M15 is connected to the source of transistor M16; the drain of transistor M11 is connected to the gate and drain of transistor M12, and the gate of transistor M13; the drain of transistor M13 is connected to the source of transistor M14; the gate of transistor M14 is connected to the drain of transistor M16; the drain of transistor M14 is connected to the drain of transistor M18; the sources of transistors M12, M13, M21, and M22 are grounded. The gate of transistor M17 is connected to the gate of transistor M19, and the drain of transistor M17 is connected to the source of transistor M18. The gate and drain of transistor M17 are connected together. The gate of transistor M18 is connected to the gate of transistor M20, and the gate and drain of transistor M18 are connected together. The drain of transistor M19 is connected to the source of transistor M20, and the drain of transistor M20 is connected to the drain of transistor M21. The gate of transistor M21 is connected to its own drain and the gate of transistor M22. The drain of transistor M22 is connected to the emitter of transistor Q7; the base of transistor Q7 is connected to one end of capacitor C2 and one end of resistor R7; the collector of transistor Q7 is connected to the source of transistor M23; the other end of capacitor C2 is grounded, and the other end of resistor R7 is connected to the reference core circuit and the bias circuit; the gate of transistor M23 is connected to the bias circuit, the drain of transistor M23 is connected to one end of resistor R8, and the other end of resistor R8 is connected to the power supply voltage VDD; the emitter of transistor Q6 is grounded, the base of transistor Q6 is connected to the drain of transistor M13, and the collector of transistor Q6 is connected to the gate of transistor M14. The reference voltage is drawn from the base of transistor Q7; The bias circuit includes transistors M3~M9 and resistor R2, wherein: The sources of transistors M3 and M4 are connected to the power supply voltage VDD; the gate of transistor M3 is connected to the gate of transistor M4, the drain of transistor M3 is connected to the source of transistor M5, and the gate and drain of transistor M3 are connected; the gate of transistor M5 is connected to the gate of transistor M6; the drain of transistor M5 is connected to the startup circuit and the drain of transistor M7; the gate and drain of transistor M5 are connected. The gate of transistor M4 is also connected to the gate of transistor M10 and the gate of transistor M15, and the drain of transistor M4 is connected to the source of transistor M6; the gate of transistor M6 is also connected to the gate of transistor M11 and the gate of transistor M16, and the drain of transistor M6 is connected to the drain of transistor M8 and the gate of transistor M9. The source of transistor M7 is connected to the reference core circuit, and the gate of transistor M7 is connected to the gate of transistor M8, the gate of transistor M9, and the base current compensation circuit. The gates of transistors M8 and M9 are also connected to the gate of transistor M23; the source of transistor M8 is connected to the reference core circuit, and the source of transistor M9 is connected to the startup circuit and resistor R7; the drain of transistor M9 is connected to one end of resistor R2, and the other end of resistor R2 is connected to the power supply voltage VDD. The reference core circuit includes transistors Q2~Q5, resistors R3~R6, and capacitor C1, wherein: The emitter of transistor Q2 is grounded, the base of transistor Q2 is connected to the base of transistor Q3, and the collector of transistor Q2 is connected to the emitter of transistor M7. The emitter of transistor Q3 is grounded; the collector of transistor Q3 is connected to the base of transistor Q4 and one end of resistor R6; the other end of resistor R6 is connected to one end of resistor R4 and the base of transistor Q3; the other end of resistor R4 is connected to one end of resistor R3 and one end of resistor R5; the other end of resistor R3 is connected to the emitter of transistor M9; the other end of resistor R5 is connected to the collector of transistor Q4; the emitter of transistor Q4 is grounded. The emitter of transistor Q5 is grounded, the base of transistor Q5 is connected to the collector of transistor Q4, and the collector of transistor Q5 is connected to the source of transistor M8; one end of capacitor C1 is connected to the base of transistor Q5, and the other end of capacitor C1 is connected to the base of transistor M8.

2. The bandgap voltage reference source circuit resistant to total dose radiation according to claim 1, characterized in that, The startup circuit includes transistors Q1, M1~M2, and resistor R1, wherein: One end of resistor R1 is connected to the power supply voltage VDD; the other end of resistor R1 is connected to the drain and gate of transistor M1, and the gate of transistor M2; the source of transistor M1 is connected to the collector and base of transistor Q1, and the emitter of transistor Q1 is grounded; the drain of transistor M2 is connected to the drain of transistor M5, and the source of transistor M2 is connected to the source of transistor M9.

3. The bandgap voltage reference source circuit resistant to total dose irradiation according to claim 1, characterized in that, Resistors R3, R4, and R7 satisfy the following relationship: 。 4. The bandgap voltage reference source circuit resistant to total dose radiation according to claim 1, characterized in that, The reference voltage V output by the reference core circuit BGR Represented as: ， Where k is the Boltzmann constant, T is the operating temperature, and V is the operating temperature. be3 It is a voltage with a negative temperature coefficient.

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