基于静态随机存取存储器的时序优化装置及方法
By introducing a data bit memory and a parity bit buffer memory into the static random access memory, the timing decoupling of the encoding/decoding logic from the write path is achieved, which solves the timing burden problem of the error correction code and parity check code logic on the write path and improves the timing convergence and operational stability of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING TSINGMICRO INTELLIGENT TECH CO LTD
- Filing Date
- 2025-11-20
- Publication Date
- 2026-07-17
AI Technical Summary
During the writing process of single-port SRAM and dual-port SRAM, the error correction code and parity check code encoding logic increases the timing convergence difficulty of the critical path, resulting in increased write latency and affecting the performance of high-performance computing systems.
By introducing a data bit memory and a parity bit buffer memory into the static random access memory, the timing of the encoding and decoding logic and the write path is decoupled, avoiding the impact of encoding logic delay on the write path. An independent parity bit buffer storage mechanism and refresh mechanism are adopted to ensure that the parity bit is written to the memory at the appropriate time.
It significantly reduces the critical latency of the write path, improves the timing convergence and operational stability of the system, and ensures the reliability of data processing and timing performance under high-frequency operating conditions.
Smart Images
Figure CN121166041B_ABST