An on-orbit high-reliability fault-tolerant high-speed data processing implementation method

Abstract

This invention belongs to the field of satellite on-orbit operational data technology, and discloses an on-orbit high-reliability, fault-tolerant, high-speed data processing implementation method. High-speed data is input to the satellite's high-speed payload. The high-speed interface SerDes and PICE logic core receive the high-speed data and send it to the AXI bus module. After passing through the frame processing module, flow control module, and encoding verification module, the data is sent to the data interconnect and buffered in memory. The fault-tolerant high-speed data processing module reads data from memory, processes it, and sends the processing result to the memory buffer. Then, it passes through the encoding verification module, flow control module, and frame processing module, and is sent back to the satellite's high-speed payload via the AXI bus module, PICE logic core, and high-speed interface SerDes. This invention has the following advantages and effects: it can accommodate low-speed data while achieving high-speed data transmission and processing, and simultaneously ensures high reliability and stable operation in orbit.

Description

Technical Field

[0001] This invention relates to the field of satellite on-orbit operational data technology, and in particular to a high-speed data processing method with high reliability and fault tolerance on-orbit. Background Technology

[0002] Satellite on-orbit operational data refers to the data collected, generated, and transmitted to the ground by the payload during the normal operation of a satellite in its predetermined orbit. It represents the ultimate value of the satellite and is distinct from the engineering telemetry data that sustains the satellite platform. Satellite on-orbit operational data is large in volume and diverse in type. With the increase in satellite on-orbit operational data, higher demands are placed on data transmission, flow control, storage, and verification. Traditional low-to-medium speed serial communication methods such as IO, SPI, IIC, CAN, and UART cannot meet the requirements of high speed, high burst speed, and low latency. Furthermore, traditional on-chip caching methods have shortcomings such as slow read / write speeds and small capacity. Currently, some on-orbit operational data systems utilize high-speed data systems with some fault-tolerant hardware design. However, because they are essentially ported from ground-based high-speed systems, the reliability design, fault-tolerant design, and power control measures in the overall system implementation are still insufficient, and there is still a gap before effective on-orbit operation. Summary of the Invention

[0003] The purpose of this invention is to provide a high-reliability, fault-tolerant, high-speed data processing method in orbit that is compatible with low-speed data while enabling the transmission and processing of high-speed data, and at the same time ensures high reliability and stable operation in orbit.

[0004] The above-mentioned technical objective of this invention is achieved through the following technical solution: a high-reliability, fault-tolerant, high-speed data processing method for on-orbit operation, wherein high-speed data is input to the satellite high-speed payload, the high-speed interface Serdes and the PICE logic core receive the high-speed data and send it to the AXI bus module, and then through the frame processing module, flow control module, and encoding verification module before being sent to the data interconnect and cached by the memory; the fault-tolerant high-speed data processing module reads the data from the memory for processing, and the processing result is sent to the memory buffer and then through the encoding verification module, flow control module, and frame processing module, and then through the AXI bus module via the PICE logic core and the high-speed interface Serdes to send it to the satellite high-speed payload.

[0005] A further feature of the present invention is that the fault-tolerant high-speed data processing module is used to adjust the high-speed data stream according to the actual space environment and the overall satellite situation.

[0006] A further feature of the present invention is that the fault-tolerant high-speed data processing module includes a self-balancing design for on-orbit power and high-speed transmission. Specifically, it detects the power of the solar array; if the energy is sufficient, it detects the overall satellite thermal control; if the energy is insufficient, the control chip enters a low-power mode and switches to low-speed transmission; if the overall satellite thermal control has good heat dissipation, the control chip enters a high-power mode and switches to the highest-speed transmission.

[0007] A further feature of the present invention is that the fault-tolerant high-speed data processing module includes error correction coding and high-speed transmission self-balancing design, specifically: detecting single-event scenarios in space; if there are few single-event events, low-occupancy channel error correction coding is used; if there are many single-event events, high-occupancy channel error correction coding is used.

[0008] A further feature of the present invention is that fault-tolerant control is performed by controlling the AXI bus module and the flow control module through the space service software.

[0009] The invention is further configured such that: the frame processing module performs frame splitting and re-framing operations on satellite payload data frames and has a verification design; the flow control module controls the data flow direction and speed and has a fault-tolerant design; and the encoding verification module executes the encoding strategy of the fault-tolerant high-speed data processing module to encode and correct the correctness of the channel data.

[0010] A further feature of the present invention is that the high-speed interface Serdes uses four pairs of high-speed differential transceivers from an FPGA.

[0011] A further configuration of the present invention is as follows: the memory includes a cache module and a storage module. The cache module uses an external DDR design and has corresponding driver logic designed. The storage module uses a SATA3 interface solid-state drive and has corresponding driver logic and application logic designed.

[0012] A further configuration of the present invention is as follows: the satellite low-speed payload sends low-speed data to the AXI bus module, which then sends the data to the data interconnect after passing through the frame processing module, flow control module, and encoding verification module, and is cached by the memory; the fault-tolerant high-speed data processing module reads the data from the memory for processing, and the processing result is sent to the memory buffer and then sent to the satellite low-speed payload through the encoding verification module, flow control module, frame processing module, and then by the AXI bus module.

[0013] The invention is further configured to include two backup processing systems and a shift switching module, which selects a healthy processing system for the shift. The processing system uses a dual-core ARM SOC as the main controller. The SOC includes an embedded CPU processing unit and an FPGA processing unit. The embedded CPU processing unit and the FPGA processing unit are interconnected via a high-speed AXI bus. The embedded CPU processing unit has an external high-speed DDR cache chip and is designed with ECC error correction and detection to achieve one-to-two error correction. The refresh of the FPGA processing unit is managed by an external FLASH FPGA. The FLASH FPGA reads configuration information from three Norflash chips storing configuration information and performs a triple modular redundancy design. The output with the same majority is used as the final output of the voting system. The Nandflash pellet memory is connected to the FPGA processing unit. Through bad block management and a triple modular redundancy design for critical registers, the reliability of important data storage is ensured. The FPGA processing unit is connected to a high-speed bus interface and externally connected to a high-speed payload, AI computing module, and SATA hard drive via a high-speed switch.

[0014] The beneficial effects of this invention are as follows: The satellite high-speed payload of this invention packages high-speed data into an on-chip high-speed bus (AXI bus module) through a high-speed SerDes interface and a high-speed PCIe logic core. The frame processing module performs frame splitting and refraction operations on the satellite payload data. The flow control module controls the data flow direction and speed. The encoding and verification module executes the encoding strategy of the fault-tolerant high-speed data processing module to encode and correct the correctness of the channel data. The fault-tolerant high-speed data processing module processes satellite payload data according to service needs, featuring a dual fault-tolerant design. It can adjust the high-speed data flow according to the actual space environment and the overall satellite status. Fault-tolerant control can be performed by using satellite management software to control the AXI bus module and flow control module as needed. This invention is compatible with both low-speed data and high-speed data transmission and processing, while ensuring high reliability and stable operation in orbit. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the data flow of the present invention.

[0016] Figure 2 This is a system hardware block diagram of the present invention.

[0017] Figure 3 This is a schematic diagram of the on-orbit power and high-speed transmission self-balancing logic design of the present invention. PS refers to the embedded CPU processing unit in the SOC. PL refers to the FPGA processing unit in the SOC. The entire system adopts a dual-machine backup fault-tolerant design.

[0018] Figure 4 This is a schematic diagram of the error correction coding and high-speed transmission self-balancing logic design of the present invention. Detailed Implementation

[0019] A method for implementing high-reliability, fault-tolerant, high-speed data processing in orbit, referenced Figures 1 to 2 The satellite high-speed payload receives high-speed data. The high-speed interface Serdes and the PICE logic core receive the high-speed data and send it to the AXI bus module. After passing through the frame processing module, flow control module, and encoding verification module, the data is sent to the data interconnect and buffered by the memory. The fault-tolerant high-speed data processing module reads the data from the memory, processes it, and sends the processing result to the memory buffer. After passing through the encoding verification module, flow control module, and frame processing module, the data is sent to the satellite high-speed payload by the AXI bus module through the PICE logic core and the high-speed interface Serdes.

[0020] The high-speed interface SerDes utilizes four pairs of high-speed differential transceivers on an FPGA. The frame processing module performs frame splitting and reassembly operations on satellite payload data frames and incorporates verification design. The flow control module controls the data flow direction and speed and features fault-tolerant design. The encoding and verification module executes the encoding strategy of the fault-tolerant high-speed data processing module, encoding and correcting the channel data for correctness. The fault-tolerant high-speed data processing module is used to adjust the high-speed data stream based on actual space environment conditions and overall satellite configuration.

[0021] The fault-tolerant high-speed data processing module includes an on-orbit power and high-speed transmission self-balancing design, reference Figure 3 Specifically, this involves: detecting the power of the solar array. If energy is sufficient, the overall satellite thermal control is monitored; if energy is insufficient, the control chip enters a low-power mode, switching to low-speed transmission; if the overall satellite thermal control and heat dissipation are good, the control chip enters a high-power mode, switching to the highest transmission speed. In terms of power and speed self-balancing design, the power consumption of components (such as DDR) is adjusted in real time based on the on-orbit energy situation to adapt to different speeds. When energy is abundant, high-speed operation is performed to improve data transmission efficiency. When energy is low, component power consumption is reduced, and low-speed operation is performed to ensure the overall satellite energy safety. Simultaneously, the overall satellite thermal control situation is monitored to adjust power usage.

[0022] The fault-tolerant high-speed data processing module includes error correction coding and a high-speed transmission self-balancing design, as referenced. Figure 4Specifically, the invention detects single-event events (SEE) in space. If SEE events are infrequent, low-occupancy channel error correction coding is used; if SEE events are frequent, high-occupancy channel error correction coding is used. This invention uses spacecraft software to control the AXI bus module and flow control module for fault-tolerant control. The memory includes a cache module and a storage module. The cache module uses external DDR, and the storage module uses a SATA3 interface solid-state drive. In the self-balancing design of channel data coding error correction and high-speed transmission, when encountering severe space environments (such as solar storms) causing a high number of SEE events, i.e., when high-reliability data is the primary concern, a coding method with higher channel resource consumption is used to improve on-orbit data reliability. When normal SEE events are infrequent, i.e., when high-speed data transmission is possible, the system automatically switches to a coding method with lower channel resource consumption to achieve high-speed data transmission rates.

[0023] To accommodate low-speed data streams, the satellite's low-speed payload sends low-speed data to the AXI bus module. After passing through the frame processing module, flow control module, and encoding verification module, the data is sent to the data interconnect and buffered in memory. The fault-tolerant high-speed data processing module reads data from memory, processes it, and sends the processing result back to the memory buffer. Then, it passes through the encoding verification module, flow control module, and frame processing module before being sent back to the satellite's low-speed payload via the AXI bus module. The low-speed data stream is transmitted between the satellite's low-speed payload and the AXI bus module via medium-to-low-speed serial communication methods such as IO, SPI, IIC, CAN, and UART.

[0024] The hardware used in this invention is based on the hardware architecture of a fault-tolerant onboard computer using a System-on-a-Chip (CPU+FPGA) that is currently in use and has some applications in orbit. The overall hardware architecture block diagram of this architecture is as follows: Figure 2 As shown, PS refers to the embedded CPU processing unit in the SOC. PL refers to the FPGA processing unit in the SOC. For a high-reliability, fault-tolerant, high-speed data processing system in orbit, two backup processing systems are designed. A shift switch module selects the healthy system to take over the shift.

[0025] It uses a dual-core ARM SOC as the main controller, with the PS and PL interconnected via a high-speed AXI bus. The PS is equipped with an external high-speed DDR cache chip and is designed with ECC error correction and detection, which can achieve one-to-two error correction.

[0026] The refresh of PL is managed by an external FLASH FPGA. The configuration information is stored in three external Norflash chips. When the FLASH FPGA reads the configuration information from the Norflash, it performs a three-modal redundancy design. The output with the same majority is used as the final output of the voting system. As long as the correct operation is performed correctly in more than two of the three modules, the correct result can be output.

[0027] The Nandflash chips are connected to the PL terminal, and the reliability of important data storage is ensured through bad block management and triple redundancy design of critical registers.

[0028] The PL side supports high-speed bus interfaces, including GTX, PCIe, and SATA interfaces, with speeds reaching approximately 10Gbps. Externally, high-speed payloads, AI computing modules, SATA hard drives, etc., can be connected via a high-speed switch.

Claims

1. A method for implementing high-reliability, fault-tolerant, high-speed data processing in orbit, characterized in that: The satellite's high-speed payload receives high-speed data. The high-speed interface SerDes and PCIe logic core receive the high-speed data and send it to the AXI bus module. After passing through the frame processing module, flow control module, and encoding / verification module, the data is sent to the data interconnect and cached by the memory. The memory includes a cache module and a storage module; the cache module uses external DDR, and the storage module uses a SATA3 interface solid-state drive. The fault-tolerant high-speed data processing module reads data from the memory, processes it, and sends the processing result back to the memory cache. After passing through the encoding / verification module, flow control module, and frame processing module, it is then sent by the AXI bus module via the PCIe logic core and the high-speed interface SerDes. The system provides high-speed payloads for the satellite; the fault-tolerant high-speed data processing module adjusts the high-speed data stream based on the actual space environment and the overall satellite condition; the fault-tolerant high-speed data processing module includes a self-balancing design for on-orbit power and high-speed transmission, specifically: detecting the power of the solar array; if the energy is sufficient, it detects the overall satellite thermal control; if the energy is insufficient, the control chip enters a low-power mode and switches to low-rate transmission; if the overall satellite thermal control and heat dissipation are good, the control chip enters a high-power mode and switches to the highest-rate transmission; the fault-tolerant high-speed data processing module includes error correction coding and a self-balancing design for high-speed transmission, specifically: detecting single-event events in space; if single-event events are few, it adopts a low-occupancy signal... Error correction coding is used; if there are many single-event events, high-occupancy channel error correction coding is used; fault-tolerant control is performed by controlling the AXI bus module and flow control module through the satellite management software; the device for implementing the above method includes two sets of mutually redundant processing systems and a shift switch module, which selects a healthy processing system for the shift; the processing system uses a dual-core ARM SOC as the main controller, the SOC includes an embedded CPU processing unit and an FPGA processing unit, the embedded CPU processing unit and the FPGA processing unit are interconnected through a high-speed AXI bus, the embedded CPU processing unit is externally connected to a high-speed DDR cache chip, and is designed with ECC. Error correction and detection, achieving one-to-two correction, is achieved through external FLASH-type FPGA management of FPGA processing unit refresh. The FLASH-type FPGA reads configuration information from three Norflash chips storing configuration information and executes a triple-modal redundancy design, using the majority of identical outputs as the final output of the voting system. Nandflash memory is connected to the FPGA processing unit, and through bad block management and triple-modal redundancy design of critical registers, the reliability of important data storage is ensured. The FPGA processing unit is connected to a high-speed bus interface, and externally, high-speed payloads, AI computing modules, and SATA hard drives are connected through a high-speed switch.

2. The on-orbit high-reliability fault-tolerant high-speed data processing implementation method according to claim 1, characterized in that: The frame processing module performs frame splitting and re-framing operations on satellite payload data frames; the flow control module controls the data flow direction and speed; and the encoding and verification module executes the encoding strategy of the fault-tolerant high-speed data processing module to encode and correct the correctness of channel data.

3. The on-orbit high-reliability fault-tolerant high-speed data processing implementation method according to claim 1, characterized in that: The high-speed interface Serdes uses four pairs of high-speed differential transceivers from an FPGA.

4. The on-orbit high-reliability fault-tolerant high-speed data processing implementation method according to claim 1, characterized in that: The satellite's low-speed payload sends low-speed data to the AXI bus module, which then passes through the frame processing module, flow control module, and encoding verification module before being sent to the data interconnect and cached by the memory. The fault-tolerant high-speed data processing module reads data from the memory, processes it, and sends the processing result back to the memory cache before it passes through the encoding verification module, flow control module, and frame processing module before being sent back to the satellite's low-speed payload via the AXI bus module.

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