Flash memory error injection test method and electronic device

Abstract

The application discloses a flash memory error injection test method and electronic equipment, and relates to the technical field of error injection test. The application utilizes inherent physical characteristics, namely, writing characteristics, of a NAND flash memory. Different data is written at least twice to the same position of a target block in the flash memory, the number of free electrons of a floating gate of the flash memory is disturbed from a physical layer, data errors in the flash memory are caused, a physical abnormal scene of the flash memory is constructed, and thus, read-write error test of the flash memory is realized. Therefore, a technician can discover problems exposed in the test process of the flash memory in time, and thus, the risk of failure after mass production is reduced.

Description

Technical Field

[0001] This application relates to the field of error injection testing technology, and in particular to a flash memory error injection testing method and electronic device. Background Technology

[0002] Error injection testing is a method where testers intentionally introduce errors into a system to determine its robustness and error handling capabilities. NAND flash memory is a non-volatile storage medium. NAND flash memory is prone to read and write errors in real-world use. Traditional testing methods inject errors at the firmware level using logical command injection, performing error injection testing at the software level. This approach cannot simulate read and write errors caused by the inherent physical characteristics of NAND flash memory, and therefore has limitations. Summary of the Invention

[0003] This application provides a flash memory error injection testing method and electronic device to at least solve the problem that related technologies are limited in that they cannot simulate the read and write errors caused by the physical characteristics of NAND flash memory itself.

[0004] This application provides a flash memory error injection testing method, including:

[0005] Determine the target block from multiple blocks of the flash memory to be tested;

[0006] According to preset test parameters, multiple error injection tests are performed on the target block to obtain the test results of each error injection test; the preset test parameters include the error ratio, and the error injection tests include:

[0007] Erase the data in the target block;

[0008] Two sets of write operations are performed consecutively at the same location in the target block, and the data written in the first set of write operations and the second set of write operations are different; the error ratio is the proportion of the difference between the second set of write operations and the first set of write operations, and the error ratios of at least two error injection tests are different;

[0009] Perform a read operation on the location and determine the test result of this error injection test based on the return status of the read operation.

[0010] This application also provides a flash memory error injection testing apparatus, comprising:

[0011] The determination module is used to determine the target block from multiple blocks of the flash memory to be tested;

[0012] The testing module is used to perform multiple error injection tests on the target block according to preset test parameters to obtain the test results of each error injection test. The preset test parameters include the error ratio. The error injection test includes: erasing data in the target block; performing two consecutive write operations on the same position in the target block, and the data written by the first and second write operations are different; the error ratio is the proportion of the difference between the second and first write operations, and the error ratios of at least two error injection tests are different; performing a read operation on the position, and determining the test result of this error injection test based on the return status of the read operation.

[0013] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described flash memory error injection test methods when executing the computer program.

[0014] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described flash memory error injection test methods.

[0015] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described flash memory error injection test methods.

[0016] The flash memory error injection test method and electronic device provided in this application offer a feasible solution for flash memory reliability testing. By utilizing the inherent physical characteristics of NAND flash memory, namely its write characteristics, different data is written to the same location of the target block in the flash memory at least twice, thereby physically interfering with the number of free electrons in the floating gate of the flash memory, causing data errors inside the flash memory, and constructing a physical abnormal scenario for the flash memory. This enables read and write error testing of the flash memory, allowing technicians to promptly identify problems exposed during the testing process, thereby reducing the risk of failure after mass production. Attached Figure Description

[0017] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a system architecture provided for this application;

[0019] Figure 2 A flowchart illustrating a flash memory error injection testing method provided in this application;

[0020] Figure 3 A flowchart illustrating another flash memory error injection testing method provided in this application;

[0021] Figure 4 A schematic diagram of the structure of a flash memory error injection test device provided in this application;

[0022] Figure 5 A schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, other embodiments obtained by those of ordinary skill in the art without creative effort are all within the protection scope of this application.

[0024] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0025] Common types of errors in solid state drives (SSDs) include firmware injection errors (such as an operation interruption causing the firmware to not be fully written, resulting in an error), data read / write errors (such as an anomaly occurring when reading or writing data to the SSD), or injection problems related to security features (such as key injection failure).

[0026] NAND flash memory read / write errors are relatively common, affecting not only data integrity but also the stability and reliability of SSDs. The causes of read / write errors are varied. They may be caused by electromagnetic interference, signal attenuation, or line noise affecting data transmission within the NAND flash memory; damage to the NAND flash memory due to high temperature, high humidity, electrostatic discharge, or abnormal voltage may also lead to data corruption; the checksum calculated by an incorrect Cyclic Redundancy Check (CRC) algorithm may not match the actual data; and unstable or out-of-range power supply voltage can also cause data write or read errors.

[0027] Error injection testing for NAND flash memory can proactively uncover potential software weaknesses that might be difficult to detect using conventional testing methods. By intentionally introducing faults and simulating real-world scenarios that could lead to errors, it allows engineers to observe the software's performance under adverse conditions, prompting them to make improvements and thus reducing the likelihood of serious problems occurring after deployment.

[0028] In related technologies, testing for NAND flash memory read / write errors involves injecting errors at the firmware level using logical command injection, thus forcibly modifying the NAND return status to an abnormal state. However, this method cannot simulate read / write errors caused by the inherent physical characteristics of NAND flash memory and has limitations.

[0029] The address structure of NAND flash memory includes: Block, Page, and Wordline.

[0030] Block: The basic unit of erasure for NAND flash memory.

[0031] Page: The basic unit for reading and writing NAND flash memory, which typically contains multiple word lines.

[0032] Character line: The specific location where text is written within the page.

[0033] The basic operations of NAND flash memory include: Read, Program, and Erase.

[0034] Reading: in units of pages, typically a page is 2 kilobytes (KB) or 4 KB.

[0035] Writing: in units of word lines; a page typically contains multiple word lines.

[0036] Erase: in blocks, where a block contains multiple pages.

[0037] Before writing, the data must be erased: after erasing, the data in the block is all 1s. The write operation changes the 1s to 0s and cannot directly overwrite the data.

[0038] A key characteristic of NAND flash memory write operations is that they can only change a 1 to a 0, not a 0 to a 1. This means that write operations are irreversible. Therefore, an erase operation must be performed before each write operation, as the erase operation restores all bits to 1.

[0039] This application utilizes the write characteristics of NAND flash memory to simulate physical errors by intentionally writing inconsistent data to the same location in the NAND flash memory. This method can realistically simulate error scenarios that may occur in NAND flash memory during actual use.

[0040] Specifically, this application provides a feasible solution for reliability testing of NAND flash memory. By utilizing the inherent physical characteristics of NAND flash memory, namely its write characteristics, different data is written to the same location of the target block in the NAND flash memory at least twice. This physically interferes with the number of free electrons in the floating gate of the NAND flash memory, causing data errors inside the NAND flash memory and constructing a physical abnormal scenario for the NAND flash memory. This enables read and write error testing of NAND flash memory, allowing technicians to promptly identify problems exposed during the testing process and thereby reducing the risk of failure after mass production.

[0041] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0042] The specific application environment architecture or specific hardware architecture on which the execution of the flash memory error injection test method depends is described here.

[0043] Figure 1 A schematic diagram of a system architecture provided for this application, such as Figure 1 As shown, the system architecture includes an electronic device 10 and an SSD 20, and the electronic device 10 is communicatively connected to the SSD 20.

[0044] SSD20 is the SSD to be tested, and electronic device 10 is used to perform fault injection testing on SSD20. For example, electronic device 10 can be any device capable of performing fault injection testing on an SSD, such as a laptop, desktop computer, or other suitable device.

[0045] The electronic device 10 includes a processor 101. The processor 101 is used to execute instructions for testing the SSD 20.

[0046] Optionally, the processor 101 is connected to the SSD 20 via a bus. For example, the bus includes a data bus, an address bus, and a control bus.

[0047] Optionally, the processor 101 connects to the SSD 20 via an interface. For example, a Serial Advanced Technology Attachment (SATA) interface or a Peripheral Component Interconnect Express (PCIe) interface. For an SSD 20 using a SATA interface, the processor 101 communicates with the SSD 20 through a SATA controller; for an SSD 20 using a PCIe interface, the processor 101 can directly perform high-speed data transfer with the SSD 20 via the PCIe bus, for example, through NVMe. Here, NVMe refers to NVM Express, or Non-Volatile Memory Host Controller Interface Specification (NVMHCIS), which is a logical device interface specification.

[0048] Figure 1 An example is given where the processor 101 and the SSD 20 are connected via a bus.

[0049] SSD20 is used for data storage. SSD20 is a non-volatile storage device, meaning that data stored on it will not be lost even when power is off. For example, in a laptop, the operating system and user files (such as documents, pictures, videos, etc.) can be stored on an SSD20.

[0050] SSD20 includes NAND flash memory 201 and a controller module 202. The controller module 202 is communicatively connected to the processor 101. Figure 1 An example is given where the processor 101 and the main control module 202 are connected via a bus.

[0051] NAND flash memory is the internal storage medium of the SSD20 and consists of a large number of storage cells arranged in a specific structure to form a storage array. Each storage cell is used to store data. Each storage cell can store one or more bits of data.

[0052] The NAND flash memory 201 is managed and controlled by the main control module 202. The main control module 202 is used to control the read and write operations of the NAND flash memory 201. The main control module 202 is connected to the NAND flash memory 201 through internal circuitry, and can send read and write commands to the NAND flash memory 201, manage the storage location of data in the NAND flash memory 201, and perform data verification and other operations.

[0053] SSD20 also includes a Flash Translation Layer (FTL). The FTL is a software and hardware integrated component; the hardware of the FTL is integrated into the main control module 202, while the software runs on the hardware. Accordingly, the main control module 202 manages and controls the NAND flash memory 201 through the FTL.

[0054] When the processor 101 tests the NAND flash memory 201, it only needs to interact with the main control module 202 of the SSD 201. The main control module 202 is used to convert the requests of the processor 101 into operation instructions for the NAND flash memory 201.

[0055] The flash memory error injection test method provided in this application is executed by a flash memory error injection test device, which is integrated into an electronic device, such as electronic device 10.

[0056] Figure 2 A flowchart illustrating a flash memory error injection testing method provided in this application is shown below. Figure 2 As shown, the method includes the following steps S201-S202.

[0057] S201: Determine the target block from multiple blocks of the flash memory to be tested.

[0058] Here, flash memory can be NAND flash memory. A block is the basic unit of erasure for NAND flash memory, and NAND flash memory contains multiple blocks.

[0059] S202: Perform multiple error injection tests on the target block according to the preset test parameters to obtain the test results of each error injection test.

[0060] Preset test parameters are used to represent test conditions. In actual testing, preset test parameters can be flexibly set to adjust the test conditions of NAND flash memory to meet test requirements.

[0061] The total number of error injection tests can be set according to actual testing needs, such as 10 times, 20 times, etc., and this application does not limit this.

[0062] The test results are used to indicate whether there are any abnormalities in the NAND flash memory.

[0063] The following describes an error injection test.

[0064] The error injection test includes the following steps S2021-S2023.

[0065] S2021: Erase the data in the target block.

[0066] The write characteristics of NAND flash memory require that it must be erased before writing; it cannot be directly overwritten.

[0067] After erasing the data in the target block, the data in the target block will be in an all-1 state.

[0068] S2022: Two sets of write operations are performed consecutively on the same location in the target block, and the data written by the first set of write operations and the second set of write operations are different.

[0069] The preset test parameters include an error ratio, which is the proportion of data differences between the second set of write operations and the first set of write operations. Difference data refers to the unique data within the written data. Furthermore, the error ratios must be different in at least two error injection tests.

[0070] A write operation changes the data at that position in the target block from 1 to 0.

[0071] The first group of write operations includes the first write operation, and the second group of write operations includes all other write operations except the first write operation. In other words, the second group of write operations includes at least one write operation.

[0072] The number of writes in a single error injection test can be set according to actual test requirements, such as 2, 3, 4, etc. This application does not limit this.

[0073] The data written in the first group of write operations is different from that written in the second group of write operations. This means that each write operation in the second group of write operations is different from the data written in the first group of write operations.

[0074] For each write operation in the second group of write operations, the same data can be written, or different data can be written.

[0075] For example, only two write operations are performed. That is, the second set of write operations contains only one write operation, and this write operation is the second write operation. For instance, the first write operation writes data A, specifically changing some bits in the target block from 1 to 0. The second write operation writes data B, specifically attempting to change some bits from 1 to 0 again. No erase operation is performed before the second write operation. If the target bits are already 0 (because the first write has already changed them from 1 to 0), then the second write operation will not change the state of these bits. In other words, the second write does not overwrite the data written in the first write, but attempts to write again, but may fail. Therefore, the second write may cause the state of some bits to be uncertain, especially when the data written in the first and second writes is inconsistent. This can cause internal data errors in the NAND flash memory, resulting in a fault state where some data is correct and some data is incorrect within the NAND flash memory.

[0076] By repeatedly writing different data to the same location in a NAND flash memory, resulting in an unexpected distribution of the number of electrons in the floating gate, charge leakage or write interference is simulated, thereby constructing a physical anomaly scenario for the NAND flash memory.

[0077] S2023: Perform a read operation on the location where the data was written, and determine the test result of this error injection test based on the return status of the read operation.

[0078] Because the data written by the two sets of write operations is inconsistent, a decoding error may occur, and a read failure will be returned.

[0079] The return status of NAND flash memory is generated and updated through its internal status register. After each operation (such as erase, read, etc.), the value of the status register is updated according to the result of the operation.

[0080] The status register contains multiple bits, each representing different status information. For example, bit 0 indicates whether the device is busy (0 means busy, 1 means ready); bit 1 indicates whether the device is write-protected (0 means not write-protected, 1 means write-protected); bit 2 indicates whether the programming operation failed (0 means successful, 1 means failed); bit 3 indicates whether the erase operation failed (0 means successful, 1 means failed); bit 4 indicates whether the block is locked (0 means unlocked, 1 means locked); bit 5 indicates whether there is an ECC error (0 means no ECC error, 1 means an ECC error exists); bit 6 indicates whether the read operation failed (0 means successful, 1 means failed). ECC is short for "Error Checking and Correcting".

[0081] After each operation, the NAND flash memory updates the corresponding bit in the status register based on the result of the operation. The value of the status register can be obtained by sending a read status command.

[0082] Accordingly, the return status of a read operation may be read failure or read success.

[0083] Optionally, if the return status is "read failed", it means that the NAND flash memory has identified an error at the read location, and the test result of this error injection test is determined to be that the NAND flash memory is normal.

[0084] Optionally, if the return status is "read successful", it means that the NAND flash memory did not recognize the error existing at the read location, and the test result of this error injection test is determined to be that there is an anomaly in the NAND flash memory.

[0085] However, there might be a false positive even in cases where the read operation is successful. Because NAND flash memory has error correction capabilities, it can identify and correct errors at the read location, resulting in a successful read status. Therefore, this situation doesn't necessarily indicate a problem with the NAND flash memory. Consequently, in such cases, a prompt message can be displayed to encourage the user to manually check for any abnormalities in the NAND flash memory.

[0086] After obtaining the test results of this error injection test, the target block can be subjected to the next error injection test, and so on, until multiple error injection tests are completed.

[0087] This application provides a feasible solution for reliability testing of NAND flash memory. By utilizing the inherent physical characteristics of NAND flash memory, namely its write characteristics, different data is written to the same location of the target block in the NAND flash memory at least twice. This physically interferes with the number of free electrons in the floating gate of the NAND flash memory, causing data errors inside the NAND flash memory and constructing a physical abnormality scenario for the NAND flash memory. This enables read and write error testing of NAND flash memory, allowing technicians to promptly identify problems exposed during the testing process and thus reduce the risk of failure after mass production.

[0088] Based on the above embodiments, multiple target blocks can be determined from multiple blocks of NAND flash memory, and multiple error injection tests can be performed on each target block, thereby achieving a more comprehensive test of NAND flash memory and reducing the limitations of testing only one target block.

[0089] Based on the above embodiments, the determination of each target block can be flexibly set. For example, any one of the multiple blocks of NAND flash memory can be determined as the target block.

[0090] In some embodiments, the target block can be selected based on different layers and regions of the NAND flash memory. S201, that is, determining the target block from multiple blocks of the NAND flash memory to be tested, includes the following various implementations.

[0091] Example 1: Determine any one of the blocks located in the starting layer from among multiple blocks as the target block.

[0092] Example 2: Select any one of the blocks located in the final layer from among multiple blocks as the target block.

[0093] Example 3: Select any one of the blocks located in the edge or middle area of ​​any layer from among multiple blocks as the target block.

[0094] From a comprehensive perspective, the aforementioned multiple implementation methods can cover the characteristics of different physical locations. NAND flash memory may exhibit differences in characteristics across different layers and regions in its physical structure. For example, blocks in the initial layer may be affected differently by manufacturing processes compared to those in the final layer. Initial layer blocks are likely the earliest manufactured and packaged, exhibiting relatively stable physical characteristics, but may suffer from early process deviation accumulation. Final layer blocks, on the other hand, are affected by more subsequent process steps, such as interlayer stress distribution. Blocks in edge and middle regions also differ in their physical environments. Edge region blocks may be affected by boundary effects, such as interactions with surrounding non-flash memory areas and differences in heat dissipation. Middle region blocks, however, are in a relatively uniform internal environment. Determining the target block through multiple implementation methods can encompass these different physical location characteristics, making the test results more reflective of the true state of the entire NAND flash memory at different locations, and avoiding the bias caused by selecting only a block at a specific location.

[0095] From a reliability perspective, the aforementioned multiple implementation methods can reduce the impact of random factors. If only a specific block is selected as the target block, the accuracy of the test results may be affected by some random factors within that block itself (such as individual manufacturing defects, uneven distribution of impurities, etc.). However, by using multiple implementation methods and selecting target blocks from different levels and regions, the interference of such random factors can be reduced. Even if an anomaly exists in a certain block, the test results of blocks in other locations can provide a more reliable reference, thereby more accurately determining the overall reliability of the flash memory.

[0096] Based on the above embodiments, in some embodiments, at least two storage units are pre-configured for storing data, which is test data to be written to the NAND flash memory.

[0097] This storage unit is not a storage unit inside the NAND flash memory, but a storage resource independent of the NAND flash memory. For example, this storage unit is Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), or simply DDR.

[0098] For a single error injection test, each write operation corresponds to one storage unit. During the write operation, data is read from the corresponding storage unit and written to the same location in the target block. Accordingly, S2022 involves performing at least two consecutive write operations on the same location in the target block. This operation is specifically implemented by sequentially reading data from at least two storage units and writing it to the same location in the target block. Each write operation writes all the data from the corresponding storage unit to the target block.

[0099] For a single error injection test, to ensure that the data written each time is different, it is necessary to configure each storage unit to store different data.

[0100] The proportion of different data in each written data set is controllable. Specifically, it can be controlled based on the error rate.

[0101] The number of writes in a single error injection test can be preset, and the total number of storage units can also be preset according to this number of writes. That is, there must be at least two storage units, and the total number of these at least two storage units must be the same as the number of writes. These at least two storage units include a first storage unit and other storage units besides the first storage unit. Each storage unit stores the same number of bytes of data; that is, each storage unit stores the same amount of data. The ratio of the different data in the other storage units (excluding the first storage unit) to the first storage unit is the aforementioned error ratio.

[0102] Optionally, if the number of write operations is 2, that is, there are two write operations, then the above error ratio is the ratio of the different data written in the second write operation and the first write operation, and also the ratio of the different data in the second storage unit and the first storage unit. For example, if the error ratio is 20%, the data stored in the first storage unit is "AAAA", and the data stored in the second storage unit is "AAAB", then the data written in the first write operation is "AAAA", and the data written in the second write operation is "AAAB".

[0103] Optionally, if the number of writes is equal to or greater than 3, that is, there are three or more write operations, then each write operation in the second group of write operations, that is, each write operation other than the first write operation, has its own corresponding error ratio, and the error ratios of different write operations can be the same or different, and this application does not limit this.

[0104] In this case, the amount of data written in each write operation is the same. NAND flash memory read operations are performed in units of pages, and the amount of data that can be stored in a page is typically 2KB or 4KB. Therefore, the amount of data written in each write operation can be set to the amount of data that can be stored in a page.

[0105] For example, if the error rate is 10% and the page can store 4KB of data, two independent DDR blocks with a storage capacity of 4KB each are pre-configured. The first DDR block is written with a uniform string, such as AAAA. The second DDR block is written with the string AAAA for the first 90% and the string BBBB for the last 10%.

[0106] In this application, one or more error ratios can be set according to actual testing needs. Each error ratio set includes at least one error ratio, specifically the error ratio corresponding to each write operation in the second set of write operations. For each error ratio set, a round of error injection testing can be performed on the target block, and each round of error injection testing includes multiple error injection tests.

[0107] The multiple error injection tests in step S202 include all error injection tests performed on the target block. Therefore, if one set of error ratios is set, these multiple error injection tests constitute one round of error injection tests, and the same set of error ratios is used. If multiple sets of error ratios are set, these multiple error injection tests include multiple rounds of error injection tests, and each round of error injection tests corresponds to a different set of error ratios. In this case, it can be considered that at least two of the multiple error injection tests use different error ratios.

[0108] This application physically interferes with the number of free electrons in the floating gate of NAND flash memory, causing data errors within the NAND flash memory and constructing a physical anomaly scenario for the NAND flash memory. By setting different error ratios, the recovery capability of NAND flash memory under different levels of error conditions can be tested. For example, a low error ratio can test the error correction capability of NAND flash memory, such as the low-density parity-check code (LDPC) decoding capability when the number of error bits in NAND flash memory is at a critical point, while a high error ratio can test its fault tolerance capability under extreme conditions.

[0109] By quantifying the error ratio, various failure scenarios can be simulated. Different error ratios can cover a range of situations from minor to severe errors, thus more comprehensively determining the behavior and performance of NAND flash memory under different error conditions. Through repeated testing and testing with different error ratios, the influence of random factors can be reduced, making the test results more representative and reliable.

[0110] It should be noted that this application allows the selection of blocks from different layers or regions as target blocks. Therefore, the error ratio setting can be dynamically adjusted for different target blocks. For example, a lower error ratio can be set for target blocks in edge regions, and a higher error ratio can be set for target blocks in the middle regions.

[0111] In some embodiments, the method provided in this application further includes: running the firmware of the SSD in a test environment and performing error monitoring for error injection testing. The test environment includes both the software environment in which the SSD firmware resides and the external physical environment in which the SSD resides. This test environment can be controlled by preset test parameters.

[0112] Accordingly, in S2023, the test result of this error injection test is determined based on the return status of the read operation. This operation includes the following steps (1)-(4).

[0113] (1): By listening for errors in the error injection test, the return status of the read operation can be obtained.

[0114] The return status of the read operation can be obtained by sending a read status command.

[0115] In some embodiments, error monitoring for error injection testing is specifically implemented by monitoring errors through an input / output testing tool or a serial port. For example, the input / output testing tool is a Flexible I / O tester (FIO), where I / O (Input / Output) refers to input and output. Before testing, the input / output testing tool or serial communication software is configured to monitor the return status of NAND flash memory read operations, ensuring that the input / output testing tool or serial communication software can capture and record the return status of each read operation.

[0116] By monitoring for errors in error injection tests, we can provide data support for subsequent troubleshooting.

[0117] (2): If the return status indicates that the read was successful, check whether there is any abnormality in the firmware.

[0118] If the return status is "read successful," it indicates that the NAND flash memory did not detect an error at the read location, and the firmware should be checked for abnormalities. Optionally, a prompt message can be output to prompt the user to manually check for firmware abnormalities. After confirming that there are no firmware abnormalities, the user can upload the results to the electronic device.

[0119] If there is an error in the firmware, proceed to step (3); if there is no error in the firmware, proceed to step (4).

[0120] (3): If it is determined that there is an anomaly in the firmware, the test result of this error injection test is determined to be that there is an anomaly in the firmware.

[0121] If the investigation results indicate that the firmware is abnormal, then it can be directly determined that the test result of this error injection test is that the firmware is abnormal.

[0122] Optionally, if an anomaly is determined in the firmware, the user can also modify the firmware to enable subsequent tests to be performed normally.

[0123] (4): If it is determined that there is no abnormality in the firmware, the test result of this error injection test is determined to be that there is an abnormality in the test environment.

[0124] If the investigation results indicate that there are no abnormalities in the firmware, then it can be determined that the test result of this error injection test is that there is an abnormality in the test environment.

[0125] For example, NAND flash memory has an error correction function that can identify and correct errors at the read location, resulting in a read success status. If the error ratio is set too low, effective error injection testing cannot be achieved under the influence of the NAND flash memory's error correction function. Therefore, it can be considered that the error ratio setting in the test environment is unreasonable.

[0126] In actual testing, the error ratio can be set to a larger value, so that even if the NAND flash memory has error correction function, it cannot correct all errors, thereby achieving effective error injection testing.

[0127] Optionally, if it is determined that there are no abnormalities in the firmware, the user can also adjust the preset test parameters to adjust the test environment so that subsequent tests can be executed normally.

[0128] The above steps (2)-(4) are examples of the case where the return status indicates that the read was successful. The following is an example of the case where the return status indicates that the read failed. In some embodiments, the test result of this error injection test is determined based on the return status of the read operation in S2023. This operation also includes the following steps (5)-(7).

[0129] (5): If the return status indicates that the read failed, execute the exception handling process in the firmware to obtain the data recovery result.

[0130] The firmware includes a pre-configured exception handling process for automatic data recovery in the event of a read failure. For example, the exception handling process includes error detection, error correction, and data recovery.

[0131] If the data recovery result indicates that the data recovery was successful, proceed to step (6); if the data recovery result indicates that the data recovery failed, proceed to step (7).

[0132] (6): If the data recovery result indicates that the data recovery was successful, the test result of this error injection test is determined to be that the NAND flash memory is normal.

[0133] This situation indicates that the NAND flash memory can handle abnormal situations, so the NAND flash memory can be considered to be normal.

[0134] (7): If the data recovery result indicates that the data recovery failed, it is determined that the test result of this error injection test is that there is an anomaly in the exception handling process.

[0135] This situation indicates that the exception handling process is unable to handle abnormal conditions, thus confirming that there is an error in the exception handling process. Optionally, in this case, a prompt message can be output to remind the user to correct the exception handling process so that subsequent tests can be executed normally.

[0136] Multi-step verification (such as read operation, firmware anomaly investigation, and data recovery results) can reduce misjudgments caused by a single indicator. For example, even if the read operation fails, it does not necessarily mean that there is a problem with the hardware itself; it may be a problem with the firmware or the test environment.

[0137] Firmware reliability can be determined by testing its performance under error conditions. This helps identify potential problems in the firmware and allows for optimization, thereby improving the overall reliability of the SSD. Testing the exception handling process verifies the SSD's data recovery capabilities under error conditions. This helps ensure that data can be effectively recovered even in the event of errors during real-world use, reducing the risk of data loss.

[0138] In some embodiments, the preset test parameters further include an error injection step size. S202, that is, according to the preset test parameters, multiple error injection tests are performed on the target block to obtain the test results of each error injection test, including: starting the test with an initial error ratio, and increasing the error ratio step size for each subsequent error injection test until the test result of the current error injection test indicates failure; the error ratio corresponding to the test result indicating failure is determined as the error tolerance threshold of the target block.

[0139] The initial error rate can be set according to actual needs, such as 10% or 15%, and this application does not limit it. The error injection step size can be set according to actual needs, such as 1% or 5%, and this application does not limit it.

[0140] Among them, a test result indicating failure means that the test result indicates that there is an error in the firmware or that there is an error in the error handling process.

[0141] The error tolerance threshold refers to the percentage of errors that a target block can tolerate. The error tolerance threshold can be used to represent the reliability level of NAND flash memory.

[0142] This embodiment provides a progressive error injection method, which does not inject the maximum proportion of errors at once, but gradually increases the error proportion in a certain step until the test fails. This can accurately measure the error proportion threshold that the target block can tolerate, thereby quantifying the reliability of NAND flash memory.

[0143] The following describes the NAND gate flash memory error injection method provided in this application using an exemplary embodiment.

[0144] Figure 3 A flowchart illustrating another flash memory error injection testing method provided in this application is shown below. Figure 3 As shown, assume there are M error injection tests, and the M error injection tests are performed sequentially, where M is a positive integer greater than or equal to 1. The method includes the following steps.

[0145] Open the NVMe tool. The NVMe tool is used to communicate with the SSD to write or read data to or from the NAND flash memory.

[0146] Initiate the first error injection test.

[0147] The first error injection test specifically includes: erasing the target block; writing data to a specified location for the first time; writing data to the specified location for the second time; and so on, until data is written to the specified location for the Nth time; and reading the data at that location. N is the total number of write operations included in one error injection test, and N is a positive integer greater than or equal to 2.

[0148] During the first error injection test, the firmware ran normally and enabled the error monitoring function.

[0149] If no exception is detected, investigate firmware issues. If an exception is detected, execute the exception handling procedure in the firmware and determine if it meets expectations. If it does not meet expectations, investigate firmware issues. If it meets expectations, determine if the test is complete, i.e., determine if this is the Mth error injection test. If the test is complete, end. If the test is not complete, execute the next error injection test, and so on, until M error injection tests are completed. "Meeting expectations" refers to whether the data was successfully recovered.

[0150] The specific process for each of the M error injection tests is the same as that for the first error injection test, and will not be repeated here. Figure 3 This example only uses the first error injection test.

[0151] The following explains how to set the preset test parameters.

[0152] In some embodiments, the preset test parameters include the error ratio. The setting of the error ratio is described in the above embodiments and will not be repeated here.

[0153] In some embodiments, the preset test parameters may further include at least one of the following.

[0154] The preset test parameters include the write position, which is the physical location where each write operation in a single error injection test is performed. For example, the same test can be performed on different write positions, and the test results for different write positions can be compared and analyzed to compare the impact of the physical location on the physical characteristics of the NAND flash memory. By testing different write positions, the error handling capability of the NAND flash memory for different locations can be tested, verifying the consistency of the physical characteristics of the NAND flash memory.

[0155] In practice, the write location is determined by the block number, page number, and wordline number. The block number identifies the block to be operated on. The page number identifies the specific page within the block. The wordline number identifies the specific location within the page. For example, assuming the NAND flash memory block size is 64KB, each block contains 128 pages, and each page size is 512 bytes, if the specified write location is the 100th byte of the 10th page of the first block, then the block number is 1, the page number is 10, and the byte offset within the page is 100. To ensure that each write operation targets the same location, the block number, page number, byte offset within the page, and write size must be consistent for each write operation. The write size refers to the amount of data written.

[0156] The preset test parameters include the number of write operations, which is the total number of write operations included in a single error injection test. For example, the same test can be performed with different numbers of write operations to verify the impact of the number of write operations on the physical characteristics of the NAND flash memory. For example, the number of write operations can be 2, 3, or other possible numbers.

[0157] The preset test parameters include an interval time, which is the time interval between two consecutive write operations in a single error injection test. For example, the same test can be performed at different interval times, such as testing the impact of shorter and longer intervals on the physical characteristics of NAND flash memory, to verify the data timeliness of the NAND flash memory. For example, the interval time can be set to 1 millisecond (ms), 2 ms, or other possible times.

[0158] The preset test parameters include a save time, which is the interval between the last write operation and the last read operation in a single error injection test. For example, the same test can be performed with different save times to verify the impact of save time on NAND flash memory. For example, the save time can be 10 seconds (s), 20 seconds, or other possible times.

[0159] The preset test parameters also include error types, which refer to the types of difference data. For example, the difference data can be set to characters with small differences, such as A and a, or it can be set to characters with large differences, such as A and B. Exemplarily, different error types can be tested to verify the NAND flash memory's ability to handle exceptions for different error types.

[0160] The preset test parameters include ambient temperature. The SSD is placed in a temperature and humidity control device, and the ambient temperature inside the device is controllable. For example, the same test can be performed at different ambient temperatures to verify the impact of ambient temperature on NAND flash memory, such as testing the change in the number of error bits under extreme temperatures. For example, the ambient temperature can be 20 degrees Celsius, 40 degrees Celsius, 60 degrees Celsius, etc.

[0161] The preset test parameters include ambient humidity. The SSD is placed in a temperature and humidity control device, and the ambient humidity within the device is controllable. For example, the same test can be performed on different ambient humidity levels to verify the impact of ambient humidity on NAND flash memory. For instance, the ambient humidity is expressed as relative humidity, such as 30%, 40%, 50%, etc.

[0162] Temperature and humidity control equipment is used to regulate and maintain the temperature and humidity within a set range in a specific space.

[0163] The preset test parameters include electric field strength. The SSD is placed in an electromagnetic field control device, and the electric field strength in the electromagnetic field control device is controllable.

[0164] The preset test parameters include magnetic field strength. The SSD is placed in an electromagnetic field control device, and the magnetic field strength inside the electromagnetic field control device is controllable.

[0165] For example, the same test is performed on different electric field strengths or different magnetic field strengths to verify the effect of electric or magnetic fields on NAND flash memory.

[0166] For example, the electromagnetic field control device is an electromagnetic interference generator or an electromagnetic shielding box.

[0167] To quantify the impact of electromagnetic fields on the number of error bits, multiple tests can be conducted under different electromagnetic field strengths to determine the number of error bits. Specifically, different electric and magnetic field strengths are set, and under each set of electric and magnetic field strengths, multiple write and read operations on the NAND flash memory are performed, and the number of error bits in each test is determined. The average number of error bits under each set of electric and magnetic field strengths is calculated, and the relationship between the number of error bits and the electromagnetic field strength is plotted.

[0168] In this application, one or more rounds of error injection testing can be set for each preset test parameter. A single round of error injection testing includes multiple error injection tests.

[0169] Taking a preset test parameter as an example, one or more values ​​of the preset test parameter can be set, and a round of error injection test can be set for each value.

[0170] The multiple error injection tests in step S202 include all error injection tests performed on the target block. Therefore, when setting a single round of error injection tests, these multiple error injection tests are also considered a single round of error injection tests, and they all use the same value of the preset test parameter. When setting multiple rounds of error injection tests, these multiple error injection tests include multiple rounds of error injection tests, and each round of error injection tests corresponds to a different value of the preset test parameter. In this case, it can be considered that at least two of the multiple error injection tests use different preset test parameters.

[0171] For example, the write locations of at least two error injection tests are different, referring to different locations within the same target block; or, the number of writes of at least two error injection tests is different; or, the interval between at least two error injection tests is different; or, the retention time of at least two error injection tests is different; or, the ambient temperature of at least two error injection tests is different; or, the ambient humidity of at least two error injection tests is different; or, the electric field strength of at least two error injection tests is different; or, the magnetic field strength of at least two error injection tests is different.

[0172] It should be noted that adjusting multiple parameters simultaneously may have a coupled effect on the test results. In each round of error injection testing for each preset test parameter, other preset test parameters remain constant, thus isolating the independent effects of each parameter.

[0173] Errors in NAND flash memory during actual operation are diverse and interconnected. For example, common errors caused by physical reasons include the following situations.

[0174] (1) Charge leakage related error: After data is written, charge gradually leaks over time, and high temperature environment will accelerate this process.

[0175] (2) Read Disturb Errors: Frequent reading of the same block causes changes in the charge of neighboring cells, especially affecting adjacent layers in NAND flash memory.

[0176] (3) Program Disturb Errors: Write operations affect the state of adjacent word lines.

[0177] (4) Endurance Errors: As the number of Program / Erase (P / E) cycles increases, the oxide layer degrades, causing the storage window to shrink and resulting in the leakage of free electrons.

[0178] Furthermore, as the number of bits stored in each storage cell within NAND flash memory continues to increase, the types and scenarios of errors become more complex and varied. Software struggles to simulate real-world error scenarios within NAND flash memory, leading to the frequent occurrence of different types of errors simultaneously, which in turn affects the overall performance of the SSD.

[0179] By setting the aforementioned preset test parameters, this application allows for flexible adjustment of the test environment during testing to better reproduce real-world data failure scenarios and improve the comprehensiveness of the test.

[0180] By setting the above preset test parameters, full coverage of test scenarios is achieved. After thorough design, testing, and verification, users can add various exception handling processes to the firmware layer based on the test results. These processes can include error detection, error correction, data recovery, etc., thereby improving the robustness of the SSD and making it more adaptable to complex and extreme environments, thus improving reliability and data security.

[0181] Quantitative error injection testing at specified locations helps verify the effectiveness of anomaly handling procedures, especially those rarely executed during normal operation, which is crucial for the safety and reliability of product-level maintenance. This application presents a novel error injection method tailored to the unique physical properties and operating scenarios of NAND flash memory. Combined with different environments, it can more realistically recreate scenarios where internal electronic leakage in NAND flash memory leads to anomalies, and test the correctness of the anomaly handling procedures. It proactively discovers problems, exposing the SSD to failures, thereby helping technicians identify and strengthen weak points and reduce the likelihood of failures in the usage environment. This method is highly operable and has broad coverage, realizing unexpected electronic arrangement at the NAND flash memory level, recreating the most realistic physical layer anomalies. It has the advantage of achieving more realistic anomaly scenarios through physical layer perturbation, making it an effective method for predicting and troubleshooting firmware failures. This ensures that the SSD can withstand and recover from anomalies encountered in actual use, thereby maintaining SSD functionality and guaranteeing user experience. This method helps discover potential problems that cannot be found through traditional logic error injection methods, ensuring that firmware can cope with unexpected scenarios and maintain functional integrity under harsh conditions.

[0182] This application applies to different types of NAND flash memory, such as NAND flash memory in SSDs used in enterprise-class storage systems.

[0183] This application is applicable to the product development stage of SSDs, enabling early detection of problems and facilitating improvements by technical personnel, thereby achieving smooth iterative product development.

[0184] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0185] Figure 4 This is a schematic diagram of a flash memory error injection testing device provided in this application. NAND gate flash memory refers to NAND flash memory. For example... Figure 4 As shown, the flash memory error injection test apparatus 40 includes the following modules.

[0186] The determination module 401 is used to determine the target block from multiple blocks of the NAND gate flash memory to be tested;

[0187] The testing module 402 is used to perform multiple error injection tests on the target block according to preset test parameters to obtain the test results of each error injection test. The preset test parameters include the error ratio. The error injection test includes: erasing data in the target block; performing two sets of write operations consecutively on the same position in the target block, and the data written by the first set of write operations and the second set of write operations are different; the error ratio is the proportion of the difference between the second set of write operations and the first set of write operations, and the error ratios of at least two error injection tests are different; performing a read operation on the position, and determining the test result of this error injection test based on the return status of the read operation.

[0188] Optionally, when determining the target block from multiple blocks of the flash memory to be tested, the determining module 401 is specifically used to perform any of the following: determining any one of the multiple blocks located in the starting layer as the target block; determining any one of the multiple blocks located in the final layer as the target block; or determining any one of the multiple blocks located in the edge region or middle region of any layer as the target block.

[0189] Optionally, the first set of write operations includes a first write operation, and the second set of write operations includes other write operations besides the first write operation; one write operation corresponds to one storage unit, and at least two storage units include a first storage unit and other storage units besides the first storage unit. Each storage unit stores the same byte of data, and the ratio of different data in the other storage units besides the first storage unit to the first storage unit is the error ratio; the test module 402, when performing two sets of write operations consecutively at the same position in the target block, is specifically used to: sequentially read data from at least two storage units and write it to the same position in the target block.

[0190] Optionally, the flash memory is the storage medium in the solid-state drive. The test module 402 is further configured to: run the firmware of the solid-state drive in the test environment and perform error monitoring for the error injection test; correspondingly, when determining the test result of this error injection test based on the return status of the read operation, the test module 402 is specifically configured to: obtain the return status of the read operation by performing error monitoring for the error injection test; if the return status indicates that the read was successful, check whether there is an anomaly in the firmware; if it is determined that there is an anomaly in the firmware, determine that the test result of this error injection test is that there is an anomaly in the firmware; if it is determined that there is no anomaly in the firmware, determine that the test result of this error injection test is that there is an anomaly in the test environment.

[0191] Optionally, when determining the test result of this error injection test based on the return status of the read operation, the test module 402 is specifically configured to: execute the exception handling process in the firmware to obtain the data recovery result if the return status indicates that the read failed; determine that the test result of this error injection test is that the NAND gate flash memory is normal if the data recovery result indicates that the data recovery failed; and determine that the test result of this error injection test is that there is an anomaly in the exception handling process if the data recovery result indicates that the data recovery failed.

[0192] Optionally, when performing error monitoring for error injection testing, the test module 402 is specifically used to: perform error monitoring for error injection testing through an input / output test tool or a serial port.

[0193] Optionally, the preset test parameters also include an error injection step size. When the test module 402 performs multiple error injection tests on the target block according to the preset test parameters to obtain the test results of each error injection test, it specifically performs the following: starting the test with an initial error ratio, and progressively increasing the error ratio according to the error injection step size for each subsequent error injection test, until the test result of the current error injection test indicates failure; the error ratio corresponding to the point where the test result indicates failure is determined as the error tolerance threshold of the target block.

[0194] Optionally, the preset test parameters may include at least one of the following: the preset test parameters include the write position, and the write positions of at least two error injection tests are different; the preset test parameters include the number of writes, and the number of writes of at least two error injection tests are different; the preset test parameters include the interval time, which is the interval between two adjacent write operations, and the interval time of at least two error injection tests is different.

[0195] Optionally, the flash memory is the storage medium in the solid-state drive, and the preset test parameters also include at least one of the following: the preset test parameters include ambient temperature, the solid-state drive is placed in a temperature and humidity control device, and the ambient temperature inside the temperature and humidity control device is controllable, and the ambient temperature of at least two error injection tests is different; the preset test parameters include ambient humidity, the solid-state drive is placed in a temperature and humidity control device, and the ambient humidity inside the temperature and humidity control device is controllable, and the ambient humidity of at least two error injection tests is different.

[0196] Optionally, the flash memory is the storage medium in the solid-state drive, and the preset test parameters also include at least one of the following: the preset test parameters include electric field strength, the solid-state drive is placed in an electromagnetic field control device, and the electric field strength in the electromagnetic field control device is controllable, and the electric field strength of at least two error injection tests is different; the preset test parameters include magnetic field strength, the solid-state drive is placed in an electromagnetic field control device, and the magnetic field strength in the electromagnetic field control device is controllable, and the magnetic field strength of at least two error injection tests is different.

[0197] For a description of the features in the embodiment corresponding to the flash memory error injection test apparatus 40, please refer to the relevant description in the embodiment corresponding to the flash memory error injection test method, which will not be repeated here.

[0198] Figure 5 A schematic diagram of the structure of the electronic device provided in this application. Figure 5 As shown, the electronic device 10 includes a processor 101 and a memory 102. Optionally, the electronic device 10 also includes a communication component 103. The processor 101, memory 102, and communication component 103 are connected via a bus.

[0199] In the specific implementation process, the processor 101 executes the computer program stored in the memory 102, causing the processor 101 to execute the above-described flash memory error injection test method embodiment.

[0200] The specific implementation process of processor 101 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0201] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0202] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0203] Buses can be Industry Standard Architecture (ISA) buses, Peripheral Component Interconnect (PCI) buses, or Extended Industry Standard Architecture (EISA) buses, etc. Buses can be categorized into address buses, data buses, control buses, etc.

[0204] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described flash memory error injection test method embodiments when running.

[0205] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0206] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the flash memory error injection test method.

[0207] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described flash memory error injection test method embodiments.

[0208] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0209] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0210] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0211] It should be understood that the above-described device embodiments are merely illustrative, and the device of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units, modules, or components may be combined, or integrated into another system, or some features may be ignored or not executed.

[0212] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this application can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.

[0213] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0214] The present application provides a detailed description of a flash memory error injection testing method and electronic device. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A flash memory error injection test method, characterized in that, include: Determine the target block from multiple blocks of the flash memory to be tested; According to preset test parameters, perform multiple error injection tests on the target block to obtain the test results of each error injection test; The preset test parameters include the error ratio, and the error injection test includes: Erase the data in the target block; Two sets of write operations are performed consecutively at the same location in the target block, and the data written by the first set of write operations and the second set of write operations are different; the error ratio is the proportion of the difference between the second set of write operations and the first set of write operations, and the error ratios of at least two error injection tests are different; A read operation is performed on the location, and the test result of this error injection test is determined based on the return status of the read operation.

2. The flash memory error injection test method according to claim 1, characterized in that, Determining the target block from a plurality of blocks of flash memory to be tested includes any of the following: The target block is determined by any one of the multiple blocks located in the starting layer. The target block is determined by any one of the multiple blocks located in the final layer. The target block is determined from any one of the multiple blocks located in the edge or middle region of any layer.

3. The flash memory error injection test method according to claim 1, characterized in that, The first group of write operations includes a first write operation, and the second group of write operations includes other write operations besides the first write operation; one write operation corresponds to one storage unit, and at least two storage units include a first storage unit and other storage units besides the first storage unit. Each storage unit stores the same number of bytes of data, and the ratio of different data in the other storage units besides the first storage unit to the first storage unit is the error ratio. The step of performing two consecutive write operations on the same location in the target block includes: Data is read sequentially from at least two of the storage units and written to the same location in the target block.

4. The flash memory error injection test method according to claim 1, characterized in that, The flash memory is a storage medium in a solid-state drive, and the method further includes: Run the firmware of the solid-state drive in the test environment and perform error monitoring for the error injection test; Determining the test result of this error injection test based on the return status of the read operation includes: By monitoring for errors in the error injection test, the return status of the read operation can be obtained; If the return status indicates that the read was successful, check whether there is any abnormality in the firmware; If it is determined that the firmware is abnormal, the test result of this error injection test is determined to be that the firmware is abnormal; If it is determined that there is no abnormality in the firmware, the test result of this error injection test is determined to be that there is an abnormality in the test environment.

5. The flash memory error injection test method according to claim 4, characterized in that, Determining the test result of this error injection test based on the return status of the read operation further includes: If the return status indicates a read failure, the exception handling process in the firmware is executed to obtain the data recovery result; If the data recovery result indicates that the data recovery was successful, the test result of this error injection test is determined to be that the flash memory is normal; If the data recovery result indicates that data recovery has failed, it is determined that the test result of this error injection test indicates that there is an anomaly in the exception handling process.

6. The flash memory error injection test method according to claim 4, characterized in that, The error monitoring for the error injection test includes: The error injection test is monitored using an input / output testing tool or a serial port.

7. The flash memory error injection test method according to claim 1, characterized in that, The preset test parameters also include the error injection step size; The step of performing multiple error injection tests on the target block according to preset test parameters to obtain the test results of each error injection test includes: The test begins with an initial error ratio, and the error ratio is increased sequentially according to the error injection step size for the next error injection test, until the test result of the current error injection test indicates failure. The error ratio corresponding to the failure indicated by the test result is determined as the error tolerance threshold of the target block.

8. The flash memory error injection test method according to claim 1, characterized in that, The method further includes at least one of the following: The preset test parameters include the write position, and the write positions of at least two of the error injection tests are different; The preset test parameters include the number of writes, and the number of writes in at least two of the error injection tests is different; The preset test parameters include an interval time, which is the interval between two adjacent write operations, and the interval time of at least two error injection tests is different.

9. The flash memory error injection test method according to claim 1, characterized in that, The flash memory is a storage medium in a solid-state drive, and the method further includes at least one of the following: The preset test parameters include ambient temperature. The solid-state drive is placed in a temperature and humidity control device, and the ambient temperature inside the temperature and humidity control device is controllable. The ambient temperature is different for at least two of the error injection tests. The preset test parameters include ambient humidity. The solid-state drive is placed in a temperature and humidity control device, and the ambient humidity inside the temperature and humidity control device is controllable. The ambient humidity is different in at least two of the error injection tests. The preset test parameters include electric field strength. The solid-state drive is placed in an electromagnetic field control device, and the electric field strength in the electromagnetic field control device is controllable. The electric field strength of at least two of the error injection tests is different. The preset test parameters include magnetic field strength. The solid-state drive is placed in an electromagnetic field control device, and the magnetic field strength in the electromagnetic field control device is controllable. The magnetic field strength of at least two of the error injection tests is different.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the flash memory error injection test method as described in any one of claims 1 to 9 when executing the computer program.

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