A low inductance stack assembly method for a pulse power module

Abstract

The present application belongs to the field of printed circuit and its assembly manufacturing, and discloses a low-inductance lamination assembly method of a pulse power module, comprising: placing power semiconductor devices and decoupling capacitors in the same plane into the cavity of a core substrate; laminating an insulating layer and selectively opening a window by using a closed-loop control method based on plasma spectrum monitoring; and finally forming a bridging conductive layer directly across the top terminal of the element by metal deposition. The present application reuses the lamination step as the forming process of the key electrical connection, reduces the dimension of the traditional three-dimensional commutation loop to quasi-two-dimensional plane in topology, breaks the current path geometry mutation and inductance bottleneck caused by vertical vias, and establishes a structural foundation for improving the electrical performance and electromagnetic compatibility of the module.

Description

Technical Field

[0001] This invention relates to a low-inductance stack-up assembly method for pulse power modules, belonging to the technical field of printed circuits and their components. Background Technology

[0002] Currently, with the widespread adoption of wide-bandgap semiconductor devices, especially silicon carbide devices, the switching frequency and power density of power electronic modules have been improved. This has placed demands on the suppression of parasitic inductance in the high-frequency commutation circuits within the modules. The technical approach is to achieve this by shortening the physical distance between power semiconductor devices and high-frequency decoupling capacitors. As a result, the assembly method of three-dimensional vertical stacking on printed circuit boards or substrates has become the mainstream and continuously optimized technical direction.

[0003] However, when this vertical stacking method is pushed to higher frequencies and densities, the change in the geometry of the current path leads to electromagnetic field concentration, thereby generating parasitic inductance. The current working path within the module inevitably needs to contract from a wide two-dimensional conductor plane, such as the pads of a device, into an approximately one-dimensional linear vertical interconnect structure, such as the pins of a via or stacked busbar, and then expand to another two-dimensional conductor plane, such as the pads of a capacitor. This abrupt change in geometry from surface to line and back to surface physically constitutes a bottleneck in the current path, leading to current congestion and magnetic field concentration, making the vertical interconnect structure itself an unavoidable concentrated source of parasitic inductance.

[0004] To alleviate this problem, the most direct approach is to continuously optimize the vertical interconnect structure, such as using shorter and thicker vias or connecting multiple vias in parallel. However, this does not change the fundamental nature that the current path must undergo geometrical abrupt changes, and its optimization effect has physical limits and diminishing marginal benefits. Another approach is to use more complex multilayer copper busbars, but this increases the manufacturing complexity and cost of the module, making it difficult to popularize in cost-sensitive applications. Specifically, existing technologies have the following shortcomings: 1. The topology of the current path is limited by three-dimensional stacking, and its inherent geometrical abrupt changes are the root cause of parasitic inductance; 2. Optimization of the vertical interconnect structure is caught in a trade-off between performance and cost; 3. The potential of existing printed circuit manufacturing processes has not been fully explored, and they are essentially fixed as structural tools for achieving three-dimensional stacking rather than functional means for reconstructing loop topology. Therefore, how to break free from the mindset of continuous optimization in the vertical direction and instead utilize the characteristics of printed circuit manufacturing technology itself to construct a low-inductance commutation loop with a more ideal topology that avoids geometrical abrupt changes in the current path has become the technical problem to be solved by this invention. Summary of the Invention

[0005] This invention provides a low-inductance stacked assembly method for pulse power modules. Its main purpose is to solve the problem of parasitic inductance caused by the geometrical abrupt change in the commutation circuit current path due to the use of three-dimensional vertical stacking in the prior art.

[0006] To achieve the above objectives, the present invention provides a low-inductance stack-up assembly method for a pulse power module, the method comprising the following steps: Step a: Prepare a core substrate with a cavity, and place the power semiconductor device and the decoupling capacitor into the cavity respectively, so that the top terminals of the power semiconductor device and the top terminals of the decoupling capacitor are coplanar with the surface of the core substrate. Step b: On the core substrate and the embedded power semiconductor device and decoupling capacitor, a laminating insulating layer is stacked to cover the top terminals of the power semiconductor device and the top terminals of the decoupling capacitor. Step c: Laser ablation is used to selectively remove the portion of the insulating layer located directly above the top terminal to form a connection window. During the removal of the insulating layer, the optical characteristics of the plasma generated by the removal process are monitored in real time. When the intensity of the characteristic spectral lines of the metal elements constituting the top terminal is detected to reach the determination threshold, the removal process at that location is automatically terminated. Step d involves depositing metal on the surface of the insulating layer and within the connection window to form a bridging conductive layer that directly electrically connects the top terminals of the power semiconductor device and the corresponding top terminals of the decoupling capacitor, thereby forming a low-inductance circuit in the critical commutation circuit that does not contain vias penetrating the substrate.

[0007] Preferably, the bridging conductive layer is a composite structure, which includes a resistive material layer in contact with the top terminal, a dielectric material layer covering the resistive material layer, and a main conductive material layer covering the dielectric material layer.

[0008] Preferably, the low-inductance circuit is a quasi-two-dimensional planar circuit, in which a bridging conductive layer serves as the current path and a bottom conductive layer located below the bridging conductive layer within the core substrate serves as the current loop.

[0009] Preferably, step d, which involves depositing metal on the surface of the insulating layer and within the connection window, specifically includes: first, chemically depositing a conductive seed layer on the surface of the insulating layer and the inner wall of the connection window; then, electroplating to allow the metal layer to grow upward from the top terminal through the connection window and finally extend laterally on the surface of the insulating layer to form a bridging conductive layer.

[0010] Preferably, the composite structure allows the main conductive material layer to form the main path of a low-inductance circuit for DC or power frequency currents; while for high-frequency oscillating currents generated during the switching transients of power semiconductor devices, the resistive material layer and the dielectric material layer together form a distributed energy dissipation path in parallel with the main path.

[0011] Preferably, the core substrate is a metal substrate, and in the step of embedding the power semiconductor device coplanarly in step a, the heat dissipation surface of the power semiconductor device is fixed to the metal bottom of the cavity to establish a heat dissipation path.

[0012] Preferably, the method further includes the step of patterning the bridging conductive layer to form a circuit pattern after forming the bridging conductive layer.

[0013] Preferably, the coplanar state refers to the absolute value of the height difference between the top terminal of the power semiconductor device and the top terminal of the decoupling capacitor relative to the surface of the core substrate, which is less than 20% of the thickness of the insulating layer after lamination and curing.

[0014] Preferably, the contact interface between the bridging conductive layer and the top terminal is a solderless direct metallized connection interface.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. A cavity for accommodating electrical components is formed on the core substrate, and power semiconductor devices and decoupling capacitors are placed coplanarly within it. This series of operations makes the top terminals of each discrete component form a flat reference surface. In the subsequent lamination step, the superimposed conductive layer directly bridges and connects these coplanar terminals, transforming the traditional circuitous path of current transmission between different layers via vertical vias into a wide-body conductor directly connected in a single plane. As a result, the geometry of the high-frequency commutation circuit is no longer a three-dimensional loop with Z-axis jumps, but is physically constrained into a quasi-two-dimensional planar structure. Abrupt changes and congestion in the current path are avoided, and the electromagnetic field of the circuit is also changed, establishing a structural foundation for the overall electrical performance of subsequent modules that is different from existing technologies.

[0016] 2. When step c is changed to first stacking an insulating layer to cover all components, and then selectively opening windows and building a bridging conductive layer by additive manufacturing, the primary task of the lamination is no longer to achieve electrical connection simultaneously. Instead, it utilizes the fluidity of the prepreg to completely replicate and solidify the height inconsistencies caused by the components' own tolerances and assembly errors under a flat insulating layer. Subsequent laser windowing and electroplating deposition are performed on this solidified substrate with a defined morphology. This arrangement of separating the adaptation of mechanical morphology and the construction of electrical connection in sequence and using different processes makes the reliability of the final connection no longer subject to the initial physical height of the components. The entire manufacturing method thus has the ability to accept fluctuations in upstream component materials and mounting processes.

[0017] 3. In the step of applying the bridging conductive layer, if a multi-layer composite structure is adopted, that is, the resistive material, dielectric material and main conductive material are stacked in sequence and pressed together, then the bridging conductor itself transcends the simple path function. For the DC or power frequency main current in the module operation, it mainly flows through the low impedance main conductive layer; while for the high-frequency oscillating current generated by switching transients, the resistive and dielectric material layers in the composite structure form a distributed energy dissipation path in parallel with it. This frequency-selective response formed inside the interconnect structure makes the high-frequency noise suppression function integrated into the basic electrical connection, avoiding the need to set up separate RC components and their introduced secondary parasitic parameters to solve the oscillation problem, so that the integration degree and high-frequency electrical performance of the module are synergistically improved. Attached Figure Description

[0018] Figure 1 A schematic diagram of the process flow for constructing the quasi-two-dimensional planar commutation circuit of this invention; Figure 2 This diagram demonstrates the effectiveness of the present invention in suppressing switching voltage overshoot and oscillation. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the present invention will be described in detail below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] This invention discloses a low-inductance stacked assembly method for a pulsed power module. The process involves first embedding power semiconductor devices and decoupling capacitors in a coplanar manner, and then using the stacking and metallization process in printed circuit manufacturing technology to directly generate a planar, wide-body bridging conductive layer on the top of the device, thereby constructing a high-frequency commutation circuit. The method mainly includes stages such as preparing a core substrate with a cavity and embedding electrical components in a coplanar manner, stacking an insulating layer and selectively opening windows using a closed-loop feedback controlled laser ablation process, and constructing a bridging conductive layer by additive metal deposition.

[0021] In a specific application, this method is used to manufacture high-power-density silicon carbide power modules for main drive inverters in new energy vehicles. These modules require suppressing the parasitic inductance of the commutation circuit to below 1nH at switching frequencies of several hundred kilohertz to control voltage overshoot and reduce switching losses. To achieve this, the existing vertical stacking structure suffers from geometrical abrupt changes in the current path, which is a concentrated source of inductance and fails to meet design requirements. Therefore, the method of this invention provides a manufacturing path that circumvents this problem at the topology level. The specific steps are as follows: First, step a is performed to prepare a core substrate with cavities, and power semiconductor devices and decoupling capacitors are placed into the cavities, such that the top terminals of the power semiconductor devices and the top terminals of the decoupling capacitors are coplanar with the surface of the core substrate. This step aims to provide a foundation for all subsequent... The stacking and connection process establishes a unified, high-precision mechanical reference surface. In one embodiment, an aluminum nitride ceramic-based copper clad laminate (AMB) with a thermal conductivity of not less than 150 W / (m·K) is selected as the core substrate, with a copper layer thickness of 0.3 mm. Using a picosecond laser with a focused spot diameter of 25 μm, two shallow cavities with a depth of 0.8 mm are fabricated on the top copper foil and ceramic layer of the core substrate. Their planar dimensions match the contours of the power semiconductor device and decoupling capacitor to be embedded, with tolerances controlled within ±20 μm. Subsequently, a 50 μm thick silver sintering paste is applied to the bottom of the cavity using an automated dispensing device, and the aforementioned devices and capacitors are mounted into the corresponding cavities. The heat dissipation surface of the power semiconductor device is fixed to the metal bottom of the cavity to establish a heat dissipation path. After 250... After the sintering process at 10MPa pressure, the components are firmly fixed. At this time, by measuring with a laser profilometer, it can be confirmed that the absolute value of the height difference between the top terminal of the power semiconductor device and the top terminal of the decoupling capacitor relative to the surface of the core substrate is less than 20% of the final thickness of the insulating layer after pressing and curing, for example, less than 20μm, thus achieving a coplanar state.

[0022] Following step b, an insulating layer is laminated onto the core substrate and the embedded power semiconductor devices and decoupling capacitors to cover the top terminals of the power semiconductor devices and decoupling capacitors. The purpose of this step is to utilize the flowability of the prepreg material under hot pressing to accommodate and cure any microstructure inconsistencies that may exist in the previous process, thereby generating a flat working surface upon which subsequent fine processing depends. Specifically, a high-frequency prepreg with a cured thickness of 100 μm is covered onto the core substrate after component embedding. Then, this laminated assembly is placed in a vacuum laminator at 200°C. Temperature and The prepreg is hot-pressed and cured for 90 minutes under pressure. During this process, the resin of the prepreg flows fully, filling all the gaps around the components and adhering tightly to the top terminal surfaces of all components. Regardless of any micron-level deviation in its original height, a robust and highly flat insulating top layer is formed after curing.

[0023] Then, step c is executed, using laser ablation to selectively remove the portion of the insulating layer directly above the top terminal to form a connection window. To address the difficulty in precisely controlling the processing depth in open-loop laser processing due to material thickness fluctuations or laser power drift, this step introduces a closed-loop feedback control mechanism based on physical phenomena. A small spectrometer linked to the main controller is installed in the optical path of the laser processing equipment to monitor the optical characteristics of the plasma generated by the interaction between the laser and matter in real time. In the initial stage of removing the insulating layer, the laser acts on the resin and glass fiber of the prepreg, and the plasma spectrum collected by the spectrometer mainly shows characteristic spectral lines of elements such as carbon, hydrogen, oxygen, and silicon. The control system continues ablation until the metallic elements constituting the top terminal appear in the spectrum. For example, the system detects the characteristic spectral lines of copper. When the intensity of these characteristic spectral lines reaches a preset threshold, the control system determines that the ablation process has reached the surface of the metal terminal and automatically terminates the removal process at that location. This threshold is set through a deterministic calibration procedure. During the process development phase, the spectral intensity at which the insulation layer is completely removed without damaging the copper surface is determined by ablating a known thickness of insulation layer and simultaneously performing cross-sectional metallographic analysis. This intensity is then set as the threshold for mass production. For example, the termination signal is triggered when the ratio of the copper characteristic spectral line signal intensity to the background noise reaches 5:1. In this way, the formation process of each connection window becomes an adaptive and self-terminating operation, ensuring the cleanliness of the bottom of the window and the integrity of the component terminals.

[0024] Finally, step d is performed, where a bridging conductive layer is formed by depositing metal on the surface of the insulating layer and within the connection windows. This step employs a pressureless additive manufacturing method to eliminate internal stress that may be caused by mechanical pressing and to form a solderless direct metallization connection interface. Specifically, the substrate treated in the previous step is first immersed in a chemical copper plating solution. Through chemical deposition, a conductive seed layer with a thickness of 0.5 μm is uniformly deposited on the entire flat surface of the top insulating layer and the inner walls of all connection windows. Then, the substrate is used as a cathode for pattern electroplating, so that the copper layer starts from the top terminal, which serves as the electrode, and extends through the connection windows. The electrodes grow upwards and eventually extend laterally across the surface of the insulating layer, interconnecting until a 70μm thick bridging conductive layer is formed. This bridging conductive layer directly electrically connects the top terminals of the power semiconductor device and the corresponding top terminals of the decoupling capacitor, thus forming a low-inductance loop in the critical commutation circuit that does not contain vias penetrating the substrate. This loop is a quasi-two-dimensional planar loop, in which the formed bridging conductive layer serves as the current path, and the bottom conductive layer located below the bridging conductive layer within the core substrate serves as the current loop, separated only by a thin insulating dielectric layer. Its structure is similar to a low-impedance parallel-plate transmission line, thereby reducing the loop inductance. The level is reduced to a lower level; after the bridging conductive layer is formed, it can be patterned and etched to form circuit patterns, such as precisely defining the width of the connection or creating other signal traces such as gate drives required by the module; in an embodiment aimed at further suppressing switching oscillations, the bridging conductive layer is constructed as a composite structure, which is adjusted in the metal deposition stage of step d; specifically, after the seed layer is formed by electroless copper plating, the main conductive copper layer is not directly electroplated, but a nickel-chromium alloy resistive material layer with a thickness of 5-10 μm is first deposited on the seed layer by sputtering; subsequently, chemical vapor deposition is used to deposit the resistive material... Above the first layer, a dielectric material layer with a thickness of 1-2 μm and a high dielectric constant, such as aluminum oxide, is covered. Finally, a copper conductive layer is formed on top of the dielectric material layer through an electroplating process. This composite structure allows the current to flow mainly through the low-resistance main conductive material layer for DC or power frequency currents, forming the main path of a low-inductance circuit. For high-frequency oscillating currents generated during the switching transients of power semiconductor devices, the resistive material layer and the dielectric material layer together form a distributed energy dissipation path in parallel with the main path, which can absorb oscillation energy and thus suppress electromagnetic interference without adding discrete resistor-capacitor components.

[0025] Furthermore, the method of this invention can also integrate a function for online diagnosis of the structural health status of the module. This function is implemented through its built-in control system after the module is assembled. The method includes: after each switching action of the power semiconductor device, using the existing sensing pins on the gate driver chip, acquiring an oscillation residual signal with a duration of 50ns from the voltage signal across the power semiconductor device at a sampling rate of not less than 1GSa / s; the digital signal processing unit within the controller extracts the characteristic frequency of the oscillation residual signal by executing a fast Fourier transform algorithm. During the initial factory testing of the module, its characteristic frequencies in a brand-new state are recorded as the health baseline frequencies. ,For example =250MHz, and set a relative threshold for degradation judgment. Stored in non-volatile memory, for example =5%; During the long-term operation of the module, the controller periodically extracts the current... and with Compare, when the conditions are met At that time, for example, the current measurement =235MHz, calculated If the value is greater than 0.05, the controller determines that the internal interconnect structure of the module may be deteriorating due to thermal fatigue or mechanical stress, and sends a warning maintenance signal to the upper-level system controller. This process transforms an electrical noise signal into an indicator reflecting the structural health status, providing the possibility of predictive maintenance for critical application scenarios. The core of structural health status determination lies in a differential comparison logic that excludes the influence of operating conditions. That is, in the final testing stage before the module leaves the factory, the health baseline frequency under a single operating condition is not only recorded. Instead, it operates within a preset operating temperature and bus voltage range, for example, -40°C. Up to 125 A scanning test was conducted from 600V to 900V to collect the characteristic frequencies corresponding to different operating conditions, thereby constructing a two-dimensional lookup table or polynomial fitting model to describe the functional relationship between the characteristic frequencies and temperature T and voltage V. It is then stored in non-volatile memory; during the long-term operation of the module, the controller acquires the current oscillation aftershock signal and extracts its characteristic frequency. Simultaneously, the real-time temperature of the module substrate is also collected. and DC bus voltage Then, by calling the model, the expected characteristic frequencies that the module should have when it is in a healthy state under the current operating conditions are calculated. Ultimately, the condition used to determine whether structural degradation has occurred is based on the normalized deviation between the current frequency and the expected frequency, i.e., when the following conditions are met... Only under this condition is it determined that the internal interconnect structure of the module has undergone irreversible physical degradation.

[0026] Example 1: This example is a specific operational instance of the technical solution described above in a particular scenario. In a manufacturing project for a high-density blade server power module designed for a supercomputing center, the technical challenge is that when multiple power modules operate in parallel at high physical density, even if the voltage overshoot of a single module is controlled within a safe threshold, the high-frequency electromagnetic noise generated by their respective switching transients will superimpose in space, forming a continuous broadband electromagnetic interference background, which in turn leads to occasional logic errors in adjacent data processing units. In this project, the low-inductance stacked assembly method of the present invention is used to manufacture the power module. When performing step a, coplanar embedding of electrical components, due to the incoming power semiconductor devices and the outgoing... The coupling capacitors themselves have manufacturing tolerances, and the thickness of the silver sintering paste at the bottom of the cavity also fluctuates during mounting, causing the top terminals of each component to not be in an ideal coplanar position. If the conductive layer is directly laminated for connection, terminals that are too high will bear stress, while terminals that are too low may form a loose connection. This dependence on mechanical precision limits the process window and yield of mass production. This solution first laminates a pure insulating layer in step b, completely replicating and solidifying all height inconsistencies caused by tolerances and assembly errors under a flat insulating layer. This step uses the insulating layer to solidify the actual physical position of the components, so that subsequent electrical connections are no longer directly constrained by the initial height deviation of the components.

[0027] Furthermore, this method of first solidifying the morphology with an insulating layer provides a stable processing base for the subsequent closed-loop controlled laser ablation process based on plasma spectral monitoring in step c. Since the absolute height of the underlying component terminals is no longer a variable affecting connection quality, the closed-loop controlled laser ablation process can focus its control on ensuring the cleanliness and undamaged state of the bottom of each connection window, thus providing a high-quality starting interface for additive metal deposition in step d. These two steps are interconnected in terms of process: the deterministic morphology created in step b enables the effective execution of closed-loop control in step c, while the interface quality ensured by step c guarantees the reliability of the solderless direct metallization connection formed in step d. When the power module manufactured using this method is finally completed and put into operation... During operation, the geometry of its internal critical commutation loop is no longer the traditional three-dimensional loop where current must contract from a wide pad into an approximately linear vertical via and then expand to another pad. Instead, a quasi-two-dimensional planar loop formed by bridging the conductive layer and the bottom conductive layer allows current to flow continuously within a wide conductor. Therefore, the parasitic inductance previously associated with the vertical via is no longer a major influencing factor in this loop. Correspondingly, the distribution of its high-frequency electromagnetic field also changes, with the magnetic field confined between two parallel conductive planes, reducing outward radiation intensity. Ultimately, blade server racks deploying this type of power module experience a reduction in overall electromagnetic interference background levels, and the previously sporadic data processing unit logic errors no longer occur, improving the overall system stability.

[0028] Example 2: To quantitatively evaluate the impact of the low-inductance stack-up assembly method of the present invention on the key electrical performance of the pulse power module, a set of comparative experiments were conducted. Two half-bridge power module sample groups were prepared for the experiment: a control group using traditional surface mount technology (SMT) and via interconnection, and an experimental group using the method of the present invention. It should be noted that both sample groups used identical silicon carbide MOSFET devices and high-frequency decoupling capacitors, and were tested under the same gate drive parameters, so that the package assembly structure was the only variable. The experiment was conducted on a standard dual-pulse test platform, which consisted of a DC power supply providing up to 1000V, a 100μH load inductor, and the corresponding gate drive circuit. The data acquisition equipment included an oscilloscope with a bandwidth of 1GHz, a high-voltage differential probe with a bandwidth of 400MHz, and a Rogowski coil current probe with a bandwidth of 200MHz. The test operating parameters were set as follows: DC bus voltage 800V, turn-off current 100A, gate drive voltage +18V / -3V, and ambient temperature 25°C. This operating condition is designed to simulate the working state of silicon carbide devices in applications such as main inverters for electric vehicles.

[0029] During the experiment, a double-pulse gate signal was applied to both the control group and the experimental group, and the drain-source voltage during the turn-off period of the second pulse was accurately captured. and drain current The transient waveforms; from the acquired waveforms, it was observed that at the moment of turn-off, the two sample groups... Both waveforms exhibited voltage overshoot and subsequent oscillations. Analysis of the waveform data revealed that the control group experienced a drain-source voltage overshoot of 128V at a current change rate of 2550 A / ns, while the experimental group, at a similar current change rate of 2610 A / ns, only experienced a voltage overshoot of 25V. Based on the formula... The calculated parasitic inductance of the commutation circuit was approximately 5.02 nH in the control group and 0.96 nH in the experimental group. This reduction in inductance is due to the quasi-two-dimensional planar circuit constructed by the method of this invention, which structurally eliminates the geometric abrupt changes in the current path caused by vertical vias. Its current loop area is smaller than the loop area formed by the current having to jump between different layers of the circuit board through vias in the control group. Experimental data shows that, under the same test conditions, the parasitic inductance of the key commutation circuit of the power module assembled using the method of this invention is reduced by about 80% compared with the module assembled using the traditional vertical interconnection method. Correspondingly, the voltage overshoot during the switching process is also suppressed.

[0030] Example 3: This example combines Figures 1 to 2 A method for assembling a low-inductance stacked module for a pulse power module is described, such as... Figure 1As shown, the process begins with a core substrate, power semiconductor devices, and decoupling capacitors as core inputs. Step a is performed first, fabricating a core substrate with cavities and embedding components coplanarly. The purpose is to establish a unified and high-precision mechanical reference surface. Next, step b is performed, where an insulating layer is laminated onto the substrate with embedded components. This step aims to utilize the fluidity of the insulating material to cover and solidify the microstructure caused by assembly tolerances, thereby forming a flat working surface. Then, step c is performed, selectively opening windows in the insulating layer to expose the underlying component terminals. The unique feature of this step is the use of a closed-loop control method based on plasma spectral monitoring. By monitoring the plasma spectrum generated during the ablation process in real time, when the plasma spectrum is detected... The ablation process automatically terminates when the intensity of the characteristic spectral lines representing the terminal metal reaches a preset threshold, thus forming a high-precision connection window. Next, step d is executed, where a bridging conductive layer is constructed through additive metal deposition. The purpose is to form a solderless, directly metallized quasi-two-dimensional planar loop. After the bridging conductive layer is formed, the final process, patterning etching, can be performed to form a fine circuit pattern and optimize the high-frequency current distribution. Through the above series of steps, a low-inductance pulse power module is finally produced. Furthermore, by utilizing the structural characteristics of this module, an online diagnostic function for the structural health status can be realized. That is, by extracting the characteristic frequency of the oscillation residual signal of the switching transient and comparing it with the health baseline, it can be determined whether the module's structure has deteriorated.

[0031] like Figure 2 As shown in the figure, the vertical axis represents the drain-source voltage. The unit is volts (V), and the horizontal axis is time (nanoseconds (ns). The solid line in the figure represents the module using the traditional vertical interconnect method; at the moment of shutdown, its... The voltage experienced a severe overshoot from the 800V bus voltage level, with a peak value exceeding 925V, accompanied by prolonged, high-amplitude oscillations. In stark contrast, the module represented by the dashed line, which employs the low-inductance stack-up assembly method of this invention, exhibited suppressed voltage overshoot under the same test conditions, with a peak value of only about 825V, and the subsequent oscillations were rapidly attenuated. This comparative result demonstrates the effectiveness of the method of this invention in suppressing parasitic inductance and switching noise.

[0032] Example 4: This example aims to supplement the explanation of the key process parameter calibration and functional module implementation logic in the aforementioned technical solution. In the manufacturing process of a pulse power module for an aerospace power conversion system, high requirements are placed on process stability and module reliability; even minor process deviations can lead to potential failure risks. In this manufacturing context, to ensure that the laser ablation process in step c terminates precisely at the interface between the insulating layer and the metal terminal at each connection window, a calibration procedure for determining the plasma spectral characteristic threshold needs to be established. This procedure is executed in an offline process development phase, and its steps are as follows: First, prepare multiple test samples with the same structure as the actual product and perform steps a and b on them; second, set a laser energy density gradient, and... arrive Within the scope, To achieve the step-by-step process, laser pulses of different energy densities are used to ablate the connection windows in different regions. Simultaneously, the signal intensity ratio of the characteristic spectral lines of copper representing the metal terminal and the characteristic spectral lines of carbon representing the insulating layer in the plasma spectrum generated during the ablation process is recorded at each energy density. Finally, cross-sectional analysis of each ablated window is performed using a scanning electron microscope to determine the energy density point that completely removes the insulating layer without causing microscopic damage to the copper surface below. The spectral signal intensity ratio corresponding to this point, 10:1, is set as the threshold for automatically terminating the ablation process on the mass production line.

[0033] Furthermore, this embodiment describes the internal algorithm logic path of the function used to diagnose the health status of the module structure. During the initial power-on test of the module, the control system collects the oscillation aftershock signal under healthy conditions and performs a Fast Fourier Transform to obtain a frequency domain energy spectrum. Given that the physical structure of the module determines that its intrinsic oscillation frequency falls within a predictable range, the algorithm first applies a digital bandpass filter with a passband of 150MHz to 350MHz to filter out DC components and high-frequency noise interference. Subsequently, the algorithm searches for the frequency point with the maximum energy amplitude in the filtered spectrum data and records this frequency point as the healthy baseline frequency. In subsequent long-term operation, this process is repeated periodically to obtain the current characteristic frequency. And through judgment Whether it holds true or not is used to determine the structural health status of the module; the setting of this prior frequency band enables the algorithm to stably and unambiguously lock the effective frequency as a health status indicator from the noisy background.

[0034] Furthermore, this embodiment provides an engineering design method for selecting the resistive material layer of the composite structure bridging conductive layer to suppress switching oscillations. The goal is to enable the distributed RC network built into the composite structure to effectively dampen the RLC oscillations of the commutation circuit. The first step of this method is to obtain the equivalent output capacitance of the power semiconductor device at the target operating voltage using a network analyzer. The measured value under this operating condition is 300pF; it is known that the method of the present invention can reduce the parasitic inductance of the commutation circuit. The stability is maintained at around 1nH; the characteristic impedance of this RLC circuit is... The calculated resistance is approximately 1.83Ω. To achieve near-critical damping to attenuate oscillations, a parallel resistor equivalent to the characteristic impedance needs to be introduced. For a bridging conductive layer with a current path length of 10mm and a width of 5mm, the sheet resistance of the required resistive material can be calculated to be 0.915Ω / sq. Therefore, during manufacturing, an embedded resistive film with a sheet resistance closest to this calculated value is selected as the resistive material layer in the composite structure. This procedure transforms the material selection from relying on empirical trial and error to a calculation process based on device physical characteristics and circuit theory.

[0035] Example 5: In the mass production process of a pulse power module, to ensure that its built-in structural health status diagnostic function has consistent criteria across different production batches, a pre-deployment calibration procedure needs to be executed to set a health baseline frequency. In this procedure, at least 5% of the samples are randomly selected from the modules of the same production batch and run on a standardized power-on test platform under rated operating conditions for a short period of aging screening. Then, the oscillation aftershock signal after the switching action of each sample module is collected, and its initial characteristic frequency is extracted according to the algorithm logic. Finally, the arithmetic mean of the initial characteristic frequencies of all samples is calculated, and this average value is used as the health baseline frequency for the entire production batch. The program is written into the non-volatile memory of all modules in this batch.

[0036] To determine a relative threshold for degradation assessment of the diagnostic function This requires the execution of a parameter calibration procedure based on accelerated aging tests. In this procedure, a subset of the samples that have already undergone initial characteristic frequency calibration are selected for accelerated thermal cycling aging tests, with the test conditions set at -40°C. Up to 125 Rapid temperature cycling was performed between samples; during the experiment, the sample was removed after every 100 cycles, and its current characteristic frequency was measured on a standard test bench. Simultaneously, ultrasonic scanning microscopy was used to examine the internal structure for early failure signs such as microcracks or delamination. This experiment established a correlation between the characteristic frequency drift and the timing of internal microstructural damage. The statistical average of the frequency drift corresponding to the first observation of repeatable early failure signs was used as the relative threshold for determining degradation. The basis for this is that when the average drift is 5%, then... Set to 5%.

[0037] Example 6: In the production introduction process of applying the assembly method of the present invention to a new type of power semiconductor device, in order to ensure the accurate adaptation of manufacturing parameters and the stability of the production process, a system deployment pre-calibration procedure needs to be executed. The first step of this procedure is to determine the cavity depth used to achieve the coplanar state. The calculation method is to add the nominal device height specified in the datasheet of the new type of power semiconductor device to the nominal thickness of the conductive adhesive after curing, and then subtract a planarization correction amount reserved for subsequent stacking processes. This planarization correction amount is set to 10% of the thickness of the insulating layer after curing used in subsequent step b. The cavity depth calculated in this way allows the top terminal surface of the component to be slightly lower than the surface of the core substrate after embedding, providing process margin for resin flow and final planarization of the insulating layer during the pressing process. In order to cope with the possible micron-level component position offset during the component mounting process in step a, ... To address the issue of the laser ablation target deviating from the center of the top terminal of the component in step c, an online quality monitoring and anomaly detection logic was added to the closed-loop control logic. This logic, in addition to monitoring whether the intensity of the characteristic spectral lines of the metal element in the plasma spectrum reaches the judgment threshold, simultaneously calculates the time from the start of ablation to the appearance of the metal characteristic spectral lines and accumulates the total signal integral value of the metal characteristic spectral lines during the ablation process. By ablating and collecting data on normal windows and windows with various known offsets during the process development stage, a statistical distribution model of the aforementioned time parameters and signal integral values ​​can be established. During mass production, if the ablation time or signal integral value of a certain window deviates from the normal range defined by this statistical model by more than three standard deviations, the control system marks the module as a suspected defect and sends it to the manual re-inspection station, thereby preventing connection defects caused by component placement misalignment from flowing into subsequent processes.

[0038] In one specific embodiment of the present invention, after the deposition of the bridging conductive layer is completed in step d, the step of patterning the bridging conductive layer is not only to form the auxiliary circuit patterns such as gate drive and signal sensing required by the module, but also to perform final geometric optimization on the conductor portion carrying the main commutation current. Specifically, the design of the etched pattern follows a principle that, while meeting the electrical clearance requirements, the projected overlap area between the current path forming the quasi-two-dimensional planar loop and the loop conductor is maximized. The corners of the etched pattern are rounded using electromagnetic field simulation software to suppress the current congestion effect. In this way, the patterning etching step is transformed from a standard circuit manufacturing process into a functional step for finely controlling the high-frequency current distribution and further reducing the local inductive reactance of the loop.

[0039] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A low-inductance stacked assembly method for a pulse power module, characterized in that, The method includes the following steps: Step a: Prepare a core substrate with a cavity, and place the power semiconductor device and the decoupling capacitor into the cavity respectively, so that the top terminals of the power semiconductor device and the top terminals of the decoupling capacitor are coplanar with the surface of the core substrate. Step b: On the core substrate and the embedded power semiconductor device and decoupling capacitor, a laminating insulating layer is stacked to cover the top terminals of the power semiconductor device and the top terminals of the decoupling capacitor. Step c: Laser ablation is used to selectively remove the portion of the insulating layer located directly above the top terminal to form a connection window. During the removal of the insulating layer, the optical characteristics of the plasma generated by the removal process are monitored in real time. When the intensity of the characteristic spectral lines of the metal elements constituting the top terminal is detected to reach the determination threshold, the removal process at that location is automatically terminated. Step d involves depositing metal on the surface of the insulating layer and within the connection window to form a bridging conductive layer that directly electrically connects the top terminals of the power semiconductor device and the corresponding top terminals of the decoupling capacitor, thereby forming a low-inductance circuit in the critical commutation circuit that does not contain vias penetrating the substrate.

2. The low-inductance stacked assembly method for a pulse power module according to claim 1, characterized in that, The bridging conductive layer is a composite structure, which includes a resistive material layer in contact with the top terminal, a dielectric material layer covering the resistive material layer, and a main conductive material layer covering the dielectric material layer.

3. The low-inductance stacked assembly method for a pulse power module according to claim 1, characterized in that, The low-inductance circuit is a quasi-two-dimensional planar circuit. The quasi-two-dimensional planar circuit is formed by the bridging conductive layer as the current path and the bottom conductive layer located below the bridging conductive layer in the core substrate as the current loop.

4. The low-inductance stacked assembly method for a pulse power module according to claim 1, characterized in that, Step d, which involves depositing metal on the surface of the insulating layer and within the connection window to form a bridging conductive layer, specifically includes: first, chemically depositing a conductive seed layer on the surface of the insulating layer and the inner wall of the connection window; then, electroplating to allow the metal layer to grow upward from the top terminal through the connection window and finally extend laterally on the surface of the insulating layer to form a bridging conductive layer.

5. A low-inductance stacked assembly method for a pulse power module according to claim 2, characterized in that, The composite structure allows the main conductive material layer to form the main path of a low-inductance circuit for DC or power frequency currents; while for the high-frequency oscillating current generated during the switching transients of power semiconductor devices, the resistive material layer and the dielectric material layer together form a distributed energy dissipation path in parallel with the main path.

6. The low-inductance stacked assembly method for a pulse power module according to claim 1, characterized in that, The core substrate is a metal substrate, and in step a, the power semiconductor device is embedded in the coplanar surface, and the heat dissipation surface of the power semiconductor device is fixed to the metal bottom of the cavity.

7. The low-inductance stacked assembly method for a pulse power module according to claim 1, characterized in that, The method also includes a step of patterning the bridging conductive layer to form a circuit pattern after the bridging conductive layer is formed.

8. A low-inductance stacked assembly method for a pulse power module according to claim 1, characterized in that, Coplanar state refers to the absolute value of the height difference between the top terminal of the power semiconductor device and the top terminal of the decoupling capacitor relative to the surface of the core substrate, which is less than 20% of the thickness of the insulating layer after lamination and curing.

9. A low-inductance stacked assembly method for a pulse power module according to claim 1, characterized in that, The contact interface between the bridging conductive layer and the top terminal is a solderless, direct metallized connection interface.

Images