Integration method of thin film transistor-based complementary circuit

Abstract

The invention provides an integration method of a thin film transistor-based complementary circuit, and belongs to the field of integrated circuit micro-nano electronic devices. The thin film transistor-based complementary circuit comprises a P-type TFT and an N-type TFT, the electrodes of the P-type TFT and the N-type TFT are interconnected, and the P-type TFT and the N-type TFT can realize two-dimensional coplanar integration in the same substrate plane to form a planar CMOS circuit; and a three-dimensional integrated structure can be formed through multilayer stacking on the surface of the substrate, so that a monolithic three-dimensional CMOS integrated circuit is realized. The invention is not only suitable for an inverter, but also can be expanded to a NAND gate, a NOR gate, a trigger and a storage array, and further constructs a processor unit (CPU), a sensing circuit and a system-on-chip (SoC).

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuit micro-nano electronic devices, and particularly relates to an integration technology of thin film transistor-based complementary circuit. BACKGROUND

[0002] Thin film transistor (TFT) is a key device in display technology, flexible electronics and low-temperature integrated circuits. To meet the development needs of flexible and low-temperature electronics, TFT devices often need to be prepared on temperature-sensitive substrates such as glass or polyimide (PI), and the process temperature generally should not exceed 400-500 ℃ to maintain the mechanical and chemical stability of the substrate.

[0003] Existing TFT inverter circuits are mostly based on a single material system (such as polycrystalline silicon or all-oxide semiconductor). However, in the process of silicon-based TFT, a heat treatment step with a temperature higher than 600 ℃ is usually required, which is not suitable for low-temperature substrates. Although oxide TFT has the advantage of low-temperature process, it mainly presents N-type characteristics and lacks stable P-type devices, making it difficult to form a complete complementary logic circuit. The limitations of this material system significantly restrict the integration of high-performance, scalable CMOS circuits under low-temperature conditions.

[0004] In recent years, germanium-based materials have become an important research direction in the field of TFT due to their excellent hole mobility and P-type conductivity. Through techniques such as metal-induced crystallization (MIC), high-quality crystalline germanium films can be obtained at relatively low temperatures, thereby realizing P-type TFT devices compatible with flexible and low-temperature processes. This provides the possibility for the heterogeneous integration of oxide N-type TFTs.

[0005] However, current researches mostly still remain at the device level, lacking overall integration schemes for circuits and systems, especially in terms of how to efficiently realize complementary logic circuit design, improve circuit integration and functional expandability. Therefore, it is necessary to explore a heterogeneous integration method based on P-type germanium-based TFT and N-type oxide TFT, and further propose an integration technology suitable for planar

[0006] CMOS circuits and monolithic three-dimensional CMOS circuits, which is of great significance for promoting the development of low-temperature flexible electronics. SUMMARY

[0007] The present application provides an integration method of complementary circuit based on P-type germanium-based thin film transistor and N-type oxide thin film transistor. This method can realize the planar integration and monolithic three-dimensional integration of heterogeneous materials under low-temperature substrate conditions, thereby breaking through the limitations of existing TFT circuits in process temperature, material properties and functional expansion.

[0008] The technical scheme of the present application is as follows:

[0009] An integrated method of a thin film transistor-based complementary circuit, characterized in that the thin film transistor-based complementary circuit comprises electrode-interconnected P-type TFT and N-type TFT, wherein the P-type TFT comprises a substrate, a gate electrode, a gate dielectric layer, a P-type active layer and source / drain electrodes arranged in sequence, the P-type active layer is formed of a germanium-based material, the N-type TFT comprises a substrate, a gate electrode, a gate dielectric layer, an N-type active layer and source / drain electrodes arranged in sequence, the N-type active layer is an oxide semiconductor material, and the specific steps comprise:

[0010] 1) cleaning the substrate;

[0011] 2) the specific steps for preparing the P-type TFT include deposition and patterning of the gate electrode, the gate dielectric layer, the P-type active layer and the source / drain electrodes, wherein the low-temperature crystallization is realized at a temperature not higher than 400 DEG C by using a metal-induced crystallization (MIC) process after deposition of the germanium-based material;

[0012] 3) the specific steps for preparing the N-type TFT include deposition and patterning of the gate electrode, the gate dielectric layer, the N-type active layer and the source / drain electrodes;

[0013] 4) post-annealing at a temperature not higher than 300 DEG C;

[0014] 5) electrode interconnection, and completion of the thin film transistor-based complementary circuit.

[0015] Further, the P-type TFT and the N-type TFT are integrated in two dimensions in the same plane to form a planar CMOS circuit, or a three-dimensional integrated structure is formed by stacking multiple layers on the surface of the substrate to realize a monolithic three-dimensional CMOS integrated circuit.

[0016] Further, the P-type active layer adopts a germanium-silicon alloy (Si 1-x Ge x ), which can be formed by physical vapor deposition (such as sputtering), chemical vapor deposition (CVD), atomic layer deposition (ALD) and the like. The thickness of the P-type active layer is 5-100 nanometers.

[0017] Further, the N-type active layer adopts zinc oxide (ZnO) or a multi-element oxide material mainly composed of ZnO, such as indium-gallium-zinc oxide (IGZO), which is deposited by sputtering, ALD or CVD. The thickness of the N-type active layer is 5-100 nanometers.

[0018] Further, the gate electrode is made of one or more of the following: aluminum, titanium, molybdenum, gold, palladium, platinum, tantalum, or a combination thereof, or one or more of the following: transparent conductive film indium tin oxide (ITO), aluminum zinc oxide (AZO), or a conductive film, and is formed by sputtering or evaporation.

[0019] Further, the gate dielectric layer is made of aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), or a high-k dielectric material such as doped Al2O3, HfO2, TiO2, and has a thickness of 10-300 nanometers and is formed by sputtering, ALD or CVD.

[0020] Further, the source / drain electrode is made of one or more of the following: aluminum, titanium, molybdenum, gold, palladium, platinum, tantalum, or a combination thereof, or one or more of the following: transparent conductive film indium tin oxide (ITO), aluminum zinc oxide (AZO), or a conductive film, and is formed by sputtering or evaporation. The source / drain electrode has a thickness of 10-500 nanometers.

[0021] Further, the substrate is made of glass, polyimide, or other flexible or temperature-sensitive substrates, so as to realize complementary circuit integration in a heterogeneous material system.

[0022] The complementary circuit of the present application is composed of P-type TFT and N-type TFT in a complementary relationship, and can realize integration of a logic functional unit. Both the P-type TFT and the N-type TFT device adopt a bottom gate structure, and the complementary connection between devices is realized by electrodes or wiring. In terms of circuit integration, the P-type TFT and the N-type TFT can be two-dimensionally co-planarly integrated in the same substrate plane to form a planar CMOS circuit, or can be three-dimensionally stacked on the surface of the substrate to form a three-dimensional integrated structure, so as to realize a monolithic three-dimensional CMOS integrated circuit, thereby significantly improving the integration density in a limited area. The present application is not only suitable for inverters, but also can be extended to NAND gates, NOR gates, flip-flops, memory arrays, and further to processor units (CPU), sensing circuits and system on chip (SoC).

[0023] The advantages of the present application are as follows:

[0024] (1) Heterogeneous material structure compatibility design, realizing heterogeneous integration of complementary TFTs;

[0025] (2) Low-temperature process of no more than 400 degrees Celsius, good compatibility with glass, plastic, polyimide and other flexible or temperature-sensitive substrates;

[0026] (3) Extensible to more complex complementary logic circuits and functional modules. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1The complementary circuit structure diagram provided by the present invention includes: (a) a complementary inverter circuit; (b) a bottom-gate TFT structure; (c) a two-dimensional planar CMOS inverter structure; and (d) a three-dimensional stacked CMOS structure diagram.

[0028] Figure 2 A schematic diagram of the low-temperature preparation process steps used in this invention.

[0029] Figure 3 The voltage transfer characteristics of the two-dimensional planar inverter prepared according to a specific embodiment of the present invention.

[0030] Figure 4 The static voltage gain of the two-dimensional planar inverter prepared in a specific embodiment of the present invention.

[0031] Figure 5 The static power consumption of the two-dimensional planar inverter prepared in a specific embodiment of the present invention.

[0032] Figure 6 The noise margin of the two-dimensional planar inverter prepared in a specific embodiment of the present invention.

[0033] Figure 7 The dynamic response characteristics of the two-dimensional planar inverter prepared according to a specific embodiment of the present invention.

[0034] The diagram is labeled as follows: 1—substrate; 2—bottom gate electrode; 3—bottom gate dielectric; 4—active layer; 5—source / drain electrode. Detailed Implementation

[0035] The invention will be further described below with reference to the accompanying drawings and examples.

[0036] like Figure 1 As shown, this invention provides an integration method for a complementary circuit based on P-type germanium-based thin-film transistors and N-type oxide thin-film transistors. In a specific embodiment, a two-dimensional planar CMOS inverter circuit is used as an example, wherein the P-type TFT acts as a pull-up transistor and the N-type TFT acts as a pull-down transistor. Figure 1 As shown in (a), both are bottom-gate structures, sequentially comprising a substrate, a bottom gate electrode, a bottom gate dielectric, an active layer, and source / drain electrodes, as follows. Figure 1 As shown in (b). The active layer of the P-type TFT is a germanium-based thin film (with Si). 1-x Ge x Taking a pure germanium thin film with x=1 as an example, its crystallization process employs metal-induced crystallization (MIC) technology, using aluminum as the metal; the active layer of the N-type TFT is an oxide semiconductor (taking zinc oxide as an example). In terms of circuit connection, the gate interconnection between the P-type and N-type TFTs serves as the inverter input (V... IN Its drain interconnect serves as the output terminal of the inverter (V). OUT), the source of the P-type TFT is connected to a power supply voltage terminal (V DD ), the source of the N-type TFT is grounded (GND), thereby constructing a CMOS inverter logic unit, as shown in Figure 1 (c). On this basis, the integrated scheme of the present application is not limited to two-dimensional planar circuits. On the basis of two-dimensional coplanar integration, the P-type TFT and the N-type TFT can also be implemented in a multi-layer stacked manner to achieve three-dimensional monolithic integration, as shown in Figure 1 (d), which can significantly improve the circuit integration.

[0037] This embodiment takes a two-dimensional planar CMOS inverter circuit as an example, in which the P-type TFT and the N-type TFT are in the same plane, and the gate electrode, gate dielectric layer, source / drain electrode of the P-type TFT and the gate electrode, gate dielectric layer, source / drain electrode of the N-type TFT are prepared at the same time, the process steps are as shown in Figure 2 , mainly including:

[0038] 1) substrate cleaning;

[0039] 2) bottom gate electrode deposition and patterning;

[0040] 3) bottom gate dielectric layer deposition and patterning;

[0041] 4) P-type active layer deposition (using germanium-based material, and low-temperature crystallization is realized at no more than 400°C through metal-induced crystallization process);

[0042] 5) N-type active layer deposition (using zinc oxide or multi-element oxide semiconductor);

[0043] 6) source / drain electrode deposition and patterning;

[0044] 7) post-annealing process (no more than 300°C) to improve contact characteristics and electrical stability;

[0045] 8) electrode interconnection, completing the construction of the inverter circuit.

[0046] In a specific embodiment of the present application, the voltage transfer characteristic (VTC) of the prepared inverter is as shown in Figure 3 . The VTC curve shows obvious level inversion characteristics, with a relatively steep transition edge, indicating that the inverter has good switching characteristics and static voltage transfer performance. In a specific embodiment of the present application, the static voltage gain of the prepared inverter is as shown in Figure 4 . At V DD = 3V, the maximum static gain of the inverter reaches 4.24V / V, indicating that the inverter has good amplification capability and can effectively enhance the input signal, which is conducive to realizing the cascade driving of multi-stage complementary logic circuits. In a specific embodiment of the present application, the static power consumption of the prepared inverter is as shown in Figure 5As shown. In V DD At 3V, the power consumption is 94μW. In a specific embodiment of the present invention, the noise margin of the fabricated inverter is as follows: Figure 6 As shown. In V DD At 3V, its high-level input noise margin (NM) H The low-level input noise margin is 0.61V (Nm). L The noise margin is 0.47V. This level of noise margin indicates that the device has good noise immunity and can tolerate large input voltage disturbances without affecting the correctness of the logic function. In a specific embodiment of the present invention, the dynamic response characteristics of the fabricated inverter are as follows: Figure 7 As shown. In V DD At 3V and with an input signal frequency of 1kHz, the measured rise time was 46.50μs and the fall time was 6.70μs.

[0047] Therefore, the complementary circuit integration method proposed in this invention is applicable to the implementation of two-dimensional CMOS inverter circuits. Figure 3 – Figure 7 The experimental results can also be extended to three-dimensional integrated structures, and further extended to various application scenarios such as logic gate arrays, memory units, processor circuits and sensing circuits.

[0048] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A method of integrating thin film transistor based complementary circuits, characterized by: The thin film transistor-based complementary circuit comprises electrode-interconnected P-type TFT and N-type TFT, wherein the P-type TFT comprises substrate, gate electrode, gate dielectric layer, P-type active layer and source / drain electrode arranged in sequence, the P-type active layer is formed by germanium-based material, the N-type TFT comprises substrate, gate electrode, gate dielectric layer, N-type active layer and source / drain electrode arranged in sequence, the N-type active layer is oxide semiconductor material, and the specific steps comprise: 1) cleaning the substrate; 2) the specific steps for preparing the P-type TFT comprise: gate electrode, gate dielectric layer, P-type active layer and source / drain electrode deposition and patterning, wherein the low-temperature crystallization of the germanium-based material is realized at a temperature not higher than 400 DEG C by using metal-induced crystallization process after the deposition of the germanium-based material; 3) the specific steps for preparing the N-type TFT comprise: gate electrode, gate dielectric layer, N-type active layer and source / drain electrode deposition and patterning; 4) post-annealing at a temperature not higher than 300 DEG C; 5) electrode interconnection, and the thin film transistor-based complementary circuit is completed.

2. The method of Claim 1, wherein: The P-type TFT and the N-type TFT are integrated in the same plane to form a planar CMOS circuit, or a three-dimensional integrated structure is formed by stacking multiple layers on the surface of the substrate to realize a monolithic three-dimensional CMOS integrated circuit.

3. The method of Claim 2, wherein: The P-type TFT and the N-type TFT are in the same plane, and the gate electrode, the gate dielectric layer, the source / drain electrode of the P-type TFT and the gate electrode, the gate dielectric layer, the source / drain electrode of the N-type TFT are prepared at the same time, and the specific steps comprise: 1) cleaning the substrate; 2) gate electrode and gate dielectric layer deposition and patterning; 3) the P-type active layer is made of germanium-based material, and the low-temperature crystallization of the germanium-based material is realized at a temperature not higher than 400 DEG C by using metal-induced crystallization process after the deposition of the germanium-based material; 4) depositing oxide semiconductor material as the N-type active layer; 5) source / drain electrode deposition and patterning; 6) post-annealing at a temperature not higher than 300 DEG C; 7) electrode interconnection, and the thin film transistor-based complementary circuit is completed.

4. The method of Claim 1, wherein: the thin film transistor-based complementary circuit is integrated on a single substrate. The germanium-based material is germanium-silicon alloy, which is formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition method, and the thickness of the P-type active layer ranges from 5 nm to 100 nm.

5. The method of Claim 1, wherein: the thin film transistor-based complementary circuit is integrated on a single substrate. The oxide semiconductor material is zinc oxide ZnO or multi-element oxide material mainly composed of ZnO, which is deposited by sputtering, ALD or CVD method, and the thickness of the N-type active layer ranges from 5 nm to 100 nm.

6. The method of Claim 1, wherein: the thin film transistor-based complementary circuit is integrated on a single substrate. The gate electrode is made of one or more of the following combinations of metals: aluminum, titanium, molybdenum, gold, palladium, platinum, tantalum, or one or more of the following combinations of transparent conductive thin films: indium tin oxide, aluminum zinc oxide conductive thin film, which is deposited by sputtering or evaporation method, and the thickness of the gate electrode ranges from 10 nm to 500 nm.

7. The method of Claim 1, wherein: the thin film transistor-based complementary circuit is integrated on a single substrate. The gate dielectric layer is made of one or more of the following high-k dielectric materials: aluminum oxide, hafnium oxide, titanium oxide, or doped Al2O3, HfO2, TiO2, and the thickness of the gate dielectric layer ranges from 10 nm to 300 nm, which is deposited by sputtering, ALD or CVD method.

8. The integration method of the thin-film transistor-based complementary circuit as described in claim 1, characterized in that: The source / drain electrode is made of one or more of the following metals: aluminum, titanium, molybdenum, gold, palladium, platinum, tantalum, etc., or one or more of the following transparent conductive films: indium tin oxide, aluminum zinc oxide, etc., and is deposited by sputtering or evaporation. The thickness of the source / drain electrode is in the range of 10-500 nm.

9. The method of Claim 1, wherein: the thin film transistor-based complementary circuit is integrated on a single substrate. The substrate is made of glass, polyimide or a temperature-sensitive substrate.

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