A single-photon avalanche detector with high detection efficiency and a preparation method thereof

Abstract

The application discloses a single-photon avalanche detector with high detection efficiency and a preparation method thereof. The single-photon avalanche detector comprises, from bottom to top, a semi-insulating substrate, an n+InGaAs substrate epitaxial layer, an n+InAlAs substrate epitaxial layer, an i:InAlAs epitaxial multiplication layer, a p+InAlAs charge layer, an InAlAs / InAlGaAs superlattice gradient layer, an InAlGaAs / InGaAs superlattice absorption layer, a p+:InAlAs epitaxial layer and a p+:InP epitaxial layer. The InAlAs / InAlGaAs superlattice gradient layer is arranged in a periodic cycle, and the InAlGaAs / InGaAs superlattice absorption layer is arranged in a periodic cycle. Compared with the prior art, the application can improve the quantum efficiency of the device, increase the width of the depletion region, reduce the electric field of the absorption layer and improve the carrier collection efficiency.

Description

Technical Field

[0001] This invention relates to the technical field of single-photon avalanche detectors, and in particular to a high-efficiency single-photon avalanche detector and its fabrication method. Background Technology

[0002] Detection efficiency is an important indicator of single-photon avalanche detectors, characterizing the photoelectric detection capability of the device. Detection efficiency is the product of several efficiency indicators, including quantum efficiency, the probability of holes being injected into the multiplication region, the probability of holes triggering avalanches in the multiplication layer, and the probability of avalanches being detected. Therefore, detection efficiency is usually improved by increasing the quantum efficiency of the device. However, the quantum efficiency of traditional InGaAs SPADs in the industry is generally below 30%, which is due to: (1) to avoid a sharp increase in tunneling dark count, the absorption layer thickness is ≤1.5um; (2) large carrier transport loss, with a collection efficiency of less than 80%. Summary of the Invention

[0003] The purpose of this invention is to address the shortcomings of existing technologies by providing a high-efficiency single-photon avalanche detector and its fabrication method. To improve quantum efficiency, the absorption layer and gradient layer in the epitaxial structure are replaced with a superlattice structure, which can improve the quantum efficiency of the device, increase the width of the depletion region, reduce the electric field of the absorption layer, and improve the carrier collection efficiency.

[0004] To achieve the above objectives, the technical solution provided by this invention is as follows: a high-efficiency single-photon avalanche detector, comprising, from bottom to top, a semi-insulating substrate, an n+InGaAs epitaxial layer, an n+InAlAs epitaxial layer, an i:InAlAs epitaxial multiplication layer, a p+InAlAs charge layer, an InAlAs / InAlGaAs superlattice graded layer, an InAlGaAs / InGaAs superlattice absorption layer, a p+:InAlAs epitaxial layer, and a p+:InP epitaxial layer; wherein the InAlAs / InAlGaAs superlattice... The gradient layer comprises several cyclically arranged InAlGaAs monolayers and InAlAs monolayers, wherein the Al composition of each InAlGaAs monolayer decreases gradually according to a preset first rule, until the Al composition of the last InAlGaAs monolayer decreases to 0.24; the InAlGaAs / InGaAs superlattice absorption layer comprises several cyclically arranged InGaAs monolayers and InAlGaAs monolayers, wherein the Al composition of each InAlGaAs monolayer increases gradually from 0 to 0.24 according to a preset second rule.

[0005] Furthermore, the first rule includes:

[0006] In the first cycle, the Al component gradually changes from 0.48 to X1; in the second cycle, the Al component gradually changes from X1 to X2; until the last cycle, the Al component gradually changes from Xn-1 to 0.24.

[0007] Furthermore, the second rule includes:

[0008] For each InAlGaAs monolayer, the Al composition near the InGaAs monolayer is 0, increasing to 0.24 as the thickness increases. Specifically: in the first InGaAlAs monolayer, the Al composition gradually changes from 0.24 to 0; in the second InGaAlAs monolayer, the Al composition gradually changes from 0 to 0.24; if the last period is an odd-numbered period, the Al composition of the InAlGaAs monolayer gradually changes from 0.24 to 0; if the last period is an even-numbered period, the Al composition gradually changes from 0 to 0.24.

[0009] Furthermore, the semi-insulating substrate is an InP substrate, and the size of the semi-insulating substrate is 2-4 inches.

[0010] Further, the n+InGaAs substrate epitaxial layer is a Si-doped n+InGaAs substrate epitaxial layer with a thickness of 200-1000 nm; the n+InAlAs substrate epitaxial layer is a Si-doped n+InAlAs substrate epitaxial layer with a thickness of 200-800 nm; the i:InAlAs epitaxial multiplication layer is an intrinsically doped i:InAlAs epitaxial multiplication layer with a thickness of 300-1500 nm; according to claim 1, a high-efficiency single-photon avalanche detector is characterized in that: the p+InAlAs charge layer is a Zn-doped p+InAlAs charge layer with a thickness of 50-300 nm.

[0011] Furthermore, in the InAlAs / InAlGaAs superlattice graded layer, the thickness of the InAlGaAs monolayer is 2-10 nm, and the thickness of the InAlAs monolayer is 2-10 nm; in a single period, the InAlGaAs monolayer is grown on top of the InAlAs monolayer, the superlattice period ranges from 4 to 30 periods, and the thickness of the InAlAs / InAlGaAs superlattice graded layer is 80-150 nm.

[0012] Furthermore, in the InAlGaAs / InGaAs superlattice absorption layer, the thickness of the InAlGaAs monolayer is 5-10 nm, and the thickness of the InGaAs monolayer is 5-10 nm; in a single period, the InGaAs monolayer is grown on top of the InAlGaAs monolayer, and the superlattice period ranges from 30 to 100 periods.

[0013] Furthermore, the p+:InAlAs epitaxial layer is a Zn-doped p+:InAlAs epitaxial layer with a thickness of 300-1000 nm; the p+:InP epitaxial layer is an intrinsically doped p+:InP epitaxial layer with a thickness of 2000-4000 nm.

[0014] Furthermore, a first Zn diffusion hole and a second Zn diffusion hole are provided on the p+:InP epitaxial layer, wherein the first Zn diffusion hole is a deep diffusion hole and the second Zn diffusion hole is a shallow diffusion hole, and the diameter of the deep diffusion hole is smaller than the diameter of the shallow diffusion hole.

[0015] A method for fabricating a high-detection-efficiency single-photon avalanche detector as described above includes the following steps:

[0016] S1. Transfer the substrate into the MOCVD cavity. The substrate is a semi-insulating InP substrate with a coverage size of 2-4 inches.

[0017] S2. Grow an n+InGaAs epitaxial layer on the substrate to form a low-resistance ohmic contact with the underlying metal electrode. Temperature: 590–650℃; Thickness: 200–1000 nm; Si doping concentration: 1 × 10⁻⁶. 18 ~1×10 19 cm -3 ;

[0018] S3. Grow an n+InAlAs epitaxial layer on an n+InGaAs substrate epitaxial layer, restricting lateral electron flow, at a temperature of 570–650℃, a thickness of 200–800 nm, and a Si doping concentration of 8 × 10⁻⁶. 17 ~5×10 18 cm -3 ;

[0019] S4. An i:InAlAs epitaxial multiplication layer is grown on the n+InAlAs substrate epitaxial layer as the main region where the avalanche multiplication effect occurs. The temperature is 570-650℃ and the thickness is 300-1500nm. The i:InAlAs epitaxial multiplication layer is intrinsically doped.

[0020] S5. Grow a p+InAlAs charge layer on the i:InAlAs epitaxial multiplication layer to control the electric field of the i:InAlAs epitaxial multiplication layer and the superlattice absorption layer. The temperature is 570–650℃, the thickness is 50–300 nm, and the Zn doping concentration is 6 × 10⁻⁶. 16 ~5×10 17 cm -2 Surface density range: 2–2.5 × 10⁻⁶ 12 cm -3 ;

[0021] S6. An InAlAs / InAlGaAs superlattice graded layer is grown on the p+InAlAs charge layer to filter dislocations, wherein In... 0.52 AlAs layer temperature 570–650℃, thickness 2–10 nm, In 0.53 Ga x Al y The As layer temperature is 490–550℃, and the thickness is 2–10 nm. The Al composition is adjusted to regulate the band gap. In the first period, the Al composition gradually changes from 0.48 to X1; in the second period, the Al composition gradually changes from X1 to X2, until the last period when the Al composition gradually changes from Xn-1 to 0.24. The superlattice period is 4–30, and the thickness of the graded layer ranges from 80–150 nm.

[0022] S7. An InAlGaAs / InAlGaAs superlattice absorption layer is grown on an InAlAs / InAlGaAs superlattice graded layer. In the first period, the Al composition of the InGaAlAs layer gradually decreases from 0.24 to 0. In the second period, the Al composition gradually decreases from 0 to 0.24. If the last period is an odd-numbered period, the Al composition of the InAlGaAs layer gradually decreases from 0.24 to 0; if the last period is an even-numbered period, the Al composition gradually decreases from 0 to 0.24. The temperature is 490–550℃, and the thickness is 5–10 nm. 0.52 GaAs layer temperature 570~650℃, thickness 5~10nm, period 30~100;

[0023] S8. Grow a p+:InAlAs epitaxial layer on the InAlGaAs / InGaAs superlattice absorber layer to confine hole diffusion. Temperature: 570–650℃; Thickness: 300–1000 nm; Zn doping concentration: 1×10⁻⁶. 17 ~1×10 18 cm -3 ;

[0024] S9. Grow a p+:InP epitaxial layer on the p+:InAlAs epitaxial layer for Zn diffusion at a temperature of 550–620℃ and a thickness of 2000–4000 nm. The p+:InP epitaxial layer is intrinsically doped.

[0025] S10. After surface organic cleaning on the p+:InP epitaxial layer, a high-temperature resistant dielectric film SiNx or SiO2 is grown, and then diffusion holes are formed by photolithography etching process.

[0026] S11. The epitaxial wafer with diffusion holes is fed into MOCVD for a Zn deep diffusion. The distance between the first central junction and the p+:InAlAs epitaxial layer is 0.5~1um.

[0027] S12. Grow a second high-temperature resistant dielectric film SiNx or SiO2, and form a diffusion hole through photolithography etching process. The diameter of the diffusion hole is smaller than the diameter of the first diffusion hole described in step S10.

[0028] S13. The epitaxial wafer is fed into MOCVD for secondary shallow Zn diffusion. The depth of the second central junction is 0.5 to 1 μm shallower than the depth of the first central junction described in step S11.

[0029] S14. Remove the high-temperature resistant dielectric film and grow the passivation layer;

[0030] S15. A metal contact area is formed on the passivation layer by photolithography etching, and then a contact electrode is formed by evaporation using EB electron beam or magnetron sputtering technology to form the device.

[0031] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0032] 1. In this invention, the original absorption layer is replaced with a superlattice structure, which can maintain a large depletion region width while keeping the electric field of the absorption layer low. This improves quantum efficiency while avoiding interband tunneling (BTBT) and dark counting.

[0033] 2. In this invention, the original gradient layer is replaced with a superlattice structure to improve carrier collection efficiency, thereby improving the overall quantum efficiency of the device. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of the present invention.

[0035] Figure 2 This is a schematic diagram of the InAlAs / InAlGaAs superlattice gradient layer.

[0036] Figure 3 This is a schematic diagram of the InAlGaAs / InGaAs superlattice absorption layer.

[0037] Figure 4 This is a schematic diagram of the structure of the first and second Zn diffusion pores. Detailed Implementation

[0038] The present invention will be further described below with reference to specific embodiments.

[0039] See Figure 1 As shown, the high-efficiency single-photon avalanche detector provided in this embodiment includes, from bottom to top, a semi-insulating substrate 1, an n+InGaAs epitaxial layer 2, an n+InAlAs epitaxial layer 3, an i:InAlAs epitaxial multiplication layer 4, a p+InAlAs charge layer 5, an InAlAs / InAlGaAs superlattice graded layer 6, an InAlGaAs / InGaAs superlattice absorption layer 7, a p+:InAlAs epitaxial layer 8, and a p+:InP epitaxial layer 9. The n+InGaAs epitaxial layer 2, n+InAlAs epitaxial layer 3, i:InAlAs epitaxial multiplication layer 4, p+InAlAs charge layer 5, InAlAs / InAlGaAs superlattice graded layer 6, InAlGaAs / InGaAs superlattice absorption layer 7, p+:InAlAs epitaxial layer 8, and p+:InP epitaxial layer 9 are all grown using metal-organic chemical vapor deposition (MOCVD) technology.

[0040] The semi-insulating substrate 1 is an InP substrate that is introduced into the MOCVD cavity, and the size of the semi-insulating substrate 1 is 2-4 inches.

[0041] The n+InGaAs substrate epitaxial layer 2 is a Si-doped n+InGaAs substrate epitaxial layer 2, used to form a low-resistance ohmic contact with the underlying metal electrode. Its temperature is 590–650℃, and the Si doping concentration is 1×10⁻⁶. 18 ~1×10 19 cm -3 The thickness of the n+InGaAs substrate epitaxial layer 2 is 200-1000nm.

[0042] The n+InAlAs substrate epitaxial layer 3 is a Si-doped n+InAlAs substrate epitaxial layer 3, which serves to restrict the lateral flow of electrons. Its temperature ranges from 570 to 650°C. The thickness of the n+InAlAs substrate epitaxial layer 3 is 200-800 nm, and the Si doping concentration is 8 × 10⁻⁶. 17 ~5×10 18 cm -3 .

[0043] The i:InAlAs epitaxial multiplication layer 4 is an intrinsically doped i:InAlAs epitaxial multiplication layer, which is the main region where the avalanche multiplication effect occurs. Electrons or holes are accelerated by a high electric field here and gain sufficient energy to generate new electron-hole pairs through collisional ionization, thereby achieving internal amplification of the photocurrent. Its temperature is 570-650℃, and the thickness of the i:InAlAs epitaxial multiplication layer 4 is 300-1500nm.

[0044] The p+InAlAs charge layer 5 is a Zn-doped p+InAlAs charge layer 5, which functions to modulate the electric field of the multiplication layer and the superlattice absorption layer. Its temperature is 570–650℃, and the thickness of the p+InAlAs charge layer 5 is 50–300 nm, with a Zn doping concentration of 6 × 10⁻⁶. 16 ~5×10 17 cm -2 Surface density range: 2–2.5 × 10⁻⁶ 12 cm -3 .

[0045] See Figure 2 As shown, the InAlAs / InAlGaAs superlattice graded layer 6 comprises several periodically arranged InAlGaAs monolayers and InAlAs monolayers, which serve to filter dislocations. Furthermore, the bandgap gradient introduces a built-in electric field, both of which improve carrier collection efficiency and indirectly enhance quantum efficiency. In the InAlAs / InAlGaAs superlattice graded layer 6, In... 0.52 AlAs layer temperature 570–650℃, thickness 2–10 nm, In 0.53 Ga x Al y The As layer is grown at a temperature of 490–550 °C and a thickness of 2–10 nm. The Al composition is adjusted to regulate the band gap. In the first cycle, the Al composition gradually changes from 0.48 to X1; in the second cycle, it changes from X1 to X2, and so on, with the final cycle showing an Al composition that gradually changes from Xn-1 to 0.24. Within a single cycle, an InAlGaAs monolayer is grown on top of another InAlAs monolayer. The superlattice period ranges from 4 to 30 cycles, and the thickness of the InAlAs / InAlGaAs superlattice graded layer 6 is 80–150 nm.

[0046] See Figure 3 As shown, the InAlGaAs / InGaAs superlattice absorber layer 7 comprises several cyclically arranged InGaAs and InAlGaAs monolayers. The superlattice introduces a built-in electric field, increasing diffusion intensity, widening the depletion region, suppressing dark counting, and improving quantum efficiency. In the InAlGaAs / InGaAs superlattice absorber layer 7, the Al composition of the first InGaAlAs layer gradually decreases from 0.24 to 0, the Al composition of the second layer gradually decreases from 0 to 0.24, and if the last period is odd, the Al composition of the InAlGaAs layer gradually decreases from 0.24 to 0; if the last period is even, the Al composition gradually decreases from 0 to 0.24. The temperature is 490–550℃, and the thickness is 5–10 nm. 0.52The GaAs layer temperature is 570–650 °C; in a single cycle, the InGaAs monolayer is grown on top of the InAlGaAs monolayer, and the superlattice cycle ranges from 30 to 100 cycles.

[0047] The p+:InAlAs epitaxial layer 8 is a Zn-doped p+:InAlAs epitaxial layer 8, which restricts hole diffusion. The thickness of the p+:InAlAs epitaxial layer 8 is 300-1000 nm, and the Zn doping concentration is 1×10¹⁷~1×10¹⁸ cm⁻³.

[0048] The p+:InP epitaxial layer 9 is an intrinsically doped p+:InP epitaxial layer 9 used for Zn diffusion at a temperature of 550–620℃, and its thickness is 2000–4000 nm. After surface organic cleaning on the p+:InP epitaxial layer 9, a high-temperature resistant dielectric film SiNx or SiO2 is grown, and then diffusion holes are formed by photolithography etching. The epitaxial wafer with diffusion holes is then fed into an MOCVD for the first Zn diffusion (deep diffusion), with the center junction distance from the p+:InAlAs epitaxial layer 0.5–1 μm. A second high-temperature resistant dielectric film SiNx or SiO2 is then grown, and diffusion holes are formed by photolithography etching. The epitaxial wafer is then fed into an MOCVD for the second Zn diffusion (shallow diffusion), with the depth of the second junction being 0.5–1 μm shallower than the depth of the first junction. See [link to relevant documentation]. Figure 4 As shown, the diameter of the deep diffusion hole is smaller than that of the shallow diffusion hole. Then, the dielectric film is removed, and a passivation layer is grown. On the passivation layer, a metal contact area is formed by photolithography etching. Then, a contact electrode is formed by evaporation using EB electron beam or magnetron sputtering technology to form a usable device.

[0049] The above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Therefore, any changes made in accordance with the shape and principle of the present invention should be covered within the protection scope of the present invention.

Claims

1. A high-efficiency single-photon avalanche detector, characterized in that: The structure comprises, from bottom to top, a semi-insulating substrate, an n+InGaAs epitaxial layer, an n+InAlAs epitaxial layer, an i:InAlAs epitaxial multiplication layer, a p+InAlAs charge layer, an InAlAs / InAlGaAs superlattice graded layer, an InAlGaAs / InGaAs superlattice absorber layer, a p+:InAlAs epitaxial layer, and a p+:InP epitaxial layer; the InAlAs / InAlGaAs superlattice graded layer comprises several cyclically arranged InAlGaAs monolayers and InAlAs monolayers, wherein the Al composition of each period's InAlGaAs monolayer gradually decreases according to a predetermined first rule, until the Al composition of the last period's InAlGaAs monolayer decreases to 0.24; the InAlGaAs / InGaAs superlattice absorber layer... It includes several InGaAs monolayers and InAlGaAs monolayers arranged in a cyclical pattern. For each InAlGaAs monolayer, the Al composition near the InGaAs monolayer is 0, and increases to 0.24 as the thickness increases. Specifically: in the first InAlGaAs monolayer, the Al composition gradually changes from 0.24 to 0; in the second InAlGaAs monolayer, the Al composition gradually changes from 0 to 0.24; if the last period is an odd-numbered period, the Al composition of the InAlGaAs monolayer gradually changes from 0.24 to 0; if the last period is an even-numbered period, the Al composition gradually changes from 0 to 0.

24.

2. The high-efficiency single-photon avalanche detector according to claim 1, characterized in that, The first rule includes: In the first cycle, the Al component gradually changes from 0.48 to X1; in the second cycle, the Al component gradually changes from X1 to X2; until the last cycle, the Al component gradually changes from Xn-1 to 0.

24.

3. The high-efficiency single-photon avalanche detector according to claim 1, characterized in that: The semi-insulating substrate is an InP substrate, and the size of the semi-insulating substrate is 2-4 inches.

4. A high-efficiency single-photon avalanche detector according to claim 1, characterized in that: The n+InGaAs substrate epitaxial layer is a Si-doped n+InGaAs substrate epitaxial layer with a thickness of 200-1000 nm; the n+InAlAs substrate epitaxial layer is a Si-doped n+InAlAs substrate epitaxial layer with a thickness of 200-800 nm; the i:InAlAs epitaxial multiplication layer is an intrinsically doped i:InAlAs epitaxial multiplication layer with a thickness of 300-1500 nm; the p+InAlAs charge layer is a Zn-doped p+InAlAs charge layer with a thickness of 50-300 nm.

5. A high-efficiency single-photon avalanche detector according to claim 1, characterized in that: In the InAlAs / InAlGaAs superlattice graded layer, the thickness of the InAlGaAs monolayer is 2-10 nm; in a single period, the InAlGaAs monolayer is grown on top of the InAlAs monolayer, the superlattice period ranges from 4 to 30 periods, and the thickness of the InAlAs / InAlGaAs superlattice graded layer is 80-150 nm.

6. A high-efficiency single-photon avalanche detector according to claim 1, characterized in that: In the InAlGaAs / InGaAs superlattice absorption layer, the thickness of the InAlGaAs monolayer is 5-10 nm, and the thickness of the InGaAs monolayer is 5-10 nm; in a single period, the InGaAs monolayer is grown on top of the InAlGaAs monolayer, and the superlattice period ranges from 30 to 100 periods.

7. A high-efficiency single-photon avalanche detector according to claim 1, characterized in that: The p+:InAlAs epitaxial layer is a Zn-doped p+:InAlAs epitaxial layer with a thickness of 300-1000 nm; the p+:InP epitaxial layer has a thickness of 2000-4000 nm.

8. A high-efficiency single-photon avalanche detector according to claim 1, characterized in that: The p+:InP epitaxial layer is provided with a first Zn diffusion hole and a second Zn diffusion hole, wherein the first Zn diffusion hole is a deep diffusion hole and the second Zn diffusion hole is a shallow diffusion hole, and the diameter of the deep diffusion hole is larger than the diameter of the shallow diffusion hole.

9. A method for fabricating a high-detection-efficiency single-photon avalanche detector according to any one of claims 1-8, characterized in that, Includes the following steps: S1. Transfer the substrate into the MOCVD cavity. The substrate is a semi-insulating InP substrate with a coverage size of 2-4 inches. S2. Grow an n+InGaAs epitaxial layer on the substrate to form a low-resistance ohmic contact with the underlying metal electrode. Temperature: 590~650℃; Thickness: 200~1000nm; Si doping concentration: 1×10⁻⁶. 18 ~1×10 19 cm -3 ; S3. Grow an n+InAlAs epitaxial layer on an n+InGaAs substrate epitaxial layer, restricting lateral electron flow, at a temperature of 570~650℃, a thickness of 200~800nm, and a Si doping concentration of 8×10⁻⁶. 17 ~5×10 18 cm -3 ; S4. An i:InAlAs epitaxial multiplication layer is grown on the n+InAlAs substrate epitaxial layer as the main region where the avalanche multiplication effect occurs. The temperature is 570~650℃ and the thickness is 300~1500nm. The i:InAlAs epitaxial multiplication layer is intrinsically doped. S5. Grow a p+InAlAs charge layer on the i:InAlAs epitaxial multiplication layer to control the electric field of the i:InAlAs epitaxial multiplication layer and the superlattice absorption layer. The temperature is 570~650℃, the thickness is 50~300nm, and the Zn doping concentration is 6×10⁻⁶. 16 ~5×10 17 cm -3 Surface density range: 2~2.5×10 12 cm -2 ; S6. Grow an InAlAs / InAlGaAs superlattice graded layer on the p+InAlAs charge layer to filter dislocations, where In... 0.52 AlAs layer temperature 570~650℃, thickness 2~10nm, In 0.53 Ga x Al y The As layer temperature is 490~550℃, and the thickness is 2~10nm. The Al composition is adjusted to adjust the band gap. In the first period, the Al composition gradually changes from 0.48 to X1; in the second period, the Al composition gradually changes from X1 to X2, until the last period when the Al composition gradually changes from Xn-1 to 0.

24. The superlattice period is 4~30, and the thickness of the graded layer ranges from 80~150nm. S7. An InAlGaAs / InAlGaAs superlattice absorption layer is grown on an InAlAs / InAlGaAs superlattice graded layer. In the first period, the Al composition of the InAlGaAs layer gradually decreases from 0.24 to 0. In the second period, the Al composition gradually decreases from 0 to 0.

24. If the last period is odd-numbered, the Al composition of the InAlGaAs layer gradually decreases from 0.24 to 0; if the last period is even-numbered, the Al composition gradually decreases from 0 to 0.

24. The temperature is 490~550℃, and the thickness is 5~10 nm. 0.52 GaAs layer temperature 570~650℃, thickness 5~10nm, period 30~100; S8. Grow a p+:InAlAs epitaxial layer on the InAlGaAs / InGaAs superlattice absorber layer to confine hole diffusion. Temperature: 570~650℃, thickness: 300~1000nm, Zn doping concentration: 1×10⁻⁶ 17 ~1×10 18 cm -3 ; S9. Grow a p+:InP epitaxial layer on a p+:InAlAs epitaxial layer for Zn diffusion at a temperature of 550~620℃ and a thickness of 2000~4000nm. S10. After surface organic cleaning on the p+:InP epitaxial layer, a high-temperature resistant dielectric film SiNx or SiO2 is grown, and then a deep diffusion hole is formed by photolithography etching process. S11. The epitaxial wafer with deep diffusion holes is fed into MOCVD for one Zn deep diffusion. The distance between the first central junction and the p+:InAlAs epitaxial layer is 0.5~1um. S12. Grow a second high-temperature resistant dielectric film SiNx or SiO2, and form shallow diffusion holes through photolithography etching process. The diameter of the shallow diffusion holes is smaller than the diameter of the deep diffusion holes described in step S10. S13. The epitaxial wafer is fed into MOCVD for secondary shallow Zn diffusion. The depth of the second central junction is 0.5~1um shallower than the depth of the first central junction described in step S11. S14. Remove the high-temperature resistant dielectric film and grow the passivation layer; S15. A metal contact area is formed on the passivation layer by photolithography etching, and then a contact electrode is formed by evaporation using EB electron beam or magnetron sputtering technology to form the device.

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