Circuit control method for increasing signal generation speed and control device thereof

Abstract

This invention provides a circuit control method and control device for improving signal generation speed, belonging to the field of signal processing circuit technology. It includes: inputting the same reference clock to at least two FPGAs, with each FPGA performing offset correction on the received reference clock; dividing the reference clock period into several sub-cycles equal to the number of FPGAs; each FPGA generating a corresponding signal sequence within its corresponding sub-cycle of the reference clock; inputting a switching clock to a MUX, controlling the MUX to cyclically select one of the at least two FPGAs within different cycles of the switching clock and outputting its generated signal sequence to a driver; and the driver integrating all signal sequences output by the at least two FPGAs to generate an output signal. This invention significantly improves signal generation and transmission speed through the parallel division of labor among multiple FPGAs and the serialization combination of the MUX.

Description

Technical Field

[0001] This invention relates to the technical field of signal processing integrated circuits, and in particular to a circuit control method and control device for improving signal generation speed. Background Technology

[0002] Currently, in the integrated control circuits of automated test equipment (ATE) and high-speed signal test systems, the high-speed signal generation speed and signal transmission speed are limited due to the inherent speed limitation of FPGA (Field Programmable Gate Array).

[0003] Especially when testing complex systems such as high-speed memory interfaces, SerDes, and PCIe, it is often impossible to provide sufficient test signal speed.

[0004] In view of this, based on the optimized design of FPGA, a novel circuit control method and control device for improving signal generation speed are proposed to solve all or part of the above problems. Summary of the Invention

[0005] To address at least one of the aforementioned problems and deficiencies in the prior art, embodiments of the present invention provide a circuit control method and control device for improving signal generation speed. This method achieves a significant increase in signal generation and transmission speed through a combination of circuit control that combines the parallel generation of signal sequences by multiple FPGAs with the serialized output of a complete signal by a MUX. The technical solution is as follows:

[0006] According to one aspect of the present invention, a circuit control method for improving signal generation speed is provided. The circuit control method includes:

[0007] The same reference clock is input to at least two FPGAs, and each of the at least two FPGAs performs offset correction on the received reference clock.

[0008] The period of the segmented reference clock is a number of sub-cycles equal to the number of FPGAs;

[0009] Each FPGA generates a corresponding signal sequence within the corresponding sub-cycle of the reference clock;

[0010] Input a switching clock to the MUX, and control the MUX to cyclically select at least one of the corresponding FPGAs from the two FPGAs in different cycles of the switching clock and output the generated signal sequence to the driver;

[0011] The driver integrates all signal sequences from at least two FPGAs to generate the output signal.

[0012] In some embodiments, the circuit control method further includes initializing each FPGA by sending a SYNC pulse signal to each FPGA to align the clock phase of each FPGA.

[0013] In some embodiments, preferably, the timing of the triggering of the synchronization pulse signal is within the first to third cycles of the reference clock after power-on, and the pulse width of the synchronization pulse signal is 1 / 10 to 1 / 5 of each cycle of the reference clock.

[0014] In some embodiments, preferably, each FPGA uses a dynamic feedback mechanism through its internal phase-locked loop (PLL / DLL) module to monitor the clock offset between each FPGA in real time. If the clock offset is greater than 50ps, initialization is triggered to resend the synchronization pulse signal.

[0015] In some embodiments, specifically when the number of at least two FPGAs is N, the MUX is 2. K 1 MUX. 2 K :1 MUX has 2 input channels K Where N=2 K K ≥ 1 and is a positive integer. 2 K 1. The switching clock frequency of the MUX is N times the frequency of the reference clock, and the switching clock uses a phase-locked loop filter to control clock jitter to be less than or equal to 10ps RMS. 2. K :1 The gating logic of MUX follows the cyclic shift order.

[0016] In some embodiments, specifically, the driver is a slew rate adjustable DDR driver that dynamically adjusts the output impedance to 50Ω ± 5% based on the transmission line impedance. The slew rate adjustment strategy involves dynamically calculating the optimal slew rate based on the amplitude of the reflected signal after injecting a test pulse signal into the DDR driver before signal transmission.

[0017] In some embodiments, further, when an instruction to interrupt transmission is received, the FPGA is controlled to complete the signal sequence being transmitted and cache the data of the untransmitted signal sequence in its internal memory; the MUX is controlled to clear the buffer queue of the signal sequence transmission.

[0018] In some embodiments, further, when the interrupt ends, the current FPGA rereads the last 3-5 unacknowledged transmission signal sequences before the interrupt from its memory, and inserts an error verification code at the output of the MUX and sends it to the driver along with the signal sequence to be output for the driver to verify the continuity of the signal sequence.

[0019] In some embodiments, preferably, the step of each FPGA generating a corresponding signal sequence within a corresponding sub-cycle of the reference clock further includes data preloading, which involves sequentially pre-storing the signal sequence generated by each FPGA into the buffer of that FPGA. Alternatively, the buffer may be a FIFO buffer or a pipeline buffer.

[0020] According to another aspect of the present invention, a control device for improving signal generation speed is provided, which generates a high-speed signal by using the circuit control method described above. The control device includes:

[0021] The clock module is configured to input the same reference clock to at least two FPGAs and divide the period of the reference clock into a number of sub-cycles equal to the number of FPGAs.

[0022] An FPGA module is configured to include at least two FPGAs, wherein each FPGA receives the same reference clock from a clock module and then performs offset correction on the reference clock, and each FPGA generates a corresponding signal sequence within the corresponding sub-cycle of the reference clock.

[0023] The MUX module is configured to include a switching clock and a scheduling control module. The scheduling control module controls the MUX to cyclically select at least one of the corresponding FPGAs from the two FPGAs in different cycles of the switching clock and output the signal sequence it generates.

[0024] The driver module is configured to generate an output signal by integrating all signal sequences from at least two FPGAs through a driver.

[0025] The circuit control method and control device for improving signal generation speed provided by embodiments of the present invention have at least one or a portion of the following advantages:

[0026] (1) By using a combination circuit that combines the parallel generation of signal sequences by multiple FPGAs with the serialized output of the complete signal by a MUX, the speed of signal generation and transmission is improved, extending the output signal speed to 2 times that of a single FPGA. n This doubles the speed, meeting high-speed testing requirements;

[0027] (2) By using a synchronous reference clock, each FPGA can generate a synchronous signal sequence. At the same time, the signal is transmitted to the MUX and allocated bit by bit through a high-speed connection line, which helps to improve the total signal generation rate and obtain a higher signal output frequency.

[0028] (3) By configuring a transmission management feedback mechanism in the signal transmission circuit from FPGA to MUX, it is ensured that the current signal transmission is completed and the untransmitted signal data is buffered when an interrupt occurs, and that signal transmission is quickly restored after the interrupt ends;

[0029] (4) The scheduling control module is configured in the MUX to realize functions such as interrupt management, data buffering and error recovery;

[0030] (5) By switching the clock for the MUX input and setting the scheduling control module, the configuration of the MUX can be optimized to flexibly adjust the signal generation speed and the output speed to the driver, which helps to ensure compatibility under different test equipment and test requirements;

[0031] (6) By dynamically adjusting the impedance in a DDR driver with adjustable slew rate, signal reflection and loss can be effectively avoided, ensuring stable transmission and signal integrity of high-speed signals, such as during testing.

[0032] (7) By using FPGA and MUX in conjunction with high-speed transmission circuit design, it is generally applicable to high-end testing scenarios such as DRAM SLT, PCIe / USB PHY testing, and SerDes verification. Attached Figure Description

[0033] These and / or other aspects and advantages of the present invention will become apparent and readily understood from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:

[0034] Figure 1 A flowchart of a circuit control method according to an embodiment of the present invention;

[0035] Figure 2 According to Figure 1 A schematic diagram of the functional module structure of the control device designed according to the method flow diagram is shown.

[0036] Figure 3 This is a schematic diagram of the structure of a control device according to an embodiment of the present invention;

[0037] Figure 4 A schematic diagram of the circuit structure of the MUX module of a control device according to an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of the circuit structure of the drive module of a control device according to an embodiment of the present invention. Detailed Implementation

[0039] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation thereof.

[0040] It should also be understood that although the terms "first," "second," "third," etc., may be used in the following embodiments of the invention to describe a component comprising two or more of the same component, these components should not be limited to these terms. These terms are only used to distinguish each component from one another and should not be construed as a limitation of the invention.

[0041] To improve signal generation speed, embodiments of this invention propose a novel circuit control method and device. This method combines the parallel generation of signal sequences by multiple FPGAs (Field-Programmable Gate Arrays) with the serialized output of complete signals by a MUX (Multiple-Single-Output Selector), thereby increasing the speed of both signal generation and transmission. Taking an automated test equipment (ATE) as an example, this circuit control method can extend the speed of test signals from the previous method using a single FPGA to 2... n times.

[0042] According to one aspect of the present invention, a circuit control method for improving signal generation speed is provided.

[0043] See Figure 1 The flowchart of the circuit control method is shown. Specifically, it includes:

[0044] Step S101: Input the same reference clock to at least two FPGAs and each of the at least two FPGAs performs offset correction on the received reference clock;

[0045] Step S102: Divide the period of the reference clock into several sub-cycles equal to the number of FPGAs;

[0046] Step S103: Each FPGA generates a corresponding signal sequence within the corresponding sub-cycle of the reference clock;

[0047] Step S104: Input a switching clock to the MUX, and control the MUX to cyclically select at least one of the corresponding FPGAs from the two FPGAs in different cycles of the switching clock and output the signal sequence generated therefrom to the driver;

[0048] Step S105: The driver integrates all signal sequences from at least two FPGAs to generate an output signal.

[0049] In one example, the circuit control method further includes initializing each FPGA by sending a SYNC pulse signal to each FPGA to align the clock phase of each FPGA.

[0050] In one example, preferably, the timing of the synchronization pulse signal is within the first to third cycles of the reference clock after power-on, and the pulse width of the synchronization pulse signal is 1 / 10 to 1 / 5 of each cycle of the reference clock.

[0051] In one example, more preferably, each FPGA uses a dynamic feedback mechanism (e.g., RESET / READY mechanism) through its internal phase-locked loop (PLL / DLL) module to monitor the clock offset between each FPGA in real time. If the clock offset is greater than 50ps, initialization is triggered to resend the synchronization pulse signal.

[0052] In one example, furthermore, when designing the PCB circuit, it is also necessary to set the clock traces of a number of FPGAs configured in the control circuit to the same length.

[0053] In the process of initializing the synchronous reference clock and establishing the dynamic feedback mechanism, other feedback control logic can be added according to the requirements of signal transmission speed and quality. Only some illustrative examples of implementation are provided here, and those skilled in the art should not understand it as a limitation of the present invention.

[0054] In one example, preferably, the step of each FPGA generating a corresponding signal sequence in the corresponding sub-cycle of the reference clock further includes data preloading, which involves pre-storing the signal sequence generated by each FPGA into the buffer of that FPGA in sequence.

[0055] Thus, a number of FPGAs generate signal sequences at a reference clock frequency and generate corresponding bit data strictly according to the rhythm of the reference clock. Alternatively, the buffer can be a FIFO buffer or a pipeline buffer.

[0056] In one example, specifically, when the number of at least two FPGAs is N, the MUX is 2. K 1 MUX. 2 K :1 MUX has 2 input channels K Where N=2 K K ≥ 1 and is a positive integer. In this case, 2 K 1. The switching clock frequency of the MUX is N times the frequency of the reference clock. Preferably, the switching clock uses a phase-locked loop filter to control clock jitter to be less than or equal to 10ps RMS. 2. K:1 The gating logic of MUX follows the cyclic shift order.

[0057] Thus, when the control circuit is configured with N FPGAs and 2 K 1. The speed at which signals are generated using this circuit control method after the MUX is 2 times the speed when using a single FPGA. K For example, using two FPGAs requires configuring a 2:1 MUX to achieve a 2x speed increase (if a single FPGA outputs 400Mbps, the device under test will receive an 800Mbps signal), using four FPGAs requires configuring a 4:1 MUX to achieve a 4x speed increase, using eight FPGAs requires configuring an 8:1 MUX to achieve an 8x speed increase, and so on.

[0058] In one example, specifically, the driver is a slew rate adjustable DDR driver that dynamically adjusts the output impedance to 50Ω ± 5% based on the transmission line impedance. The slew rate adjustment strategy involves dynamically calculating the optimal slew rate based on the amplitude of the reflected signal after injecting a test pulse signal into the DDR driver before signal transmission. Preferably, the DDR driver supports high-speed driving, typically reaching speeds of hundreds of MHz to several GHz.

[0059] When signal transmission is interrupted, such as when the upper control system issues a command to interrupt signal transmission, or when the driver or the device under test sends a feedback signal to the MUX indicating that signal transmission needs to be interrupted, this circuit control method can also achieve data buffering during the interruption and data transmission recovery after the interruption by establishing a data scheduling and management mechanism between the FPGA and the MUX through a high-speed transmission circuit.

[0060] In one example, specifically, when an interrupt transmission instruction is received, the FPGA is controlled to complete the currently transmitting signal sequence and buffer the data of the untransmitted signal sequence into its internal memory; the MUX is controlled to clear the buffer queue of the signal sequence transmission.

[0061] Furthermore, after the interrupt ends, the current FPGA rereads the last 3-5 unacknowledged transmission signal sequences before the interrupt from its memory, and inserts an error verification code at the output of the MUX and sends it to the driver along with the signal sequence to be output so that the driver can verify the continuity of the signal sequence.

[0062] Thus, the error recovery mechanism formed by backtracking 3-5 bits of the error verification code combination can effectively solve the problem of data disorder after the interruption of multiple FPGA parallel circuits.

[0063] In one example, preferably, high-speed connection circuits or lines are used when designing the overall PCB circuit using this circuit control method, along with LVDS interfaces or high-speed I / O interfaces. Simultaneously, the high-speed circuits or lines also require, for example, differential designs to control impedance, particularly in the high-speed connection circuit from the MUX to the DDR driver, where impedance control is necessary to ensure signal transmission stability and integrity.

[0064] According to another aspect of the present invention, a control device 200 for improving the signal generation speed is provided, which generates high-speed signals by using the circuit control method described above.

[0065] See Figure 2 This shows the composition of the functional modules in the control device.

[0066] See Figure 3 The structure of a control device according to one embodiment of the circuit control method is shown. Figure 3 For example, the number of FPGAs selected is 2.

[0067] Combination Figure 2 and Figure 3 As shown, the control device 200 includes:

[0068] Clock module 210 is configured to input the same reference clock to at least two FPGAs and divide the period of the reference clock into a number of sub-cycles equal to the number of FPGAs.

[0069] FPGA module 220 is configured to include at least two FPGAs, wherein each FPGA receives the same reference clock from clock module 210 and performs offset correction on the reference clock, and each FPGA generates a corresponding signal sequence in the corresponding sub-cycle of the reference clock.

[0070] MUX module 230 is configured to include a switching clock 231 and a scheduling control module 232. The scheduling control module 232 controls the MUX to cyclically select at least one of the corresponding FPGAs from at least two FPGAs and output the signal sequence generated therefrom within different cycles of the switching clock 231.

[0071] The driver module 240 is configured to generate an output signal by integrating all signal sequences output from at least two FPGAs through the driver 241.

[0072] For example, see Figure 4 and Figure 5 The circuit structure of one embodiment of the MUX module 230 and the drive module 240 in the control device 200 is shown.

[0073] like Figure 3As shown in one example, specifically,

[0074] The FPGA module 220 contains two FPGAs, namely the first FPGA 221 and the second FPGA 222.

[0075] Correspondingly, the period of the reference clock is first divided into two sub-periods, which include an even-numbered period and an odd-numbered period. Then, the first FPGA 221 is controlled to generate a first signal sequence in the even-numbered period, and the second FPGA 222 is controlled to generate a second signal sequence in the odd-numbered period.

[0076] Specifically, the first FPGA221 generates 1 bit of data (e.g., bit 0, 2, 4, ...) in every even-numbered cycle of the reference clock; the second FPGA222 generates 1 bit of data (e.g., bit 1, 3, 5, ...) in every odd-numbered cycle of the reference clock. Both FPGAs generate data at the reference clock frequency and must strictly follow the rhythm of the reference clock to generate the bit data.

[0077] Correspondingly, the MUX at this time is a 2:1 MUX, that is, the 2:1 MUX includes two input terminals and one output terminal, and the selection of the output link is controlled by combinational logic circuits (such as controllable digital switches). The two input terminals include a first input terminal and a second input terminal. The first input terminal is connected to the output terminal of the first FPGA221 through a first high-speed connection link L1, and the second input terminal is connected to the output terminal of the second FPGA222 through a second high-speed connection link L2.

[0078] Correspondingly, the frequency of the switching clock input to the aforementioned 2:1 MUX is twice the frequency of the reference clock.

[0079] The scheduling control module 232 in the MUX module 230 controls the 2:1 MUX to run at twice the reference clock, and alternately selects the output of the first FPGA 221 and the second FPGA 222.

[0080] The specific action process of 2:1 MUX is as follows:

[0081] First cycle: Output the first data bit of FPGA221;

[0082] Second cycle: Output the data bits of the second FPGA222;

[0083] Third cycle: Output the next data bit of the first FPGA221;

[0084] Fourth cycle: Output the next data bit of the second FPGA222;

[0085] This process is repeated, with each signal sequence corresponding to a different FPGA being output sequentially through alternating selection.

[0086] By having multiple FPGAs work in parallel and generate high-speed signals for different parts through division of labor, and then serializing and outputting them through a MUX, the speed and efficiency of signal generation are greatly improved.

[0087] Each FPGA is responsible for generating a portion of the signal data (i.e., a certain signal sequence). Under the control of a synchronous reference clock, each FPGA generates signals synchronously with other FPGAs and transmits the signals to a MUX circuit with a corresponding number of input terminals via high-speed interconnects (such as LVDS interfaces). The signals of each FPGA are assigned bit by bit; for example, the first FPGA221 is responsible for the signal sequence with even bits, and the second FPGA222 is responsible for the signal sequence with odd bits.

[0088] This control circuit design solves the speed limitation of a single FPGA, significantly increasing the overall signal generation rate. Multiple FPGAs working in parallel are equivalent to stitching together multiple low-speed signals, thus achieving a higher signal output frequency.

[0089] When it is necessary to further increase the number of parallel operations on the FPGA, the aforementioned circuit control method can be referenced, with N=2. K The number of FPGAs is expanded based on K≥1 and is a positive integer, and the MUX corresponding to the number of input channels is matched to further improve the signal generation speed.

[0090] The circuit control method and control device for improving signal generation speed provided by embodiments of the present invention have at least one or a portion of the following advantages:

[0091] (1) By using a combination circuit that combines the parallel generation of signal sequences by multiple FPGAs with the serialized output of the complete signal by a MUX, the speed of signal generation and transmission is improved, extending the output signal speed to 2 times that of a single FPGA. n This doubles the speed, meeting high-speed testing requirements;

[0092] (2) By using a synchronous reference clock, each FPGA can generate a synchronous signal sequence. At the same time, the signal is transmitted to the MUX and allocated bit by bit through a high-speed connection line, which helps to improve the total signal generation rate and obtain a higher signal output frequency.

[0093] (3) By configuring a transmission management feedback mechanism in the signal transmission circuit from FPGA to MUX, it is ensured that the current signal transmission is completed and the untransmitted signal data is buffered when an interrupt occurs, and that signal transmission is quickly restored after the interrupt ends;

[0094] (4) The scheduling control module is configured in the MUX to realize functions such as interrupt management, data buffering and error recovery;

[0095] (5) By switching the clock for the MUX input and setting the scheduling control module, the configuration of the MUX can be optimized to flexibly adjust the signal generation speed and the output speed to the driver, which helps to ensure compatibility under different test equipment and test requirements;

[0096] (6) By dynamically adjusting the impedance in a DDR driver with adjustable slew rate, signal reflection and loss can be effectively avoided, ensuring stable transmission and signal integrity of high-speed signals, such as during testing.

[0097] (7) By using FPGA and MUX in conjunction with high-speed transmission circuit design, it is generally applicable to high-end testing scenarios such as DRAM SLT, PCIe / USB PHY testing, and SerDes verification.

[0098] While some embodiments of the present general inventive concept have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A circuit control method for improving signal generation speed, characterized in that, The circuit control method includes: The same reference clock is input to at least two FPGAs, and each of the at least two FPGAs performs offset correction on the received reference clock; The period of the reference clock is divided into several sub-cycles equal to the number of FPGAs; Each FPGA generates a corresponding signal sequence within the corresponding sub-cycle of the reference clock. Input a switching clock to the MUX, and control the MUX to cyclically select at least one of the corresponding FPGAs from two FPGAs within different periods of the switching clock and output the generated signal sequence to the driver; The driver integrates all signal sequences output from the at least two FPGAs to generate an output signal.

2. The circuit control method according to claim 1, characterized in that, The circuit control method further includes initializing each FPGA by sending a synchronization pulse signal to each FPGA to align the clock phase of each FPGA.

3. The circuit control method according to claim 2, characterized in that, The synchronization pulse signal is triggered during the first to third cycles of the reference clock after power-on, and the pulse width of the synchronization pulse signal is 1 / 10 to 1 / 5 of each cycle of the reference clock.

4. The circuit control method according to claim 2, characterized in that, Each FPGA uses its internal phase-locked loop module to monitor the clock offset between each FPGA in real time through a dynamic feedback mechanism. If the clock offset is greater than 50ps, initialization is triggered to resend the synchronization pulse signal.

5. The circuit control method according to claim 1, characterized in that, When the number of the at least two FPGAs is N, the MUX is 2. K 1 MUX, The 2 K The MUX has 2 input channels. K Where N=2 K K ≥ 1 and is a positive integer. The 2 K The switching clock frequency of the 1 MUX is N times the frequency of the reference clock, and the switching clock uses a phase-locked loop filter to control clock jitter to be less than or equal to 10 ps RMS. The 2 K :1 The gating logic of MUX follows the cyclic shift order.

6. The circuit control method according to claim 1, characterized in that, The driver is a slew rate adjustable DDR driver, which dynamically adjusts the output impedance to 50Ω±5% according to the transmission line impedance; The slew rate adjustment strategy involves injecting a test pulse signal into the DDR driver before signal transmission and then dynamically calculating the optimal slew rate based on the amplitude of the reflected signal.

7. The circuit control method according to any one of claims 1-6, characterized in that, When a command to interrupt transmission is received, Control the FPGA to complete the currently transmitted signal sequence and buffer the data of the untransmitted signal sequence into its internal memory; Controls the MUX to clear the buffer queue for signal sequence transmission.

8. The circuit control method according to claim 7, characterized in that, When the interruption ends The current FPGA rereads the last 3-5 unacknowledged transmission signal sequences before the interruption from its memory. Furthermore, an error verification code is inserted at the output of the MUX and sent to the driver along with the signal sequence to be output so that the driver can verify the continuity of the signal sequence.

9. The circuit control method according to claim 7 or 8, characterized in that, The step of each FPGA generating a corresponding signal sequence within the corresponding sub-cycle of the reference clock further includes data preloading, wherein the data preloading is to pre-store the signal sequence generated by each FPGA into the buffer of that FPGA in sequence, wherein the buffer is a FIFO buffer or a Pipeline buffer.

10. A control device for improving signal generation speed, the control device generating a high-speed signal using the circuit control method according to any one of claims 1-9, characterized in that, The control device includes: A clock module is configured to input the same reference clock to at least two FPGAs and divide the period of the reference clock into a number of sub-cycles equal to the number of FPGAs. An FPGA module is configured to include at least two FPGAs, wherein each of the at least two FPGAs receives the same reference clock from the clock module and performs offset correction on the reference clock, and each FPGA generates a corresponding signal sequence in the corresponding sub-cycle of the reference clock. The MUX module is configured to include a switching clock and a scheduling control module. The scheduling control module controls the MUX to cyclically select at least one of the corresponding FPGAs from at least two FPGAs and output the signal sequence it generates during different cycles of the switching clock. The driver module is configured to generate an output signal by integrating all signal sequences from at least two FPGAs through a driver.

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