A macro layout method based on combination of monte carlo tree search and bayesian optimization

Abstract

This invention discloses a macro-layout method based on a combination of Monte Carlo tree search and Bayesian optimization. This method optimizes the macro-cell layout by dividing the circuit layout space into a grid and sorting macrocells by area, constructing a search tree. Bayesian optimization of the macro-cell layout space involves randomly selecting nodes with high node value from the search tree for layout optimization, calculating and recording the HPWL (half-perimeter line length) and node visit count for each layout. During optimization, the layout is gradually improved by expanding node information and updating the optimization objective until a preset number of iterations is met. Finally, the optimal macro-layout scheme is output by selecting the node with the best evaluation metric. The optimization method provided by this invention can effectively improve layout quality and is applicable to macro-layout problems in integrated circuit design.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit electronic design automation technology, and relates to a macro layout method based on a combination of Monte Carlo tree search and Bayesian optimization. Background Technology

[0002] With the rapid development of integrated circuit technology, the feature size of semiconductor manufacturing processes is constantly shrinking, resulting in a significant increase in chip integration. This advancement has brought unprecedented challenges to chip designers. Traditional chip design methods, which mainly rely on manual operation, are no longer sufficient to meet the increasingly stringent requirements for chip performance, power consumption, and design cycle time. Therefore, the continuous improvement of Electronic Design Automation (EDA) tools has become crucial to address the ever-increasing complexity of chip design.

[0003] Macro-placement is a critical step in the physical design flow of VLSI (Very Large Scale Integration), determining the relative positions of macro modules in the chip netlist and significantly impacting subsequent standard cell placement and routing. Modern chip design typically includes numerous pre-placed modules; ignoring these modules can lead to illegal placement or suboptimal solutions. The mixed-size macro-placement problem can be summarized as follows: given a predetermined chip canvas (placement area) and a netlist containing macros, standard cells, and pre-placed modules of various sizes, the goal is to determine the positions of all macros to prevent overlap while minimizing metrics such as line length and routerizability. The quality of macro-placement directly affects chip performance, power consumption, and area. Initially, with simple chip structures, macro-placement problems could be solved manually. However, with increasing chip integration and design rules becoming more complex, automated placement algorithms are needed to assist in design. Traditional optimization placement algorithms can be categorized into three types: partitioned placement algorithms, simulated annealing algorithms, and analytical placement algorithms. Partitioned placement algorithms divide the chip into multiple regions and progressively optimize the macro cell placement within each region, but they are prone to getting trapped in local optima when dealing with large-scale chips. Simulated annealing avoids local optima by introducing randomness, but its computational complexity is high, making it difficult to converge quickly in practical applications. Analytical placement algorithms optimize macrocell placement using mathematical models, but they perform poorly when dealing with complex constraints. These traditional methods have limitations in computational efficiency, placement quality, and adaptability, making them difficult to meet the demands of modern chip design.

[0004] With the advent of the era of big data and artificial intelligence, data volume and computing power are exploding, and intelligentization is likely to be an effective way to break through the current bottlenecks in the quality and efficiency of macro-module layout. Machine learning has begun to be applied in many research fields and has achieved some important progress. Among them, reinforcement learning, with its good self-learning and generalization capabilities, is gradually becoming one of the most active research areas in machine learning. Recently, reinforcement learning methods have modeled the problem as a Markov decision process in a discrete action space by dividing the chip layout into a discrete grid and gradually placing macro-elements into the grid. In each step of the Markov process, the reinforcement learning agent decides the placement position of the current macro-element. After placing the current element, the system gives a reward, and the state transitions. This process is repeated until every macro-element is placed on the chip layout. However, reinforcement learning methods may lead to suboptimal solutions due to the large search space.

[0005] Therefore, an efficient optimization method needs to be designed to address the problem of placing macro-components on chips, in order to overcome its limitations in handling large-scale, highly complex chip design problems. Summary of the Invention

[0006] The purpose of this invention is to address the problem that existing macro-component placement methods are not well optimized and are prone to getting trapped in local optima. This invention proposes a macro-layout method based on a combination of Monte Carlo tree search (MCTS) and Bayesian optimization (BO).

[0007] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0008] In a first aspect, the present invention provides a macro-layout method based on a combination of Monte Carlo tree search and Bayesian optimization, comprising the following steps:

[0009] Step S1: Obtain the netlist and layout space of the circuit to be laid out, divide the layout space into a grid, the netlist contains multiple macro cells, and arrange all macro cells in descending order of their area;

[0010] Step S2: Construct a search tree, where each node in the search tree represents a macro layout state;

[0011] Step S3: For the current optimized macro layout state, perform Bayesian optimization of the macro cell layout space for each macro cell in sequence until the Bayesian optimization iteration reaches the maximum period;

[0012] Specifically, the process involves performing Bayesian optimization of the macrocell layout space for each macrocell. A node is randomly selected from the current optimization state. Starting with macrocells within this node, they are sequentially placed onto the mesh, recording the half-perimeter wire length (HPWL) of the node's growth and its current position. This continues until all macrocells have been placed, and the sum of the final HPWL is recorded. This process is repeated to obtain a new sum of HPWL. If the sum of HPWLs is less than the previous maximum sum, the current macrocell position information is expanded to leaf node information, and the value of the current leaf node is calculated. This process continues until the Bayesian optimization iterates to the maximum period (n times).

[0013] Step S4: Select the macro layout corresponding to the node with the best evaluation metric from the search tree as the final output result.

[0014] Secondly, the present invention provides a macro layout apparatus for implementing the above method, comprising the following modules:

[0015] The data processing module is used to obtain the netlist and placement space of the circuit to be placed, divide the placement space into a grid, and sort the macro cells in descending order of macro cell area.

[0016] The search tree building module is used to build multi-level search trees;

[0017] The layout optimization module uses Bayesian optimization to optimize the layout of macrocells;

[0018] The output module, when the iteration termination condition of Bayesian optimization is met, selects the node with the smallest semi-perimeter length from the search tree and outputs the macro layout scheme.

[0019] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a macro layout method based on a combination of Monte Carlo tree search and Bayesian optimization as described in any of the first aspects.

[0020] Fourthly, the present invention provides a computer device, comprising:

[0021] Memory is used to store instructions.

[0022] A processor for executing the instructions, causing the computer device to perform operations of a macro-layout method based on a combination of Monte Carlo tree search and Bayesian optimization as described in any of the first aspects.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] This invention provides a macro-layout method based on a combination of Monte Carlo tree search and Bayesian optimization. By combining Monte Carlo tree search and Bayesian optimization algorithms, it can efficiently handle macro-module layout problems. Specifically, a collaborative framework is constructed. Monte Carlo tree search is used to explore the solution space of the macro-layout and generate a series of candidate layout schemes; Bayesian optimization then optimizes these candidate schemes based on existing scheme evaluation information, guiding the search towards a better layout. This achieves multiple objectives: ensuring layout validity, improving layout quality, and optimizing resource utilization. Attached Figure Description

[0025] Figure 1 This is a flowchart of a macro layout method based on a combination of Monte Carlo tree search and Bayesian optimization according to the present invention.

[0026] Figure 2 This invention describes the implementation process of a macro layout method based on a combination of Monte Carlo tree search and Bayesian optimization.

[0027] Figure 3 This is a schematic diagram of the Bayesian optimization macro layout space iteration of the present invention.

[0028] Figure 4 This is a schematic diagram illustrating the iterative expansion and pruning optimization model of the Monte Carlo tree macrounit of the present invention. Detailed Implementation

[0029] The technical solutions described below will be clearly and comprehensively explained with reference to the accompanying drawings of the embodiments of the present invention. It should be noted that the embodiments detailed herein cover only some aspects of the present invention, not all aspects. Other embodiments obtained by those skilled in the art without inventive effort are all within the protection scope of the present invention.

[0030] The present invention will be further described below with reference to specific embodiments.

[0031] Example 1:

[0032] like Figure 1 and Figure 2 As shown, this embodiment introduces a macro-layout method based on a combination of Monte Carlo tree search and Bayesian optimization, including the following steps:

[0033] Step S1: Obtain the netlist and placement space of the circuit to be placed. Divide the placement space into a mesh, resulting in a meshed placement space. The netlist contains multiple macrocells, which are arranged in descending order of area.

[0034] Specifically, in this embodiment, the layout space is divided into m*m grids, where the value of m should be adjusted appropriately according to the number of macros. The position information of each placed macro is the lower left corner position information of the grid, and the grid state after placement should be set to prevent macro placement. Based on the input circuit information, the area of ​​the macro cells is calculated and arranged in descending order so that macro cells can be placed sequentially later.

[0035] Step S2: Construct a search tree where each node represents a macro layout state. Different nodes of the same macro layout state contain different positions of the same macro unit within the layout.

[0036] Specifically, in this embodiment, a root node is created, representing an empty canvas for the optimization node (i.e., no macros are placed). Initial exploration is performed first, allowing Bayesian optimization to begin with a relatively good solution. After optimization, good solutions are added to the leaf nodes of the currently selected optimization node (based on the macro order: the root node is an empty canvas, its leaf nodes contain the first macro information (leaf node 1), leaf node 1's leaf nodes contain the first and second macro information (leaf node 2), and so on, until all macro units are placed). For the hyperparameter selection, M1=200, M2=5. This allows the Bayesian optimization of macro unit positions to iterate 1000 times, comparing the results of different methods.

[0037] Step S3: Perform Bayesian optimization of the macrocell layout space for each macrocell. Randomly select a node from the current optimization state, and starting with the macrocells within that node, place them sequentially onto the grid, recording the HPWL growth of each node and its current position, until all macrocells have been placed. Record the sum of the HPWLs after all macrocells have been placed. Repeat the above steps to obtain a new sum of HPWLs. If the sum of HPWLs is less than the previous maximum sum of HPWLs, expand the current macrocell position information to leaf node information and calculate the value of the current leaf node, until the Bayesian optimization iteration reaches the maximum period (n times).

[0038] Specifically, in this embodiment, the first loop after initializing the macrocells in descending order starts with the optimization of the first macrocell. When the second execution reaches step S3, the optimization of the second macrocell begins. And so on.

[0039] like Figure 3 As shown, when selecting the macrocell to be optimized (a) i After that, a i-2 and a i-1 Macrocell fixed (i.e., s) i-1 (state), randomly from s i-1The optimization node selects a node to begin optimization until all macro cells are placed. During placement, for the currently optimized macro cell, a valid position on the grid (one of the first p positions with the smallest line length increment) is randomly selected for placement. For other macro cells, the position with the smallest HPWL increment is prioritized for placement.

[0040] Furthermore, the iterative process of the Bayesian optimization algorithm includes:

[0041] Based on existing layout evaluation information, a prior distribution model of the objective function is constructed. This model describes the distribution of the objective function, providing a foundation for subsequent optimization. According to the prior distribution model, candidate layout schemes with high value points are selected for evaluation. These candidate layout schemes are obtained through node selection and expansion in the search tree. The prior distribution model is updated based on the evaluation results. By continuously updating the model, the search scope is gradually narrowed, guiding the search towards a better layout. This process is repeated until the set maximum iteration period is reached. After each iteration, the optimization node is updated based on the iteration results, and the optimized node is updated to the next macrounit, continuing the subsequent optimization steps until all macrounits are optimized.

[0042] Step S4: When optimizing the number of leaf nodes, retain the corresponding maximum number of set nodes according to the leaf node value score from high to low in order to control the size of the search tree, avoid over-expansion, and update the optimized object to the next macro unit.

[0043] Specifically, in this embodiment, if the HPWL after all macros are placed is better than the HPWL of the tree node in one round of Bayesian optimization, the macro position message is saved, and the node value F(x) of the currently optimized node is retained. Bayesian optimization continues from the original optimized node until the Bayesian optimization iteration reaches the maximum period. The formula for calculating the current node is:

[0044]

[0045] In the formula: hpwl(x) is the negative value of the half-circle length of all macros on the canvas in the current step; k is a hyperparameter balancing exploration and development; n p n represents the number of times the parent node has been visited. m This represents the number of visits to the current node. In the iterative process of Monte Carlo tree search, a leaf node is systematically selected for expansion, involving four key steps: selection, expansion, simulation, and backpropagation. First, the algorithm recursively navigates from the root node to its child nodes, prioritizing nodes with higher values ​​to identify leaf nodes. Then, the next action is executed, resulting in the expansion of new child nodes. Finally, backpropagation updates the value and visit count of the parent node.

[0046] Based on the set number of nodes to retain at the same level, n, the top n optimized nodes with smaller HPWL values ​​are retained. These optimized nodes are then updated to the next macro (preserving the original macro's position), reducing the search space. This allows the algorithm to perform more advantageous explorations within a limited time. Figure 4 As shown, s i-1 a is fixed in the middle i-3 a i-2 and a i-1 When the update optimization node becomes a i At that time, s i The positions after performing n rounds of Bayesian optimization of the macro layout are all based on s i-1 The macro is fixed in the middle, and if the optimized s i If the number of nodes is greater than n (let's say 3), and the graph has 4 nodes, nodes with higher value will be deleted. This ensures that the number of randomly selected nodes will not exceed n, reducing the search space size while achieving efficient exploration.

[0047] Step S5: Repeat steps 3-4 until each macrocell has undergone n Bayesian optimizations. In each iteration, the placement of the macrocells is continuously optimized, gradually improving the placement quality.

[0048] The first round (S3-S5) primarily explores multiple locations for the macro with the largest area. The second round begins exploring the location of the second largest macro (starting from the location of the macro in the first round), until the preset number of iterations is reached. Increasing the number of Bayesian optimization iterations involves optimizing a node for a certain number of n rounds, then switching to another node for optimization.

[0049] Step S6: When the termination condition is met, select the macro layout corresponding to the node with the best evaluation index from the search tree as the final output result.

[0050] This layout is a chip macro layout scheme optimized by the algorithm, which can be directly used in subsequent chip design processes, such as placement and routing.

[0051] To further verify the effectiveness of the method of the present invention, a comparative experiment was conducted, and the results are shown in Table 1.

[0052] Table 1. HPWL values ​​of macro layout results (×10) 5 )

[0053]

[0054] Table 1 shows the best HPWL values ​​achieved by the comparative methods on the ISPD2005 benchmark. Each result consists of the average of 5 runs. The best (minimum) average value for each chip is shown in bold. As shown in Table 1, the method of this invention demonstrates superior optimization compared to other methods on multiple benchmarks, significantly reducing trace length and improving layout quality. The method of this invention exhibits stable performance on different datasets and can adapt to chip design needs of various sizes and complexities. The method of this invention has good adaptability and scalability, and can be integrated with other EDA tools to provide comprehensive support for the chip design flow.

[0055] Example 2:

[0056] This embodiment describes a computer-readable storage medium storing a computer program that, when executed by a processor, implements a macro layout method based on a combination of Monte Carlo tree search and Bayesian optimization as described in any of Embodiment 1.

[0057] Example 3:

[0058] This embodiment describes a computer device, including:

[0059] Memory is used to store instructions.

[0060] A processor is configured to execute the instructions, causing the computer device to perform an operation of a macro-layout method based on a combination of Monte Carlo tree search and Bayesian optimization as described in any of Embodiment 1.

[0061] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0062] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart. Figure 1 One or more processes and / or boxes Figure 1A device that provides the functions specified in one or more boxes.

[0063] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0064] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0065] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A macro placement method based on the combination of Monte Carlo tree search and Bayesian optimization, characterized in that, The method includes the following steps: Step S1: Obtain the netlist and layout space of the circuit to be laid out, divide the layout space into a grid, the netlist contains multiple macro cells, and arrange all macro cells in descending order of their area; Step S2: Construct a search tree, where each node in the search tree represents a macro layout state; the method for constructing the search tree includes: Initialize the root node, which represents an empty layout state without any macrocells; generate multiple candidate positions for each macrocell, with each candidate position corresponding to a child node in the search tree; sort the macrocells in descending order of area, and expand the child nodes for each macrocell sequentially to form a multi-level search tree structure, where each level of nodes represents different layout positions of the same macrocell; dynamically evaluate the current set of nodes to be optimized, and dynamically select the optimized node based on the set node value score to guide the subsequent optimization process; Step S3: For the current optimized macro-layout state, sequentially perform Bayesian optimization of the macro-cell layout space for each macro-cell until the Bayesian optimization iteration reaches the maximum period; specifically including the following steps: Step S31: Select a macro cell and place it sequentially on the grid, starting from the current macro cell. Record the increment of the half-perimeter length and the position at each step until all macro cells are placed. Record the sum of the half-perimeter lengths after all macro cells are placed. During the placement process, for the currently optimized macro cell, randomly select a legal position on the grid for placement. For other macro cells, prioritize the position with the smallest increment of the half-perimeter length. Step S32: Repeat step S31 to obtain the new sum of half-circumference line lengths. If the new sum of half-circumference line lengths is less than the previous largest sum of half-circumference line lengths, expand the current macrocell position information into leaf node information and calculate the current leaf node value until the Bayesian optimization iteration reaches the maximum period. Step S4: Select the macro layout corresponding to the node with the best evaluation metric from the search tree as the final output result.

2. The macro placement method based on the combination of Monte Carlo tree search and Bayesian optimization of claim 1, wherein, A macro layout state contains different positions of the same macro cell within the layout.

3. A macro layout device for implementing the method according to any one of claims 1-2, characterized by Includes the following modules: The data processing module is used to obtain the netlist and placement space of the circuit to be placed, divide the placement space into a grid, and sort the macro cells in descending order of macro cell area. The search tree building module is used to build multi-level search trees; The layout optimization module uses Bayesian optimization to optimize the layout of macrocells; The output module, when the iteration termination condition of Bayesian optimization is met, selects the node with the smallest semi-perimeter length from the search tree and outputs the macro layout scheme.

4. A computer device, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, When the processor executes the program, it implements the method as described in any one of claims 1-2.

5. A computer readable storage medium storing a computer program, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1-2.

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