一种基于Systolic阵列的计算结构可配置卷积神经网络加速系统
By designing a computational structure based on a Systolic array and configurable units, and combining deep parallel convolution and Winograd convolution modes, the flexibility and efficiency issues of existing hardware accelerators when dealing with different CNN models are solved, achieving low-power, high-performance acceleration of convolutional neural networks.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAZHONG UNIV OF SCI & TECH
- Filing Date
- 2025-08-29
- Publication Date
- 2026-07-17
AI Technical Summary
Existing convolutional neural network hardware accelerators lack flexibility when dealing with CNN models with different layer structures, and insufficient algorithm and hardware optimization leads to limitations in power consumption and real-time performance of the acceleration system.
It adopts a computational structure design based on a Systolic array, combined with configurable units and data flow scheduling, to support flexible configuration of different convolutional layers. It is accelerated by deep parallel convolution and Winograd convolution mode, and the computation process is optimized by using a double buffer mechanism and a control signal pulsation mechanism.
It achieves high computational performance acceleration of convolutional neural networks with low power consumption, supports the applicability of various CNN models, improves computational efficiency and resource utilization, simplifies the design process, and reduces instruction processing latency.
Smart Images
Figure CN121189398B_ABST