Electron emission device and method of manufacturing the same

Abstract

This invention provides an electron emission device and its fabrication method. The fabrication method includes: providing a silicon substrate, including a first side and a second side opposite to each other; forming a monocrystalline silicon epitaxial layer on the first side of the silicon substrate by homoepitaxial growth, wherein the resistivity of the monocrystalline silicon epitaxial layer is greater than that of the silicon substrate; forming a porous structure in the monocrystalline silicon epitaxial layer, wherein each pore of the porous structure contains multiple nano-silicon grains, and forming a silicon oxide thin film on the surface of the nano-silicon grains; forming a first electrode on the porous structure; and forming a second electrode on the second side of the silicon substrate. The monocrystalline silicon epitaxial layer of this invention has high resistivity, and during electron emission, the voltage drop can be entirely concentrated in the emission region of the monocrystalline silicon epitaxial layer, which can greatly improve the emission current density of the electron emission device and enhance the emission performance of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to an electron emission device and its manufacturing method. Background Technology

[0002] Electron emission devices play a crucial role in the modern electronics industry, with widespread applications in flat panel displays, X-ray sources, sensors, and microelectronic devices. Traditional electron emission materials, such as tungsten filaments and molybdenum filaments, are widely used in thermionic emission sources due to their high melting points and good electrical conductivity. However, these materials have some inherent limitations, such as the need for high operating temperatures, low electron emission efficiency, and limited lifespan.

[0003] In recent years, with the development of nanotechnology and materials science, porous silicon materials have attracted widespread attention due to their unique structure and properties. Porous silicon is a silicon-based material with high specific surface area, high porosity, and tunable pore size, which makes it potentially valuable in the field of electron emission. Porous silicon can be prepared by methods such as chemical etching, electrochemical etching, or plasma etching, and its pore structure and size can be controlled by process parameters.

[0004] The most common and simplest method for preparing porous silicon is to form nanocrystals on a single-crystal silicon substrate through photoelectrochemical etching. These nanocrystals are then used for electron tunneling and acceleration, ultimately leading to their emission. However, because the single-crystal silicon substrates used in this method are typically low resistivity, the emission voltage is generally quite low.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an electron emission device and its manufacturing method, so as to solve the problems of low emission efficiency, leakage, and easy breakdown in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating an electron emission device, the method comprising: providing a silicon substrate, including a first side and a second side opposite to each other; forming a single-crystal silicon epitaxial layer on the first side of the silicon substrate by homoepitaxial growth, wherein the resistivity of the single-crystal silicon epitaxial layer is greater than the resistivity of the silicon substrate; forming a porous structure in the single-crystal silicon epitaxial layer, wherein each pore of the porous structure contains a plurality of nano-silicon grains, and forming a silicon oxide thin film on the surface of the nano-silicon grains; forming a first electrode on the porous structure; and forming a second electrode on the second side of the silicon substrate.

[0008] Optionally, the homoepitaxial method includes chemical vapor deposition, wherein the resistivity of the single-crystal silicon epitaxial layer is more than 100 times that of the resistivity of the silicon substrate, the resistivity of the single-crystal silicon epitaxial layer is greater than 10 Ω·cm, and the resistivity of the silicon substrate is 0.001 Ω·cm to 0.05 Ω·cm.

[0009] Optionally, the method for forming the porous structure includes photoelectrochemical etching, which includes pulsed current etching.

[0010] Optionally, the thickness of the single-crystal silicon epitaxial layer is greater than the thickness of the porous structure, so that the photoelectrochemical etching region converges within the single-crystal silicon epitaxial layer.

[0011] Optionally, the thickness of the single-crystal silicon epitaxial layer is 0.5μm to 10μm, and the average size of the nano-silicon grains is 1nm to 10nm.

[0012] Optionally, the nano-silicon grains contained in the porous structure are arranged in a columnar shape so that the applied electric field is uniformly distributed along the columnar array of nano-silicon grains.

[0013] Optionally, the silicon oxide film is formed by electrochemical oxidation or rapid thermal oxidation, and the thickness of the silicon oxide film is 0.1 nm to 5 nm.

[0014] The present invention also provides an electron emission device, the electron emission device comprising: a silicon substrate, including a first surface and a second surface opposite to each other; a single-crystal silicon epitaxial layer, homoepitaxially formed on the first surface of the silicon substrate, wherein the resistivity of the single-crystal silicon epitaxial layer is greater than the resistivity of the silicon substrate; a porous structure formed in the single-crystal silicon epitaxial layer, wherein each pore of the porous structure contains a plurality of nano-silicon grains, and a silicon oxide thin film is formed on the surface of the nano-silicon grains; a first electrode formed on the porous structure; and a second electrode formed on the second surface of the silicon substrate.

[0015] Optionally, the resistivity of the single-crystal silicon epitaxial layer is more than 100 times that of the resistivity of the silicon substrate, the resistivity of the single-crystal silicon epitaxial layer is greater than 10 Ω·cm, and the resistivity of the silicon substrate is 0.001 Ω·cm to 0.05 Ω·cm.

[0016] Optionally, the thickness of the single-crystal silicon epitaxial layer is greater than the thickness of the porous structure.

[0017] Optionally, the thickness of the single-crystal silicon epitaxial layer is 0.5μm to 10μm, and the average size of the nano-silicon grains is 1nm to 10nm.

[0018] Optionally, the nano-silicon grains contained in the porous structure are arranged in a columnar shape so that the applied electric field is uniformly distributed along the columnar array of nano-silicon grains.

[0019] Optionally, the thickness of the silicon oxide film is 0.1 nm to 5 nm.

[0020] As described above, the electron emission device and its manufacturing method of the present invention have the following beneficial effects:

[0021] This invention creates a porous structure by homogeneously epitaxially forming a high-resistivity monocrystalline silicon epitaxial layer on a monocrystalline silicon substrate and then etching the epitaxial layer with an etching solution. First, the high-resistivity monocrystalline silicon epitaxial layer allows the voltage drop during electron emission to be concentrated entirely within its emission region, significantly increasing the emission current density and improving the emission performance of the electron emission device. Second, the monocrystalline silicon epitaxial layer produced by this invention lacks grain boundaries, resulting in a more uniform etching effect compared to polycrystalline silicon. It avoids residual crystal pillars and other structures, preventing localized breakdown and reducing chromatic aberration of emitted electrons while improving collimation. Third, the thickness of the monocrystalline silicon epitaxial layer is greater than the thickness of the porous structure, meaning the photoelectrochemical etching region converges within the monocrystalline silicon epitaxial layer. This prevents leakage current caused by photoelectrochemical etching penetration, further improving device performance. Attached Figure Description

[0022] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0023] Figures 1 to 8 The diagram shows the structural schematics of each step in the fabrication method of the electron emission device according to an embodiment of the present invention, wherein... Figure 8 The diagram shown is a structural schematic of an electron emission device according to an embodiment of the present invention.

[0024] Component designation explanation

[0025] 101 Silicon substrate

[0026] 102 Single-crystal silicon epitaxial layer

[0027] 103 Porous Structure

[0028] 104 nanometer silicon grains

[0029] 105 silicon oxide thin film

[0030] 106 First Electrode

[0031] 107 Second Electrode Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0034] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0035] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0036] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0037] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0038] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0039] Epitaxial growth (often simply called epitaxy) is one of the most important processes in the manufacture of semiconductor materials and devices. Its application and development are of great significance for improving the quality of semiconductor materials and the performance of devices, for the development of new materials and devices, and for the advancement of semiconductor science. Epitaxial growth is the process of growing a new single-crystal layer, with the required conductivity type, resistivity, thickness, crystal structure, and integrity, along the original crystallographic direction on a carefully prepared single-crystal substrate under certain conditions. The grown single-crystal layer is called an epitaxial layer.

[0040] Epitaxial technology began to develop gradually in the early 1960s. Its emergence solved many previously intractable problems in semiconductor device manufacturing, significantly improving device performance. The ability to precisely control the thickness and doping of epitaxial layers propelled the rapidly developing semiconductor integrated circuit technology into a more mature stage. Subsequently, driven by applications, silicon epitaxial technology experienced substantial development.

[0041] Existing methods for preparing porous silicon by growing polycrystalline silicon layers suffer from grain boundary issues. During photoelectrochemical etching to form nanocrystals, the etching solution penetrates along the grain boundaries into the silicon substrate, creating pathways. These pathways introduce leakage current, significantly impacting emission performance. Furthermore, when the etched porous silicon contains residual crystal pillars, these pillars can also contribute emitted electrons, potentially causing localized breakdowns and altering the surrounding electric field. This ultimately leads to problems such as increased chromatic aberration and reduced collimation of emitted electrons.

[0042] like Figures 1 to 8 As shown, this embodiment provides a method for fabricating an electron emission device, the method comprising the following steps:

[0043] like Figure 1 As shown, step 1) is performed first, providing a silicon substrate 101, including a first side and a second side opposite to each other.

[0044] In one embodiment, the silicon substrate 101 is a single-crystal silicon substrate, which may contain doped ions, such as N-type doped ions (e.g., phosphorus, arsenic, etc.) or P-type doped ions (e.g., boron, etc.). The resistivity of the single-crystal silicon substrate may be, for example, 0.001 Ω·cm to 0.05 Ω·cm, but is not limited to the examples or ranges listed herein.

[0045] In one embodiment, the process further includes surface pretreatment of the silicon substrate 101. Specifically, the monocrystalline silicon can be immersed in a solution with a H2SO4:H2O2 ratio of 3:1 until the bubbles disappear, thereby cleaning and removing organic residues from the surface of the silicon substrate 101. After immersion, the silicon substrate 101 can be further immersed in deionized water (DIW) to remove the natural oxide layer on the surface, completing the surface pretreatment of the silicon substrate 101. Of course, other cleaning methods can also be used to remove organic matter and the natural oxide layer from the surface of the silicon substrate 101, and are not limited to the examples listed herein.

[0046] like Figure 2 As shown, then step 2) is performed, in which a single-crystal silicon epitaxial layer 102 is formed on the first surface of the silicon substrate 101 by homoepitaxialization, wherein the resistivity of the single-crystal silicon epitaxial layer 102 is greater than the resistivity of the silicon substrate 101.

[0047] In one embodiment, before homoepitaxial growth, a gas containing the desired dopant atoms can be added to the precursor atmosphere (silane, dichlorosilane, trichlorosilane, or other silicon sources). The N-type dopant gas can be one or both of phosphine (PH3) and arsine (AsH3), while the P-type dopant gas can be borane (B2H6), etc. This doping step ensures that the single-crystal silicon epitaxial layer 102 and the single-crystal silicon substrate have the same conductivity type. Furthermore, the desired resistivity of the single-crystal silicon epitaxial layer 102 can be obtained by controlling the doping concentration.

[0048] In one embodiment, the homoepitaxial method includes chemical vapor deposition, in which case the homoepitaxial method may include the following steps:

[0049] 1) The cleaned silicon substrate 101 is loaded into the epitaxial reactor, and the epitaxial reactor is evacuated to reduce gas and vapor molecules in the epitaxial reactor, thereby reducing the incorporation of unwanted impurities.

[0050] 2) The silicon substrate 101 is heated by a heating element to reach a temperature suitable for epitaxial growth. This temperature can be selected according to the type of silicon source. For example, the epitaxial temperature is 850-950℃ for silicon source SiH4, 1050-1100℃ for silicon source SiHCl3, and 1100-1150℃ for silicon source SiH2Cl2.

[0051] 3) The required reactive gases (such as organometallic compounds, H2, etc.) are introduced into the epitaxial reactor. These gases undergo chemical decomposition or recombination reactions on the surface of the silicon substrate 101, releasing silicon atoms which are deposited on the silicon substrate 101 to form a single-crystal silicon thin film. The growth rate and quality of the single-crystal silicon thin film are affected by various factors, including temperature, gas flow rate, pressure, and reaction time. After the desired film thickness is reached, the introduction of reactive gases is stopped, the temperature is gradually reduced, and the growth process is terminated.

[0052] 4) Cool the substrate to room temperature to fix the structure of the single-crystal silicon epitaxial layer 102. If necessary, the single-crystal silicon epitaxial layer 102 can also be subjected to subsequent processing, such as annealing or polishing.

[0053] In one embodiment, the resistivity of the single-crystal silicon epitaxial layer 102 is more than 100 times that of the silicon substrate 101, and the resistivity of the single-crystal silicon epitaxial layer 102 is greater than 10 Ω·cm. The single-crystal silicon epitaxial layer 102 of the invention is high-resistivity, while the silicon substrate 101 has low resistance. During electron emission, the voltage drop can be concentrated entirely in the emission region of the single-crystal silicon epitaxial layer 102, which can greatly improve the emission current density of the electron emission device and improve the emission performance of the device.

[0054] In one embodiment, the thickness of the single-crystal silicon epitaxial layer 102 is 0.5 μm to 10 μm.

[0055] like Figures 3-6 As shown, where, Figure 4 Displayed as Figure 3 Enlarged structural diagram of the area within the dashed box. Figure 6 Displayed as Figure 5 The enlarged structural diagram at the dashed box in the middle is then shown. Then, step 3) is performed, in which a porous structure 103 is formed in the single crystal silicon epitaxial layer 102. Each pore of the porous structure 103 contains a plurality of nano-silicon grains 104, and a silicon oxide thin film 105 is formed on the surface of the nano-silicon grains 104.

[0056] In one embodiment, the method for forming the porous structure 103 includes photoelectrochemical etching, which includes pulsed current etching.

[0057] In one embodiment, a silicon substrate 101 with a monocrystalline silicon epitaxial layer 102 formed on its surface is subjected to photoelectrochemical etching under pulsed constant current conditions to form a porous structure 103 in the monocrystalline silicon epitaxial layer 102. The etching solution can be a hydrofluoric acid mixture (e.g., a 1:1 mixture of 49% HF acid solution and 99.8% ethanol), with a pulse delay of 1 ms to 3 ms, a source delay of 6 ms to 10 ms (pulse delay duty cycle of 0.15 to 0.3), and a current density of 20 to 30 mA / cm².2 The distance between the halogen light source and the single-crystal silicon epitaxial layer 102 is 15–25 cm, and the photoelectrochemical etching time is 40–60 s. In a specific example, the etching solution can be a hydrofluoric acid mixture, with a pulse delay of 2 ms, a source delay of 8 ms (duty cycle of 0.2), and a current density of 20–30 mA / cm². 2 The distance between the halogen light source and the single-crystal silicon epitaxial layer 102 is 20 cm, and the photoelectrochemical etching time is 50 s.

[0058] In one embodiment, after photoelectrochemical etching, the columnar porous structure 103 containing nano-silicon grains 104 formed by etching the single-crystal silicon epitaxial layer 102 is oxidized. For example, the rapid thermal oxidation temperature is 850°C to 950°C and the time is 15 minutes to 30 minutes to form a silicon oxide film 105 on the outer surface of the nano-silicon grains 104. In a specific example, the rapid thermal oxidation temperature can be 900°C and the time can be 25 minutes.

[0059] In one embodiment, the thickness of the single-crystal silicon epitaxial layer 102 is greater than the thickness of the porous structure 103, so that the photoelectrochemical etching region converges within the single-crystal silicon epitaxial layer 102. For example, the thickness of the single-crystal silicon epitaxial layer 102 is 0.5 μm to 10 μm, and the thickness of the porous structure 103 is preferably 10 nm to 5000 nm. Its thickness can be adjusted according to the thickness of the single-crystal silicon epitaxial layer 102. Preferably, the thickness of the porous structure 103 is one-third to two-thirds of the thickness of the single-crystal silicon epitaxial layer 102. The single-crystal silicon epitaxial layer 102 fabricated by this invention has no grain boundaries, resulting in a more uniform etching effect compared to polycrystalline silicon. It does not produce residual crystal pillars or other structures, thereby avoiding the problem of local breakdown of the device, reducing the chromatic aberration of emitted electrons, and improving collimation. Meanwhile, the thickness of the single-crystal silicon epitaxial layer 102 is greater than the thickness of the porous structure 103, meaning that the photoelectrochemical etching region is converging within the single-crystal silicon epitaxial layer 102. This can prevent the photoelectrochemical etching from penetrating and causing leakage current, thereby improving device performance.

[0060] In one embodiment, the average size of the nano-silicon grains 104 is between 1 nm and 10 nm.

[0061] In one embodiment, the nano-silicon grains 104 contained in the porous structure 103 are arranged in a columnar shape so that the applied electric field is uniformly distributed along the columnar array of nano-silicon grains 104.

[0062] In one embodiment, the silicon oxide film 105 is formed by electrochemical oxidation or rapid thermal oxidation, and the thickness of the silicon oxide film 105 is 0.1 nm to 5 nm.

[0063] like Figures 7-8As shown, step 4) is performed last, forming a first electrode 106 on the porous structure 103 and a second electrode 107 on the second surface of the silicon substrate 101.

[0064] In one embodiment, a Ti / Au metal layer for emission electrodes is sputtered onto the surface of the porous structure 103 as a first electrode 106. Specifically, a Ti layer with a thickness of approximately 1 nm is sputtered at a pressure of 7.52 mTorr under conditions of a gas flow rate of 50 sccm and an RF power of 300 W, and an Au layer with a thickness of approximately 10 nm is sputtered at a pressure of 7.50 mTorr. Then, a second electrode 107, including but not limited to Al, Au, and Cu, is sputtered onto the second surface of the silicon substrate 101 as an accelerating electrode.

[0065] like Figure 8 As shown, this embodiment also provides an electron emission device, which includes: a silicon substrate 101, including a first surface and a second surface opposite to each other; a single-crystal silicon epitaxial layer 102, homoepitaxially formed on the first surface of the silicon substrate 101, wherein the resistivity of the single-crystal silicon epitaxial layer 102 is greater than the resistivity of the silicon substrate 101; a porous structure 103 formed in the single-crystal silicon epitaxial layer 102, wherein each pore of the porous structure 103 contains a plurality of nano-silicon grains 104, and a silicon oxide thin film 105 is formed on the surface of the nano-silicon grains 104; a first electrode 106 formed on the porous structure 103; and a second electrode 107 formed on the second surface of the silicon substrate 101.

[0066] In one embodiment, the resistivity of the single-crystal silicon epitaxial layer 102 is more than 100 times that of the resistivity of the silicon substrate 101, the resistivity of the single-crystal silicon epitaxial layer 102 is greater than 10 Ω·cm, and the resistivity of the silicon substrate 101 is 0.001 Ω·cm to 0.05 Ω·cm.

[0067] In one embodiment, the thickness of the single-crystal silicon epitaxial layer 102 is greater than the thickness of the porous structure 103.

[0068] In one embodiment, the thickness of the single-crystal silicon epitaxial layer 102 is 0.5 μm to 10 μm, and the average size of the nano-silicon grains 104 is 1 nm to 10 nm.

[0069] In one embodiment, the nano-silicon grains 104 contained in the porous structure 103 are arranged in a columnar shape so that the applied electric field is uniformly distributed along the columnar array of nano-silicon grains 104.

[0070] In one embodiment, the thickness of the silicon oxide film 105 is 0.1 nm to 5 nm.

[0071] As described above, the electron emission device and its manufacturing method of the present invention have the following beneficial effects:

[0072] This invention creates a porous structure 103 by homogeneously epitaxially forming a high-resistivity monocrystalline silicon epitaxial layer 102 on a monocrystalline silicon substrate and then etching the monocrystalline silicon epitaxial layer 102 with an etching solution. First, the monocrystalline silicon epitaxial layer 102 is high-resistivity, allowing the voltage drop during electron emission to be concentrated entirely within the emission region of the monocrystalline silicon epitaxial layer 102, significantly increasing the emission current density and improving the emission performance of the electron emission device. Second, the monocrystalline silicon epitaxial layer 102 produced by this invention lacks grain boundaries, resulting in a more uniform etching effect compared to polycrystalline silicon. It avoids the formation of residual crystal pillars and other structures, thus preventing localized breakdown of the device, reducing chromatic aberration of emitted electrons, and improving collimation. Third, the thickness of the monocrystalline silicon epitaxial layer 102 is greater than the thickness of the porous structure 103, meaning the photoelectrochemical etching region converges within the monocrystalline silicon epitaxial layer 102. This prevents leakage current caused by photoelectrochemical etching penetration, further improving device performance.

[0073] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0074] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for producing an electron emitting device, characterized by, The manufacturing method includes: A silicon substrate is provided, including a first side and a second side facing each other; A monocrystalline silicon epitaxial layer is formed on the first surface of the silicon substrate by homoepitaxial growth, wherein the resistivity of the monocrystalline silicon epitaxial layer is greater than that of the silicon substrate. A porous structure is formed in the single-crystal silicon epitaxial layer, wherein each pore of the porous structure contains a plurality of nano-silicon grains, and a silicon oxide film is formed on the surface of the nano-silicon grains. A first electrode is formed on the porous structure; A second electrode is formed on the second surface of the silicon substrate; The method for forming the porous structure includes photoelectrochemical etching, which includes pulsed current etching. The thickness of the monocrystalline silicon epitaxial layer is greater than the thickness of the porous structure, so that the photoelectrochemical etching region converges within the monocrystalline silicon epitaxial layer; The porous structure contains nano-silicon grains arranged in a columnar shape.

2. The method of producing an electron emitting device according to claim 1, wherein: The homoepitaxial method includes chemical vapor deposition, wherein the resistivity of the single-crystal silicon epitaxial layer is more than 100 times that of the resistivity of the silicon substrate, the resistivity of the single-crystal silicon epitaxial layer is greater than 10 Ω·cm, and the resistivity of the silicon substrate is 0.001 Ω·cm to 0.05 Ω·cm.

3. The method of producing an electron emitting device according to claim 1, wherein: The thickness of the single-crystal silicon epitaxial layer is 0.5μm to 10μm, and the average size of the nano-silicon grains is 1nm to 10nm.

4. The method of producing an electron emitting device according to claim 1, wherein: The silicon oxide film is formed by electrochemical oxidation or rapid thermal oxidation, and the thickness of the silicon oxide film is 0.1 nm to 5 nm.

5. An electron emitting device, characterized by, The electron emission device includes: A silicon substrate, including a first surface and a second surface opposite to each other; A single-crystal silicon epitaxial layer is homogeneously epitaxially formed on a first surface of the silicon substrate, wherein the resistivity of the single-crystal silicon epitaxial layer is greater than the resistivity of the silicon substrate. A porous structure is formed in the single-crystal silicon epitaxial layer, wherein each pore of the porous structure contains a plurality of nano-silicon grains, and a silicon oxide film is formed on the surface of the nano-silicon grains. A first electrode is formed on the porous structure; A second electrode is formed on a second surface of the silicon substrate; The method for forming the porous structure includes photoelectrochemical etching, which includes pulsed current etching. The thickness of the single-crystal silicon epitaxial layer is greater than the thickness of the porous structure, so that the photoelectrochemical etching region converges within the single-crystal silicon epitaxial layer. The porous structure contains nano-silicon grains arranged in a columnar shape.

6. The electron emitting device according to claim 5, characterized by: The resistivity of the single-crystal silicon epitaxial layer is more than 100 times that of the silicon substrate, the resistivity of the single-crystal silicon epitaxial layer is greater than 10 Ω·cm, and the resistivity of the silicon substrate is 0.001 Ω·cm to 0.05 Ω·cm.

7. The electron emitting device according to claim 5, wherein: The thickness of the single-crystal silicon epitaxial layer is 0.5μm to 10μm, and the average size of the nano-silicon grains is 1nm to 10nm.

8. The electron emitting device according to claim 5, wherein: The thickness of the silicon oxide film is 0.1 nm to 5 nm.

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