Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof. The preparation method comprises: providing a substrate; the substrate comprises a substrate formed with a shallow trench defining an active region; wherein the shallow trench has an exposed first active region on both sides, and the surface of the first active region is adjacent to the sidewall of the shallow trench to form an initial top corner region; performing an oxidation process on the initial top corner region to form a target top corner region, the target top corner region has a rounded corner morphology compared with the initial top corner region; and reducing the oxide formed at least partially in the target top corner region to a substrate material to compensate for the consumption of the substrate material of the first active region in the oxidation process. In this way, the active region size reduction after the top corner rounding of the shallow trench can be inhibited.

Description

Technical Field

[0001] The embodiments in this application relate to the field of semiconductor process technology, and in particular to a semiconductor structure and its preparation method. Background Technology

[0002] Currently, in the manufacturing process of some semiconductor devices, it is necessary to round the corners formed by the sidewalls of STI (shallow trench isolation) and the active regions on both sides to alleviate electric field concentration and improve the reliability of the device under relatively high operating voltages.

[0003] In related technologies, the process of rounding the apex is usually achieved by using an oxidation process to optimize the apex shape, making the connection between the STI and the active regions on both sides smoother and forming a rounded morphology. However, at the same time, due to oxidation consumption, the size of the active regions on both sides of the STI is also reduced. Summary of the Invention

[0004] In view of this, several embodiments of this application aim to provide a semiconductor structure and a method for fabricating the same, which can suppress the shrinkage of the active region size after corner rounding.

[0005] One embodiment of this application provides a method for fabricating a semiconductor structure. The method includes: providing a substrate; the substrate including a subfloor, the substrate having a shallow trench defining an active region; wherein the shallow trench has exposed first active regions on both sides, and the surface of the first active region is adjacent to the sidewall of the shallow trench to form an initial apex region; performing an oxidation process on the initial apex region to form a target apex region, the target apex region having a rounded corner morphology compared to the initial apex region; and reducing at least a portion of the oxide formed in the target apex region to substrate material to compensate for the substrate material consumption of the first active region in the oxidation process.

[0006] Optionally, the step of reducing at least a portion of the oxide formed in the target apex region to substrate material to compensate for the substrate material consumption of the first active region in the oxidation process includes: injecting a reducing agent into the oxide formed in the target apex region and causing a redox reaction between the oxide and the reducing agent to reduce at least a portion of the oxide to substrate material.

[0007] Optionally, the step of injecting a reducing agent into the oxide formed in the target apex region and causing a redox reaction between the oxide and the reducing agent to reduce at least a portion of the oxide to a substrate material includes: injecting carbon atoms as a reducing agent into the oxide formed in the target apex region; and causing at least a portion of the oxide to undergo a redox reaction with the carbon atoms through an annealing process to obtain a reduced substrate material.

[0008] Optionally, in the step of injecting a reducing agent into the oxide formed in the target apex region and causing a redox reaction between the oxide and the reducing agent to reduce at least part of the oxide to substrate material, the oxide formed in the target apex region is only partially reduced to substrate material, and the unreduced remaining oxide covers the surface of the reduced substrate material; the preparation method further includes: forming a protective layer on the surface of the reduced substrate material by converting the material of the remaining oxide, the protective layer being used to suppress the diffusion of dopant ions into the shallow trench isolation structure; wherein the shallow trench isolation structure is formed in the shallow trench.

[0009] Optionally, in the step of forming a protective layer on the surface of the reduced substrate material by converting the material of the remaining oxide, the remaining oxide is converted into silicon carbide material.

[0010] Optionally, the step of forming a protective layer on the surface of the reduced substrate material by transforming the material of the residual oxide includes: implanting carbon atoms into the residual oxide; wherein the carbon atom implantation dose per unit thickness of the residual oxide is controlled to be 9.9E14 / cm. 2 ~13.2E14 / cm 2 Within the range; through an annealing process, the remaining oxide reacts with carbon atoms in a redox reaction to obtain a protective layer of silicon carbide.

[0011] Optionally, the substrate further has a second active region on both sides of the first active region; wherein the surface of the reduced substrate material is flush with the surface of the second active region.

[0012] Optionally, the reducing agent is carbon atoms; the carbon atom implantation dose per unit thickness of oxide is controlled at 6.6E14 / cm. 2 ~8.8E14 / cm 2 Within a certain range, and by controlling the annealing time, the surface of the reduced substrate material is made flush with the surface of the second active region.

[0013] Optionally, the silicon carbide protective layer is also used to generate tensile stress in the channel areas on both sides of the shallow trench.

[0014] One embodiment of this application provides a semiconductor structure, which is prepared using the semiconductor structure preparation method described above.

[0015] The unexpected effect of the various embodiments provided in this application is that, by performing an oxidation process on the initial apex region to form a target apex region with a rounded morphology, thereby achieving the apex rounding effect, the oxide formed by the oxidation consumption of the first active region exposed in the initial apex region is reduced to the substrate material to compensate for the consumption of the substrate material in the first active region, thereby suppressing the reduction in the size of the active region caused by the apex rounding. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a simulated structure after the vertex corners are rounded in related technologies.

[0017] Figure 2 and Figure 3 This is a schematic diagram comparing the simulation analysis results of current density and potential distribution under different vertex rounding effects in related technologies.

[0018] Figure 4 This is a schematic diagram of the slice structure of pull-up transistors and pull-down transistors after the vertex corners are rounded in related technologies.

[0019] Figure 5 This is a schematic diagram of the simulation results showing the relationship between the active region size and the threshold voltage in related technologies.

[0020] Figure 6 This is a schematic diagram of the diffusion effect of B ions in related technologies.

[0021] Figure 7 This is a schematic diagram of the initial oxide layer of the growth pad in the method for preparing the semiconductor structure provided in the embodiments of this application.

[0022] Figure 8 This is a schematic diagram of the formation of a hard mask layer and a patterned photoresist layer in the method for fabricating a semiconductor structure provided in the embodiments of this application.

[0023] Figure 9 This is a schematic diagram of the semiconductor intermediate structure formed in a method for preparing a semiconductor structure according to an embodiment of this application.

[0024] Figure 10 This is a schematic diagram of hard mask back etching in a semiconductor structure fabrication method provided in one embodiment of this application.

[0025] Figure 11 This is a schematic diagram of nitrogen atom implantation into the tilted portion in a method for fabricating a semiconductor structure according to another embodiment of this application.

[0026] Figure 12 This is a schematic diagram of hard mask back etching in a method for fabricating a semiconductor structure according to another embodiment of this application.

[0027] Figure 13 This is a schematic diagram of the formation of a target apex region in a method for fabricating a semiconductor structure according to an embodiment of this application.

[0028] Figure 14 TEM slice image of the 40V high-voltage device provided in this application after annealing.

[0029] Figures 15 to 21 The diagram and slice image show the variation of oxide thickness on the surfaces of the active region and virtual active region provided in this application during different process steps.

[0030] Figure 22 This is a schematic diagram of carbon atom implantation in a method for fabricating a semiconductor structure according to an embodiment of this application.

[0031] Figure 23 This is a schematic diagram of the reduced substrate material obtained by annealing process in a method for fabricating a semiconductor structure according to an embodiment of this application.

[0032] Figure 24 and Figure 25 This is a schematic diagram of STI filling to form a shallow trench isolation structure in a semiconductor structure fabrication method provided in one embodiment of this application.

[0033] Figure 26 and Figure 27 This is a schematic diagram illustrating the formation of N-type and P-type well regions in a semiconductor structure fabrication method provided in one embodiment of this application.

[0034] Figure 28 This is a schematic diagram of carbon atom implantation in a method for fabricating a semiconductor structure according to another embodiment of this application.

[0035] Figure 29 This is a schematic diagram of the annealing process in a method for fabricating a semiconductor structure according to another embodiment of this application.

[0036] Figure 30 This is a schematic diagram of the implantation of carbon atoms into the remaining oxide in a method for preparing a semiconductor structure according to another embodiment of this application.

[0037] Figure 31 This is a schematic diagram of a method for preparing a semiconductor structure according to another embodiment of this application, in which an annealing process is performed again.

[0038] Figure 32 and Figure 33 This is a schematic diagram of STI filling to form a shallow trench isolation structure in a method for fabricating a semiconductor structure according to another embodiment of this application.

[0039] Explanation of reference numerals in the attached figures:

[0040] 100, Substrate; 101, Substrate; 102, Shallow Trench; 103, First Active Region; 104, Second Active Region; 110, Initial Vertex Region; 130, Target Vertex Region; 150, Pad Oxide Layer; 160, Hard Mask Layer; 170, Pad Oxide Layer; 171, Reduced Substrate Material; 172, Residual Oxide; 180, Shallow Trench Isolation Structure; 190, Protective Layer; 200, Semiconductor Intermediate Structure; 210, Semiconductor Substrate; 211, Pad Oxide Layer Initial Form; 212, Hard Mask Layer Initial Form; 213, Semiconductor Substrate Initial Form; 220, Initial Shallow Trench; 230, Initial Pad Oxide Layer; 240, Initial Hard Mask Layer; 250, Inclined Section; 410, N-type Well Region; 420, P-type Well Region; aa, First Direction; bb, Second Direction. Detailed Implementation

[0041] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0042] In this application, the accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features.

[0043] Unless otherwise stated, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in embodiments of this application are also intended to include the plural forms unless the context clearly indicates otherwise.

[0044] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0045] In the description of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. In other words, they should not be construed as limitations on this application.

[0046] In the description of this application, unless otherwise expressly defined, the terms "installation," "connection," "linking," "fixing," "setting," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can also refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0047] In some semiconductor devices, the active region forms a apex region adjacent to the STI. This region is formed by the intersection of the active region parallel to the wafer surface and the STI sidewall, i.e., the side of the active region. Its shape is relatively sharp. Therefore, in practical applications, electric field concentration is likely to occur in this region, which affects the reliability of the semiconductor device.

[0048] To mitigate electric field concentration in the apex region, during semiconductor device manufacturing, the sharp corners formed by the sidewalls of the STI and the adjacent active regions on both sides are typically rounded to make them smoother and improve reliability. However, in practical applications, different rounding effects—that is, varying degrees of smoothness at the junction of the STI's sidewalls and the active regions on both sides—can also affect the electrical performance of the semiconductor device.

[0049] For example, refer to Figures 1 to 3 Technicians targeting Figure 1 The simulated structure with rounded apex corners shown was subjected to TCAD (Technology Computer-Aided Design Simulation) simulation analysis of the turn-off current Ioff. The simulation analysis results regarding current density and potential distribution under different apex corner rounding effects can be compared as follows: Figure 2 and Figure 3 As shown in the figure, it can be seen that Figure 2 The sidewalls of the STI and the connection between them and the active regions on both sides are compared to Figure 3 More tactful, in contrast, Figure 3The potential lines are denser, and the current density and electric field strength are greater. According to data analysis by technicians, Figure 2 medium structure relative to Figure 3 In the medium structure, the turn-off current Ioff is reduced by about half, the drain current Idsat in the saturation region is reduced by about 4%, and the threshold voltage parameters Vtgm and Vtlin are reduced by about 20mV.

[0050] Therefore, the required corner rounding effect during manufacturing varies depending on the type of semiconductor device or its performance requirements. Since corner rounding requires an oxidation process, pursuing a better rounding effect results in more substrate material being oxidized and consumed laterally by the active regions adjacent to the STI (Surface Mount Technology), thus compressing the size of the active regions. For example, see reference... Figure 4 For pull-down transistors (PD) and pull-up transistors (PU) in SRAM, PD requires a higher degree of smoothness to achieve lower turn-off current. However, if the active region size (CD) itself is relatively small, for example... Figure 4 In medium-sized PU, to achieve a higher degree of smoothness, excessive oxidation consumption can cause the active region's CD (cooling density) to become too small, thus affecting performance. For example... Figure 5 As shown, as the active region CD shrinks, the threshold voltage decreases significantly when it shrinks to a certain extent. Research has found that, as... Figure 6 As shown, the significant drop in threshold voltage is actually due to the shrinkage of the active region CD and the diffusion effect of B ions injected into the P-well.

[0051] Therefore, there is an urgent need for a semiconductor structure fabrication method that can achieve good corner rounding while suppressing the shrinkage of the active region size due to oxidation.

[0052] Please see Figures 7 to 27 One embodiment of this application provides a method for fabricating a semiconductor structure. The semiconductor structure can be applied in medium-voltage (MV) or high-voltage (HV) devices, such as semiconductor devices operating at voltages above 20V. In some embodiments, it can also be applied in low-voltage semiconductor devices. The method for fabricating the semiconductor structure may include the following steps.

[0053] S110: Provides semiconductor intermediate structure.

[0054] In this embodiment, as Figure 9 As shown, the semiconductor intermediate structure 200 includes a semiconductor substrate 210, on which an initial shallow trench 220 is formed. The initial shallow trench 220 extends from the surface of the semiconductor substrate 210 to its bottom. Specifically, the shallow trench 102 formed on the semiconductor substrate 210 can be formed using an STI etching process.

[0055] In this embodiment, the semiconductor substrate 210 can serve as the basic structure of a semiconductor device, not only providing mechanical support but also influencing the device's electrical properties, such as threshold voltage and carrier mobility, through doping with ions. Specifically, the semiconductor substrate 210 can be made of silicon (Si).

[0056] In this embodiment, a stacked initial pad oxide layer 230 and an initial hard mask layer 240 are formed on the surface of the semiconductor substrate 210 on both sides of the initial shallow trench 220. The initial pad oxide layer 230 and the initial hard mask layer 240 can be patterned structures formed by etching during the STI etching process, and can also serve as masks in subsequent process steps. Specifically, the initial pad oxide layer 230 is located between the initial hard mask layer 240 and the semiconductor substrate 210. The initial pad oxide layer 230 can serve as a masking layer in the subsequent ion implantation process to prevent damage to the surface of the semiconductor substrate 210 during ion implantation.

[0057] refer to Figure 7 For example, in some embodiments, such as Figure 7 As shown, a pad oxide layer 211, with a thickness of 55 Å, is first grown on the semiconductor substrate 213 using a furnace tube process. Then, ions are implanted into the semiconductor substrate 213 to form a deep well region, such as implanting N-type ions to form a DNW (Deep N-Well). Next, as... Figure 8 As shown, a hard mask material, such as SiN, is deposited on the initial oxide layer 211 to form a hard mask layer initial 212. A patterned photoresist layer for photolithography is then formed on the hard mask layer initial 212, defining the etching locations for STI. Finally, as... Figure 9 As shown, STI etching yields the semiconductor intermediate structure 200. The initial shallow trench 220 can be used to isolate the active regions located on either side of it. In some embodiments, NMOS and PMOS can be formed on the active regions on either side of the initial shallow trench 220 in subsequent processes. STI can be formed by filling the initial shallow trench 220 with oxide, achieving insulation and isolation of the active regions on both sides.

[0058] In this embodiment, based on the characteristics of shallow trench etching, such as when dry etching is used, the opening width of the initial shallow trench 220 gradually decreases along its concave direction. This results in the sidewalls of the initial shallow trench 220 not being ideally perpendicular to the surface of the semiconductor substrate 210, but rather inclined relative to the vertical direction of the semiconductor substrate 210 surface. The semiconductor substrate 210 has inclined portions 250 on both sides of the initial shallow trench 220, protruding from the initial pad oxide layer 230 and the initial hard mask layer 240 in a first direction aa. The first direction aa can be the arrangement direction of adjacent active regions located on both sides of the initial shallow trench 220, as referenced. Figure 9 This can also be understood as the direction in which one sidewall of the initial shallow trench 220 faces the other sidewall. In this embodiment, the vertical direction of the semiconductor substrate 210 surface can be the second direction bb.

[0059] like Figure 9 As shown, the inclined portion 250 may be the portion of the semiconductor substrate 210 that is extra compared to the semiconductor substrate 210 after the shallow trench 102 is etched in an ideal state. It can be understood that, relative to the opening width of the initial shallow trench 220 along its concave direction, the thickness of the inclined portion 250 in the first direction aa gradually increases from the surface of the substrate 101 toward the bottom of the initial shallow trench 220.

[0060] S120: By etching back through a hard mask, part of the initial pad oxide layer and part of the initial hard mask layer located on the surface of a portion of the active region are removed to obtain the substrate.

[0061] In this embodiment, the surface of the active region 103 covered by part of the initial pad oxide layer 230 and part of the initial hard mask layer 240 is exposed by hard mask pull back. On the one hand, this makes it easier for the subsequent oxidation process to act on the active region 103 and achieve corner rounding. On the other hand, it can also reduce the difficulty of STI filling in the subsequent process, improve the filling quality of STI, and make it less likely to produce voids.

[0062] In this embodiment, as Figure 10 As shown, when the initial hard mask layer 240 is made of silicon nitride, a wet process can be used for SiN pull-back. For example, the initial layer can be soaked in phosphoric acid at 160°C for 50 seconds, followed by soaking in APM at 45°C for 300 seconds. It should be noted that the soaking temperature and time during SiN pull-back can be determined based on the required thickness of the initial pad oxide layer 230 and the initial hard mask layer 240 to be pushed back in the first direction aa.

[0063] In this embodiment, as Figure 10As shown, the substrate 100 may include a substrate 101, on which a shallow trench 102 is formed defining active regions. The shallow trench 102 has exposed first active regions 103 on both sides, and the surface of the first active regions 103 is adjacent to the sidewalls of the shallow trench 102 to form an initial apex region 110. The substrate 101 also has second active regions 104 on both sides of the first active regions 103. The surface of the second active regions 104 is covered with a pad oxide layer 150 and a hard mask layer 160, namely, the remaining initial pad oxide layer 230 and the remaining initial hard mask layer 240 after hard mask back etching.

[0064] In this embodiment, as Figure 10 As shown, the initial apex region 110 has a sharp-angled shape, which is prone to electric field concentration in the working environment, thus affecting the reliability of the semiconductor structure.

[0065] In this embodiment, the shallow trench 102 can be used to fill the isolation material, such as oxide, in subsequent processes to form a shallow trench isolation structure in the shallow trench 102, thereby achieving isolation between adjacent active regions.

[0066] In some embodiments, after step S110, the inclined portion may be changed to the same material as the hard mask layer.

[0067] Because the semiconductor substrate 210 has a tilted portion 250, the irregular morphology may affect the final corner rounding effect achieved by the oxidation process. Therefore, in some embodiments, the tilted portion 250 can be modified to facilitate its removal in subsequent processes, thus avoiding its impact on the corner rounding effect. However, it should be noted that the step of removing the tilted portion 250 is not essential for achieving the technical effect of suppressing active region size reduction in this application; it merely facilitates the formation of a regular oxidation consumption compensation portion, simplifying the process while ensuring the corner rounding effect.

[0068] In some embodiments, such as Figure 11 As shown, nitrogen atoms can be implanted into the tilted portion 250 using an ion implantation process to change the tilted portion 250 to silicon nitride. Thus, if the initial hard mask layer 240 is also made of silicon nitride, the tilted portion 250 can be removed during the subsequent hard mask etch-back process on the initial hard mask layer 240, eliminating the need for an additional step to remove the tilted portion 250 and simplifying the process. In some embodiments, changing the tilted portion 250 to silicon nitride can also be achieved using a decoupled plasma nitride deposition process, using N2 as the ion source.

[0069] like Figure 12As shown, in step S120, the inclined portion 250 can be removed together to reduce the degree of inclination of the sidewall of the shallow trench 102 relative to the second direction bb in the resulting substrate 100.

[0070] S130: Perform an oxidation process on the initial apex region to form the target apex region.

[0071] In this embodiment, as Figure 13 As shown, the initial apex region 110 undergoes an oxidation process, specifically using ROX (Rapid Oxidation) technology or an RTP (Rapid Thermal Processing) platform. This oxidation process smooths the originally sharp initial apex region 110 with the generated silicon dioxide, forming a target apex region 130 with rounded corners compared to the initial apex region 110, thus achieving a corner rounding effect. Simultaneously, it can repair damage to the surface of the initial apex region caused by the previous STI etching process.

[0072] The ratio of silicon dioxide formed by oxidizing silicon using the RTP thermal treatment process is typically 0.45:1, meaning that 0.45 Å of silicon is required to generate 1 Å of silicon dioxide. Therefore, in some embodiments, generating 60 Å of silicon dioxide would require 27 Å of silicon, resulting in a 5.4 nm reduction in the active region size of the semiconductor device and impacting its electrical performance.

[0073] In this embodiment, the oxide formed in the target apex region 130 after the oxidation process can serve as a pad oxide layer 170 (Liner OX) to passivate etching damage and optimize interface quality, thereby improving the oxide filling quality for subsequent STI.

[0074] S140: Reduce at least a portion of the oxide formed in the target apex region to substrate material to compensate for the substrate material consumption of the first active region in the oxidation process.

[0075] Technicians have observed that in some manufacturing processes, after annealing, the oxide thickness on the surface of the active area (AA) of the device is often reduced compared to the oxide thickness on the surface of the dummy active area (Dummy AA). For example, in reference... Figure 14 In the TEM slice image of the 40V high voltage device after the SMT (stress proximity) annealing process, it can be seen that the oxide on the dummy AA is thicker than the oxide on the MV (medium voltage) region.

[0076] To address this phenomenon, technicians, through numerous experiments and theoretical analyses, discovered that the cause lies in the implantation of carbon atoms into the oxide on the active region surface. Under the high-temperature conditions of the annealing process, these carbon atoms undergo a redox reaction with the oxide, reducing some of the oxide to the substrate material, thus leading to a reduction in the original oxide thickness. For example, refer to... Figures 15 to 21 The oxide OX thickness on the surface of AA and Dummy AA is as follows Figure 15 As shown, initially everything was kept consistent, but C atoms were implanted into the oxide on the AA surface. After a subsequent annealing process, as... Figure 16 and Figure 17 As shown, the oxide thickness on the AA surface was found to be 96 Å, and the oxide thickness on the Dummy AA surface was 161 Å. Further, after completing the etching process, as... Figure 18 and Figure 19 As shown, the oxide thickness on the AA surface is 47 Å, and the oxide thickness on the Dummy AA surface is 82 Å. After a SAB (Self-aligned silicide barrier) wet etching process, as shown... Figure 20 As shown, the AA surface is free of oxides, while the oxide thickness on the dummy AA surface is still 60 Å. Finally, surface cleaning is performed using the Siconi process. Figure 21 As shown, the oxides on the surface of the Dummy AA were removed. From Figures 15 to 21 It can be seen that after the annealing process, a thickness difference is generated between the oxides on the surfaces of AA and DummyAA. The oxide thickness on the surface of AA is always thinner than that on the surface of DummyAA. As mentioned earlier, the reason for this phenomenon is that some of the oxides on the surface of AA are reduced to the substrate material during the annealing process.

[0077] In this embodiment, at least a portion of the oxide can be reduced to substrate material by injecting a reducing agent, such as carbon atoms, into the oxide formed in the target apex region and causing a redox reaction between the oxide and the reducing agent.

[0078] Specifically, such as Figure 22 As shown, in some embodiments, carbon atoms can be implanted into the oxide formed in the target apex region 130 using an ion implantation process. Optionally, the implantation energy of the C atoms can be 2 keV, and the implantation dose can be 4.2E16 / cm². In the case of forming 60 Å of silicon dioxide, the implantation depth can be controlled at 55 Å.

[0079] Next, as Figure 23As shown, an annealing process is used to induce a redox reaction between at least some oxides and carbon atoms, resulting in a reduced substrate material 171. Specifically, the annealing temperature can be set within the range of 1000℃ to 1400℃, for example, 1250℃. Under this high temperature condition, silicon dioxide undergoes a redox reaction with the implanted C atoms, with the reaction equation being SiO2 + 2C = 2CO + Si, thereby obtaining the reduced substrate material, i.e., Si. The stoichiometry of SiO2 to C in the reaction is 1:2. (Reference) Figure 23 As can be seen, the substrate material that was originally consumed by oxidation was remade, that is, the substrate material consumption of the first active region 103 in the oxidation process was compensated, and the effect of rounding the top corners was achieved at the same time.

[0080] It should be noted that, in order to... Figure 23 In step S140, the reduced substrate material 171 is distinguished from the original substrate material. Figure 23 The substrate material 171 that was restored was illustrated using different colors. In reality, the restored substrate material 171 could be the same material as the original substrate material.

[0081] S150: Perform STI filling to form a shallow trench isolation structure.

[0082] In this embodiment, as Figure 24 As shown, TEOS is deposited as an isolation material for the opening formed between adjacent target apex regions 130. It can then be annealed at a certain temperature to make the deposited TEOS more dense. It can then be smoothed using a TEOS CMP process, where a hard mask layer 160 can be used as a stop layer, and EPD technology is used to stop the TEOS deposition on the hard mask layer 160.

[0083] Furthermore, the remaining hard mask layer 160 can be removed using a combined process of phosphoric acid and DHF (diluted hydrofluoric acid) to form a layer such as... Figure 25 The shallow trench isolation structure 180 shown is located between adjacent active regions.

[0084] S160: Different types of ion implantation are performed on the active regions located on both sides of the shallow trench isolation structure to form P-type and N-type well regions respectively.

[0085] In this embodiment, as Figure 26As shown, the N-type well region 410 can be fabricated first. After the active region on one side of the shallow trench isolation structure 180 to be implanted with ions is exposed and developed using photolithography, the ion implantation process is performed. Specifically, N-type ions such as phosphorus ions and arsenic ions can be selected, and the implantation can be performed in three stages, each time implanted to a different depth in the substrate, ultimately forming the N-type well region 410.

[0086] Similarly, such as Figure 27 As shown, the photoresist set during the fabrication of the N-type well region 410 is removed first, and then the P-type well region 420 is fabricated. Similarly, the active region on the other side of the shallow trench isolation structure 180 can be exposed and developed using photolithography, followed by ion implantation. Specifically, P-type ions such as B or BF2 can be selected. Since boron ions are relatively light, they can be implanted in four stages, each time to a different depth in the substrate, ultimately forming the P-type well region 420.

[0087] In this embodiment, after the N-type well region 410 and the P-type well region 420 are fabricated, the basic substrate unit of NMOS and PMOS is formed, including the N-type well region 410 and the P-type well region 420, and the shallow trench isolation structure 180 located between the N-type well region 410 and the P-type well region 420.

[0088] In this embodiment, an unexpected effect is that by performing an oxidation process on the initial apex region to form a target apex region with a rounded morphology, thereby achieving the apex rounding effect, the oxide formed by the oxidation consumption of the first active region exposed in the initial apex region is reduced to substrate material to compensate for the consumption of substrate material in the first active region, thereby suppressing the reduction in active region size caused by apex rounding.

[0089] Please see Figures 28 to 33 In some embodiments, in the step of injecting a reducing agent into the oxide formed in the target apex region and causing a redox reaction between the oxide and the reducing agent to reduce at least a portion of the oxide to substrate material, the oxide formed in the target apex region is only partially reduced to substrate material, and the unreduced remaining oxide covers the surface of the reduced substrate material.

[0090] refer to Figure 29 After completing step S130, the dosage of the reducing agent can be controlled so that only the bottom part of the oxide formed in the target corner region 130 is reduced to the substrate material after the annealing process, while the remaining part near the surface is not reduced.

[0091] Specifically, such as Figure 28 As shown, and in combination Figure 13For reference, after completing step S130, the injection dose of carbon atoms can be controlled so that in the oxide formed in the target corner region 130, only the bottom part is reduced to the substrate material after the annealing process, while the rest near the surface is not reduced.

[0092] Then as Figure 29 As shown, an annealing process is used to induce a redox reaction between silicon dioxide and carbon atoms under high temperature conditions. The reaction equation is SiO2 + 2C = 2CO + Si. The annealing temperature can be set in the range of 1000℃ to 1400℃, for example, 1250℃. After the annealing process, the unreduced residual oxide 172 covers the surface of the reduced substrate material.

[0093] Specifically, for example, using the example given in the aforementioned embodiments as a comparison, when forming 60 Å of silicon dioxide in the target apex region, if only a portion of the silicon dioxide needs to be reduced, the carbon atom implantation energy and implantation dose can be adjusted accordingly. If only the bottom 27 Å of silicon dioxide needs to be reduced, the number of molecules can be calculated based on the volume, mass, and molar number of the 27 Å silicon dioxide. Then, based on the reaction equation that each molecule of silicon dioxide requires 2 carbon atoms, the required carbon atom dose can be calculated. Considering other influencing factors in the actual process and the need to compensate for activation losses, the carbon atom implantation dose per unit thickness (1 Å) of oxide can ultimately be adjusted to 6.6E14 / cm. 2 ~8.8E14 / cm 2 Within the range, such as 7E14 / cm 2 To ensure that the implanted carbon atoms completely cover the bottom 27 Å of silicon dioxide, the implantation energy can be adjusted to 1 keV.

[0094] In some embodiments, for the remaining oxides that have not been reduced, a protective layer can be formed on the surface of the reduced substrate material by changing its material composition.

[0095] Specifically, the residual oxide can be converted into silicon carbide as a protective layer. The step of forming a protective layer on the surface of the reduced substrate material by converting the residual oxide can include: implanting carbon atoms into the residual oxide; wherein the carbon atom implantation dose per unit thickness of the residual oxide is controlled to be 9.9E14 / cm². 2 ~13.2E14 / cm 2 Within the range; through the annealing process, the remaining oxides undergo an oxidation-reduction reaction with carbon atoms to obtain a protective layer of silicon carbide.

[0096] In some embodiments, such as Figure 30As shown, carbon atoms are implanted into the remaining oxide 172 again using ion implantation. Since the remaining oxide 172 needs to be converted into silicon carbide, the carbon atom implantation dose needs to be adjusted to allow the carbon atoms to undergo a redox reaction with silicon dioxide at high temperature, with the equation SiO2 + 3C = 2CO + SiC. Furthermore, since carbon atom implantation is performed on the remaining oxide 172 near the surface, the implantation depth and implantation energy also need to be adjusted accordingly. Specifically, for example, using the example given in the previous embodiment as a comparison, with 60 Å of silicon dioxide formed in the target corner region and the bottom 27 Å of silicon dioxide reduced to the substrate material, the number of molecules is calculated based on the volume, mass, and molar number of the remaining 33 Å of silicon dioxide. Then, based on the reaction equation that each molecule of silicon dioxide requires 3 carbon atoms, the required carbon atom dose can be calculated. Considering other influencing factors in the actual process, and to compensate for activation loss, the carbon atom implantation dose per unit thickness of oxide can be adjusted to 9.9E14 / cm. 2 ~13.2E14 / cm 2 Within the range, such as 11E14 / cm 2 The injected energy can be 1keV.

[0097] Next, as Figure 31 As shown, the annealing process is used again to induce a redox reaction between silicon dioxide and carbon atoms. The reaction equation is SiO2 + 3C = 2CO + SiC, where the stoichiometry of C atoms to SiO2 in the reaction is 3:1. The annealing temperature can be set in the range of 1000℃ to 1400℃, for example, 1250℃. In this way, a layer of silicon carbide can be formed in the shallow trench 102 and the first active region 103 on both sides as a protective layer 190.

[0098] In some embodiments, the protective layer 190 can be used to suppress the diffusion of doped ions into the shallow trench isolation structure. As mentioned earlier, a drop in the threshold voltage of the device is common in related technologies, partly due to the diffusion of B ions doped in the active region into the STI. By forming a protective layer 190 made of silicon carbide, the high carbon-silicon bond energy in SiC makes it difficult for B ions or BF2 ions doped in the active region to diffuse across the SiC protective layer 190 into the STI.

[0099] Furthermore, the silicon carbide protective layer 190 can also be used to generate tensile stress in the channel regions on both sides of the shallow trench 102, improving electron mobility and thus increasing device speed. Specifically, the lattice constant of silicon is 5.431 Å, and the lattice constant of C is 3.57 Å. The mismatch rate between Si and C is 34.27%, which makes the lattice constant of SiC smaller than that of Si. Moreover, the lattice constant of C is much smaller than that of silicon. Therefore, SiC only needs fewer C atoms to obtain higher stress. Thus, SiC generates tensile stress in the transverse channel through STI, thereby deforming the channel lattice and increasing its size.

[0100] In some embodiments, such as Figure 32 and Figure 33 As shown, TEOS is deposited as an isolation material for the opening formed between adjacent target apex regions 130. It can then be annealed at a certain temperature to make the deposited TEOS more dense. It can then be smoothed using a TEOS CMP process, where a hard mask layer 160 can be used as a stop layer, and EPD technology is used to stop the TEOS deposition on the hard mask layer 160.

[0101] Furthermore, the remaining hard mask layer 160 can be removed using a combination of phosphoric acid and DHF (diluted hydrofluoric acid) to form a shallow trench isolation structure 180. Subsequently, the P-type and N-type well regions can be prepared, referring to step S160 in the aforementioned embodiments, which will not be elaborated further here.

[0102] refer to Figure 29 In some embodiments, the surface of the reduced substrate material is flush with the height of the surface of the second active region 104. Specifically, the reducing agent may be carbon atoms, wherein the carbon atom implantation dose per unit thickness of oxide can be controlled to be 6.6E14 / cm. 2 ~8.8E14 / cm 2 Within a certain range, and by controlling the annealing time, the surface of the reduced substrate material is made flush with the surface of the second active region 104. By keeping the surface of the reduced substrate material flush with the surface of the second active region 104, the morphology of the active region can be made more regular, and it is less likely to produce height differences in different areas of the same layer, which is beneficial to improving the stability and reliability of the device obtained by subsequent processes.

[0103] Another embodiment of this application provides a semiconductor structure, which is prepared using the semiconductor structure preparation method described in the foregoing embodiments.

[0104] It is understood that the specific examples in this document are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of the invention.

[0105] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0106] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0107] It is understood that in the description of this application, when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it may mean that it is directly above another layer or region, or that it contains other layers or regions between itself and another layer or region. Furthermore, if the component is flipped, the layer or region will be located "below" or "under" another layer or region.

[0108] The above description is merely a specific embodiment of this application, but the protection scope of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A substrate is provided; the substrate includes a base, the base having shallow trenches forming defined active regions; wherein, the shallow trenches have exposed first active regions on both sides, and the surfaces of the first active regions are adjacent to the sidewalls of the shallow trenches to form initial apex regions; An oxidation process is performed on the initial apex region to form a target apex region, which has a rounded corner shape compared to the initial apex region; Carbon atoms are injected into the oxide formed in the target apex region as a reducing agent, and an annealing process is used to cause at least a portion of the oxide to undergo a redox reaction with the carbon atoms, reducing at least a portion of the oxide formed in the target apex region to substrate material silicon, in order to compensate for the substrate material consumption of the first active region in the oxidation process.

2. The preparation method according to claim 1, characterized in that, In the step of injecting carbon atoms as a reducing agent into the oxide formed in the target apex region and reducing at least a portion of the oxide to silicon substrate material through an annealing process, the oxide formed in the target apex region is only partially reduced to the substrate material, and the unreduced remaining oxide covers the surface of the reduced substrate material; the preparation method further includes: By transforming the material of the remaining oxide, a protective layer is formed on the surface of the reduced substrate material. The protective layer is used to suppress the diffusion of doped ions into the shallow trench isolation structure, wherein the shallow trench isolation structure is formed in the shallow trench.

3. The preparation method according to claim 2, characterized in that, In the step of forming a protective layer on the surface of the reduced substrate material by converting the material of the remaining oxide, the remaining oxide is converted into silicon carbide material.

4. The preparation method according to claim 3, characterized in that, The step of forming a protective layer on the surface of the reduced substrate material by transforming the material of the remaining oxide includes: Carbon atoms are implanted into the remaining oxide; wherein the carbon atom implantation dose per unit thickness of the remaining oxide is controlled to be 9.9E14 / cm. 2 ~13.2E14 / cm 2 Within the range; The remaining oxides undergo a redox reaction with carbon atoms through an annealing process to obtain a protective layer of silicon carbide.

5. The preparation method according to claim 2, characterized in that, The substrate also has a second active region on both sides of the first active region; wherein the surface of the reduced substrate material is flush with the surface of the second active region.

6. The preparation method according to claim 5, characterized in that, By controlling the carbon atom implantation dose in the oxide per unit thickness at 6.6E14 / cm 2 ~8.8E14 / cm 2 Within a certain range, and by controlling the annealing time, the surface of the reduced substrate material is made flush with the surface of the second active region.

7. The preparation method according to claim 4, characterized in that, The silicon carbide protective layer is also used to generate tensile stress in the channel areas on both sides of the shallow trench.

8. A semiconductor structure, characterized in that, The semiconductor structure is prepared using the semiconductor structure preparation method described in any one of claims 1 to 7.

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