An insulated gate bipolar transistor device and a method of manufacturing the same

Abstract

The embodiment of the application provides an insulated gate bipolar transistor device and a preparation method thereof, the method comprises the following steps: a substrate layer, a carrier storage layer, a super-junction P column, a P-type base region, a first gate, a second gate, a carrier blocking layer, an N-type emitter region, a dielectric layer, a P-type contact hole doped region, an emitter, a field cutoff layer, a P-type collector region and a collector. The carrier storage layer enhances the conductance modulation effect. The super-junction structure improves the withstand voltage capability of the device, accelerates the carrier extraction and reduces the switching loss. When the device is turned on, the super-junction P column can extract the holes of the P-type base region, and in combination with the carrier blocking layer, the hole extraction rate can be controlled, the potential rise of the P-type base region is limited, and the noise is inhibited. When the device is turned off, the carrier blocking layer forms an inversion layer, a hole channel is formed between the first gate and the second gate, the hole extraction rate is accelerated, the turn-off speed is improved, and the turn-off loss is reduced, so that the relationship among the conduction voltage drop, the switching loss and the noise is balanced.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor technology, and in particular to an insulated gate bipolar transistor device and its fabrication method. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs) are semiconductor devices widely used in power electronics. IGBTs, with their unique structure, combine the easy controllability of MOSFETs with the high current capacity of bipolar transistors, making them a core component of modern power conversion systems. In recent years, with the rapid development of power electronics technology, the demand for IGBTs in high-power, high-frequency applications has increased significantly. However, the on-state voltage drop and switching losses of IGBTs are mutually restrictive, and the EMI (electromagnetic interference) noise generated by high-frequency applications also poses new requirements for IGBTs. Therefore, how to balance the on-state voltage drop, switching losses, and EMI noise of IGBTs has become a major research topic. Summary of the Invention

[0003] To address the aforementioned problems, this invention discloses an insulated gate bipolar transistor device and its fabrication method.

[0004] In a first aspect, embodiments of the present invention provide an insulated gate bipolar transistor device, comprising:

[0005] Substrate layer;

[0006] A carrier storage layer is disposed above the substrate layer;

[0007] A superjunction P-pillar is disposed within a first trench; the first trench is disposed within the carrier storage layer and the substrate layer;

[0008] A P-type base region is disposed above the superjunction P-pillar and the carrier storage layer;

[0009] A first gate is disposed within a second trench; the second trench is disposed within a first region of the P-type base region and the carrier storage layer.

[0010] The second gate is disposed within the third trench; the third trench is disposed within the second region of the P-type base region and the superjunction P-pillar.

[0011] A carrier blocking layer is disposed within the P-type base region and located on both sides of the second gate;

[0012] The N-type emitter region is located within the P-type base region and on the side of the first gate away from the second gate;

[0013] A dielectric layer is disposed above the P-type base region in the region corresponding to the first gate and the second gate;

[0014] The P-type contact hole doped region is located above the P-type base region and in the region other than the carrier blocking layer and the N-type emitter region;

[0015] An emitter is disposed above the dielectric layer and the doped region of the P-type contact hole;

[0016] A field cutoff layer is disposed below the substrate layer;

[0017] The P-type collector region is located below the field cutoff layer;

[0018] The collector is located below the P-type collector region.

[0019] Optionally, the number of the first gate and the second gate is 2; the two second gates are arranged between the two first gates.

[0020] Optionally, the carrier blocking layer is disposed within the P-type base region and located between the first gate and the second gate, and between the two second gates;

[0021] The carrier blocking layer between the first gate and the second gate is configured to be a full blocking layer, and the carrier blocking layer between the two second gates is configured to be a partial blocking layer.

[0022] Optionally, the first gate includes upper and lower parts, with an oxide layer disposed between the upper half and the lower half of the first gate.

[0023] Optionally, the upper half of the first gate is connected to the gate electrode, and the second gate is connected to the emitter.

[0024] Optionally, the P-type base region is connected to the emitter.

[0025] Optionally, the doping concentration of the carrier storage layer, the superjunction P-pillar, and the field stop layer is higher than the doping concentration of the substrate layer;

[0026] The doping concentration of the P-type collector region is higher than the doping concentration of the field stop layer;

[0027] The doping concentration of the P-type base region is higher than that of the superjunction P-pillar;

[0028] The doping concentrations of the N-type emitter region, the carrier blocking layer, and the P-type contact hole doped region are higher than the doping concentration of the P-type base region.

[0029] Secondly, embodiments of the present invention provide a method for fabricating an insulated gate bipolar transistor device, the method comprising:

[0030] Provide a substrate layer;

[0031] A carrier storage layer is formed above the substrate layer;

[0032] The carrier storage layer and the substrate layer are etched to form a first trench, and P-type silicon material is filled in the first trench to form a superjunction P-pillar;

[0033] A P-type base region is formed above the superjunction P-pillar and the carrier storage layer;

[0034] A second trench is formed in the first region of the P-type base region and the carrier storage layer, and a first gate is filled in the second trench;

[0035] A third trench is formed in the second region of the P-type base region and the superjunction P-pillar, and a second gate is filled in the third trench;

[0036] N-type ions are implanted into the P-type base region to form a carrier blocking layer; the carrier blocking layer is located on both sides of the second gate.

[0037] N-type ions are implanted into the P-type base region to form an N-type emitter region; the N-type emitter region is located on the side of the first gate away from the second gate;

[0038] A dielectric layer is formed in the region above the P-type base region corresponding to the first gate and the second gate;

[0039] Above the P-type base region, P-type ions are implanted into the region other than the carrier blocking layer and the N-type emitter region to form a P-type contact hole doped region.

[0040] An emitter is formed above the dielectric layer and the doped region of the P-type contact hole;

[0041] N-type ions are implanted beneath the substrate to form a field cutoff layer;

[0042] P-type ions are injected below the field cutoff layer to form a P-type collector region;

[0043] A collector electrode is formed below the P-type collector electrode region.

[0044] Optionally, the implantation of N-type ions into the P-type base region to form a carrier blocking layer includes:

[0045] N-type ions are implanted in the P-type base region and located between the first gate and the second gate and between the two second gates to form the carrier blocking layer; the carrier blocking layer between the first gate and the second gate is a full blocking layer, and the carrier blocking layer between the two second gates is a partial blocking layer.

[0046] Optionally, the method further includes:

[0047] An oxide layer is provided in the first gate to divide the first gate into an upper half and a lower half.

[0048] Optionally, the method further includes:

[0049] The upper half of the first gate is connected to the gate electrode, and the second gate is connected to the emitter.

[0050] Thirdly, the present invention discloses a chip comprising an insulated gate bipolar transistor device as described above.

[0051] The embodiments of this invention include the following advantages: The insulated gate bipolar transistor (IGBT) device comprises: a substrate layer, a carrier storage layer, a superjunction P-pillar, a P-type base region, a first gate, a second gate, a carrier blocking layer, an N-type emitter region, a dielectric layer, a P-type contact hole doped region, an emitter, a field cutoff layer, a P-type collector region, and a collector. The design of the carrier storage layer enhances the conductivity modulation effect and reduces the on-state voltage drop. The superjunction structure improves the device's breakdown voltage, and the transverse electric field generated when the N-pillar and P-pillar deplete each other accelerates carrier extraction, reducing switching losses. Since the top of the P-pillar connects to the P-type base region, a hole path is formed around the second gate. When the device is turned on, holes in the P-type base region can be extracted. Simultaneously, combined with the carrier blocking layer, the hole extraction rate can be controlled, limiting the rise of the P-type base region potential and suppressing EMI noise. When the device is turned off, the carrier blocking layer forms an inversion layer, and a hole path can be formed between the first gate and the second gate, which accelerates the hole extraction rate, increases the turn-off speed, and reduces the turn-off loss. This allows for a better balance between on-state voltage drop, switching loss, and EMI noise. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a structural block diagram of an insulated gate bipolar transistor device according to an embodiment of the present invention;

[0054] Figure 2 This is a flowchart illustrating the steps of a method for fabricating an insulated gate bipolar transistor device according to an embodiment of the present invention.

[0055] Figure 3 This is a logic diagram of a method for fabricating an insulated gate bipolar transistor device according to an embodiment of the present invention.

[0056] Explanation of reference numerals in the attached figures:

[0057] Substrate 1, carrier storage layer 2, superjunction P pillar 3, P-type base region 4, first gate 5, second gate 6, carrier blocking layer 7, N-type emitter region 8, dielectric layer 9, P-type contact hole doped region 10, emitter 11, field cutoff layer 12, P-type collector region 13, collector 14. Detailed Implementation

[0058] This invention proposes an insulated-gate bipolar transistor (IGBT) device aimed at balancing the on-state voltage drop, switching losses, and EMI noise. To achieve this goal, embodiments of this invention introduce a split-gate structure, an alternating gate structure, a carrier storage layer, a superjunction structure, and a carrier blocking layer into a trench IGBT, forming a novel IGBT structure. This structure better balances the relationship between on-state voltage drop, switching losses, and EMI noise, reducing the device's on-state voltage drop and switching losses while suppressing EMI noise, thus improving the overall performance of the device.

[0059] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0060] Reference Figure 1 This diagram illustrates a structural block diagram of an insulated-gate bipolar transistor (IGBT) device according to an embodiment of the present invention. The IGBT device includes:

[0061] Substrate 1;

[0062] A carrier storage layer 2 is disposed above the substrate layer 1;

[0063] A superjunction P-pillar 3 is disposed within a first trench; the first trench is disposed within the carrier storage layer 2 and the substrate layer 1;

[0064] The P-type base region 4 is located above the superjunction P-pillar 3 and the carrier storage layer 2;

[0065] A first gate 5 is disposed within a second trench; the second trench is disposed within the first region of the P-type base region 4 and the carrier storage layer 2.

[0066] The second gate 6 is disposed in the third trench; the third trench is disposed in the second region of the P-type base region 4 and the superjunction P-pillar 3.

[0067] A carrier blocking layer 7 is disposed within the P-type base region 4 and located on both sides of the second gate 6;

[0068] The N-type emitter region 8 is disposed within the P-type base region 4 and located on the side of the first gate 5 away from the second gate 6;

[0069] Dielectric layer 9 is disposed above the P-type base region 4 in the region corresponding to the first gate 5 and the second gate 6;

[0070] The P-type contact hole doped region 10 is disposed above the P-type base region 4 and located in the region other than the carrier blocking layer 7 and the N-type emitter region 8;

[0071] An emitter 11 is disposed above the dielectric layer 9 and the doped region 10 of the P-type contact hole;

[0072] A field cutoff layer 12 is disposed below the substrate layer 1;

[0073] The P-type collector region 13 is located below the cutoff layer 12;

[0074] Collector 14 is located below the P-type collector region 13.

[0075] In this embodiment of the invention, the insulated gate bipolar transistor (IGBT) device includes a substrate layer, a carrier storage layer, a superjunction P-pillar, a P-type base region, a first gate, a second gate, a carrier blocking layer, an N-type emitter region, a dielectric layer, a P-type contact hole doped region, an emitter, a field cutoff layer, a P-type collector region, and a collector. The carrier storage layer is disposed above the substrate layer; the superjunction P-pillar is disposed within a first trench between the carrier storage layer and the substrate layer; the P-type base region is disposed above the superjunction P-pillar and the carrier storage layer; the first gate is located in a second trench, passing through the P-type base region and the carrier storage layer; the second gate is located in a third trench, passing through the P-type base region and extending into the superjunction P-pillar; the N-type emitter region is located on the side of the first gate away from the second gate and serves as the electron source; the P-type contact hole doped region is located above the P-type base region, making metal contact with the emitter to form an ohmic contact, ensuring the stability of the P-type base region potential and leading out… Hole current; the carrier blocking layer is located in the P-type base region and on both sides of the second gate, which can prevent holes below the P-type base region from being directly drawn upward by the emitter, forcing holes to flow laterally when turned on, thereby enhancing the conductivity modulation effect of the carrier storage layer and reducing the on-state voltage drop; the dielectric layer can wrap the first gate and the second gate; the emitter metal covers the entire top of the cell; the field cutoff layer can prevent the depletion region from penetrating to the collector, thereby further optimizing the trade-off between saturation voltage drop and turn-off loss; the P-type collector region is the hole injection source; the collector metal can collect current.

[0076] This invention, through the design of a carrier storage layer, enhances the conductivity modulation effect and reduces the on-state voltage drop. The superjunction structure improves the device's breakdown voltage, and the lateral electric field generated when the N-pillars and P-pillars deplete each other accelerates carrier extraction, reducing switching losses. Since the top of the P-pillar connects to the P-type base region, a hole path is formed around the second gate. When the device is turned on, holes in the P-type base region can be extracted. Simultaneously, combined with the carrier blocking layer, the hole extraction rate can be controlled, limiting the rise of the P-type base region potential and suppressing EMI noise. When the device is turned off, the carrier blocking layer forms an inversion layer, creating a hole path between the first and second gates, accelerating the hole extraction rate, increasing the turn-off speed, and reducing turn-off losses.

[0077] In one embodiment, the number of the first gate 5 and the second gate 6 is 2; the two second gates 6 are arranged between the two first gates 5.

[0078] In this embodiment of the invention, there are two first gates and two second gates, with two second gates arranged between two first gates. That is, the arrangement of the first and second gates is: first gate, second gate, second gate, first gate. This alternating arrangement of the first and second gates forms a periodic capacitor structure. Through capacitive coupling, the electric field distribution is dynamically adjusted, and the capacitor effect can suppress rapid changes in the electric field, reducing transient electric field spikes. The alternating arrangement of the first and second gates results in a more uniform distribution of charge carriers (electrons and holes), reducing localized high electric fields caused by charge concentration.

[0079] In one embodiment, the carrier blocking layer 7 is disposed within the P-type base region 4 and located between the first gate 5 and the second gate 6 and between the two second gates 6; the carrier blocking layer 7 disposed between the first gate 5 and the second gate 6 is a full blocking layer, and the carrier blocking layer 7 located between the two second gates 6 is a partial blocking layer.

[0080] In this embodiment of the invention, the design of the carrier storage layer can enhance the conductivity modulation effect and reduce the on-state voltage drop. By introducing a carrier blocking layer inside the P-type base region between the first gate and the second gate, and between the two second gates, holes can be blocked from entering the emitter when the device is turned on, further enhancing the conductivity modulation effect. Specifically, the carrier blocking layer between the first gate and the second gate is a full block, which can prevent holes from flowing out of the emitter, while the carrier blocking layer between the two second gates is a partial block, which can extract holes from the P-type base region.

[0081] In one embodiment, the first gate 5 includes upper and lower parts, and an oxide layer is provided between the upper half and the lower half of the first gate 5.

[0082] In this embodiment of the invention, an oxide layer is disposed in the first gate, dividing the first gate into an upper half and a lower half. The split-gate design in the first gate structure reduces the area of ​​the gate and collector facing each other, further reducing the gate capacitance and charging charge of the device, improving the switching speed of the device, and reducing switching losses.

[0083] In one embodiment, the upper half of the first gate 5 is connected to the gate electrode, the second gate 6 is connected to the emitter 11, and the P-type base region 4 is connected to the emitter 11.

[0084] In this embodiment of the invention, the second gate is connected to the emitter; the P-type base regions between the first and second gates, and between the second gates, are all in contact with the emitter; the first gate adopts a split gate design, isolating the polysilicon through a dielectric layer, wherein the upper half of the polysilicon is connected to the gate electrode (not shown in the figure), and the lower half of the polysilicon is floating. Due to the potential difference between the first and second gates, the distribution of the electric field in the trench region is dynamically adjusted to achieve a uniform electric field distribution. For example, during the turn-off process, the gate voltage decreases, the potential gradient in the first gate region is suppressed, and the emitter in the second gate region achieves a uniform electric field distribution through charge accumulation and potential buffering.

[0085] In the PNP structure of IGBT, the P-type base region is the base and needs to be fixed at a specific potential. By shorting it to the emitter (cathode), the potential of the P-type base region can be fixed at the emitter potential. This ensures that the P-type base region is short-circuited, and its base-emitter voltage is 0, thereby suppressing the conduction of parasitic NPN transistors and preventing IGBT runaway and damage.

[0086] In one embodiment, the doping concentrations of the carrier storage layer 2, the superjunction P-pillar 3, and the field cutoff layer 12 are higher than the doping concentration of the substrate layer 1; the doping concentration of the P-type collector region 13 is higher than the doping concentration of the field cutoff layer 12; the doping concentration of the P-type base region 4 is higher than the doping concentration of the superjunction P-pillar 3; and the doping concentrations of the N-type emitter region 8, the carrier blocking layer 7, and the P-type contact hole doped region 10 are higher than the doping concentration of the P-type base region 4.

[0087] In this embodiment of the invention, the higher doping concentration of the P-type base region compared to the superjunction P-pillar ensures that the MOS channel is formed in the P-base rather than in the superjunction P-pillar, guaranteeing normal gate control. The higher doping concentration of the N-type emitter region and the P-type contact hole region compared to the P-type base region ensures good ohmic contact with the metal and provides a sufficient electron source, while stabilizing the P-base potential and providing an efficient path for hole outflow, effectively suppressing parasitic NPN conduction and latch-up effects. The higher doping concentration of the carrier blocking layer compared to the P-type base region ensures that the carrier blocking layer effectively blocks upward movement of holes, forcing holes to remain in the drift region for a longer time and enhancing the conductivity modulation effect.

[0088] Reference Figure 2 The diagram illustrates a step-by-step flowchart of a method for fabricating an insulated-gate bipolar transistor device according to an embodiment of the present invention. The method specifically includes the following steps:

[0089] Step 201, Provide a substrate layer;

[0090] In this embodiment of the invention, the substrate can be a silicon-based N-type doped substrate. During the fabrication process, the substrate surface can be cleaned to remove surface contaminants, preparing it for ion implantation. Then, an oxide layer is deposited on the substrate surface to reduce lattice damage and defects caused by subsequent ion implantation, thereby reducing physical damage to the substrate. Simultaneously, it prevents oxidation or contamination of the substrate surface at high temperatures during the annealing process after ion implantation, maintaining surface cleanliness and providing a good foundation for subsequent processes.

[0091] Step 202: Form a carrier storage layer over the substrate layer;

[0092] In this embodiment of the invention, the specific process of forming the carrier storage layer can be as follows: depositing an oxide layer on the surface of the substrate layer, performing N-type ion implantation and thermal annealing on the surface of the substrate layer to form the carrier storage layer, wherein the temperature of the thermal annealing treatment is higher than 1000°C, and the doping concentration of the carrier storage layer is higher than the doping concentration of the substrate layer.

[0093] Step 203: Etch the carrier storage layer and the substrate layer to form a first trench, and fill the first trench with P-type silicon material to form a superjunction P-pillar;

[0094] In this embodiment of the invention, the specific process for fabricating the trench of the superjunction P-pillar is as follows: an oxide layer is deposited on the surface of a substrate, and a layer of photoresist is spin-coated onto the oxide layer. A first trench etching window for the superjunction P-pillar is formed through photolithography and etching processes. Then, the photoresist is removed, leaving the oxide layer as a mask. The first trench for fabricating the superjunction P-pillar is formed through dry etching. P-type silicon material is filled into the first trench to form the superjunction P-pillar. The superjunction structure can improve the breakdown voltage of the device. Simultaneously, by utilizing the lateral electric field when the N-pillar and P-pillar deplete each other, carrier extraction can be accelerated, reducing switching losses.

[0095] Step 204: A P-type base region is formed above the superjunction P-pillar and the carrier storage layer;

[0096] In this embodiment of the invention, the specific process for forming the P-type base region is as follows: a P-type epitaxial layer is grown above the superjunction P-pillar and the carrier storage layer to form the P-type base region, or an N-type epitaxial layer is grown, and the P-type base region is formed by P-type ion implantation and thermal annealing. The P-type epitaxy method has advantages in doping control, process simplicity, and material quality, while the N-type epitaxy plus ion implantation method has advantages in flexibility and process compatibility. The actual choice can be made based on a comprehensive consideration of specific needs.

[0097] Step 205: A second trench is formed in the first region of the P-type base region and the carrier storage layer, and a first gate is filled in the second trench; an oxide layer is formed in the first gate to divide the first gate into an upper half and a lower half;

[0098] In this embodiment of the invention, the first region of the P-type base region is the region in contact with the carrier storage layer. The second trench is disposed in the first region of the P-type base region and the carrier storage layer, and the first gate is filled in the second trench. The specific process for forming the first gate is as follows: the sacrificial oxide layer is removed, and a trench sidewall oxide layer is generated by thermal oxidation. Then, a layer of polysilicon is deposited on the surface of the P-type base region to fill the interior of the first gate trench, and excess polysilicon on the surface is removed. Afterward, an oxide layer is deposited on the surface of the P-type base region, and a layer of photoresist is spin-coated on the oxide layer surface. The first gate etching window is formed by photolithography and etching processes. By controlling the dry etching depth, a certain depth of polysilicon and the corresponding depth of trench sidewall oxide layer in the first gate trench are removed, and the remaining polysilicon is retained. An oxide layer is grown on the exposed polysilicon surface and the trench sidewall by thermal oxidation, which is the gate oxide layer of the first gate, and is also used to isolate the remaining polysilicon in the trench. Then, the surface oxide layer is removed. A layer of polysilicon is deposited on the surface to fill the interior of the first gate trench, and then the polysilicon on the surface of the P-type base region is removed by wet etching. An oxide layer is disposed in the first gate, dividing the first gate into an upper and lower half. The first gate structure employs a split-gate design, which reduces the area of ​​the gate and collector facing each other, further reducing the gate capacitance and charging charge of the device, improving the switching speed, and reducing switching losses.

[0099] Step 206: A third trench is formed in the second region of the P-type base region and the superjunction P-pillar, and a second gate is filled in the third trench;

[0100] In this embodiment of the invention, the second region of the P-type base region corresponds to the region of the superjunction P-pillar. A third trench is disposed in the second region of the P-type base region and the superjunction P-pillar, and the second gate is filled in the third trench. There are two first gates and two second gates, arranged between the two first gates, i.e., the arrangement of the first and second gates is: first gate, second gate, second gate, first gate. The alternating gate structure formed by the first and second gates optimizes the electric field distribution and reduces gate capacitance. Since the top of the superjunction P-pillar connects to the P-type base region, a hole path is formed around the second gate. When the device is turned on, holes in the P-type base region between the first and second gates can be extracted. Simultaneously, combined with the carrier blocking layer between the second gates, the hole extraction rate can be controlled, limiting the rise of the P-type base region potential between the first and second gates and suppressing EMI noise. When the device is turned off, the carrier blocking layer forms an inversion layer, and hole paths can be formed between the first and second gates and between the two second gates, accelerating the hole extraction rate, increasing the turn-off speed, and reducing turn-off losses.

[0101] Step 207: N-type ions are implanted into the P-type base region to form a carrier blocking layer; the carrier blocking layer is located on both sides of the second gate; N-type ions are implanted into the P-type base region and located between the first gate and the second gate and between the two second gates to form the carrier blocking layer; the carrier blocking layer between the first gate and the second gate is a full blocking layer, and the carrier blocking layer between the two second gates is a partial blocking layer.

[0102] Step 208: N-type ions are implanted into the P-type base region to form an N-type emitter region; the N-type emitter region is located on the side of the first gate away from the second gate;

[0103] In this embodiment of the invention, the specific process of forming a carrier blocking layer and an N-type emitter region on the surface of the P-type base region is as follows: an oxide layer is deposited on the surface of the P-type base region, and a photoresist layer is spin-coated on the oxide layer surface. A carrier blocking layer injection window is formed through photolithography and etching processes. An N-type ion implantation is then performed to form the carrier blocking layer. The photoresist is removed, and the N-type emitter region is formed using the same method. The design of the carrier storage layer can enhance the conductivity modulation effect and reduce the on-state voltage drop. By introducing a carrier blocking layer inside the P-type base region between the first gate and the second gate, and between the two second gates, holes can be blocked from entering the emitter when the device is turned on, further enhancing the conductivity modulation effect. Specifically, the carrier blocking layer between the first gate and the second gate is a full block, preventing holes from flowing out of the emitter, while the carrier blocking layer between the two second gates is a partial block, allowing holes to be extracted from the P-type base region. The carrier blocking layer located inside the P-type base region between the two second gates can adjust the injection window and control the hole extraction rate according to the actual application requirements of dI / dt and dV / dt when the IGBT is turned on, thereby enhancing the conductivity modulation effect. It can also work in synergy with the gate resistor to regulate dI / dt and dV / dt, thereby suppressing EMI noise while reducing on-state voltage drop and turn-on loss.

[0104] Step 209: A dielectric layer is formed in the region above the P-type base region corresponding to the first gate and the second gate;

[0105] Step 210: Above the P-type base region, P-type ions are implanted into the region other than the carrier blocking layer and the N-type emitter region to form a P-type contact hole doped region;

[0106] Step 211: An emitter is formed above the dielectric layer and the doped region of the P-type contact hole;

[0107] In this embodiment of the invention, the specific process of forming a P-type contact hole doped region and an emitter on the surface of the dielectric layer is as follows: a layer of photoresist is spin-coated on the surface of the dielectric layer, and an emitter metal contact hole etching window is formed by photolithography and etching processes; the dielectric layer is etched, and then a P-type contact hole doped region is formed by P-type ion implantation; the photoresist is removed, and emitter metal is sputtered on the surface of the dielectric layer to form an emitter that is in contact with the surface of the P-type base region.

[0108] Step 212: N-type ions are implanted beneath the substrate layer to form a field cutoff layer;

[0109] Step 213: P-type ions are implanted below the field cutoff layer to form a P-type collector region;

[0110] Step 214: A collector electrode is formed below the P-type collector electrode region.

[0111] In this embodiment of the invention, the specific process for forming the field cutoff layer, the P-type collector region, and the collector is as follows: the lower surface of the substrate layer is thinned, and high-energy N-type ion implantation is performed to form the field cutoff layer; then, P-type ion implantation is performed to form the P-type collector region; subsequently, the lower surface of the substrate layer is laser-annealed to activate the implanted ions; finally, collector metal is sputtered onto the lower surface of the substrate layer to form the collector. Thus, the fabrication of the IGBT in this embodiment of the invention is completed.

[0112] In this embodiment of the invention, the first and second gates form an alternating gate structure, which optimizes the electric field distribution and reduces gate capacitance. A split gate design is employed in the first gate structure, reducing the area of ​​the gate and collector facing each other, further reducing the gate capacitance and charging charge, improving the switching speed, and reducing switching losses. The carrier storage layer design enhances the conductivity modulation effect and reduces the on-state voltage drop. By introducing a carrier blocking layer between the first and second gates and inside the P-type base region between the two second gates, holes can be blocked from entering the emitter when the device is turned on, further enhancing the conductivity modulation effect. Specifically, the carrier blocking layer between the first and second gates is a full block, preventing holes from flowing out of the emitter, while the carrier blocking layer between the two second gates is a partial block, allowing holes to be extracted from the P-type base region. The superjunction structure improves the device's breakdown voltage, and the transverse electric field generated when the N-pillars and P-pillars deplete each other accelerates carrier extraction and reduces switching losses. Because the top of the P-pillar connects to the P-type base region, a hole path is formed around the second gate. When the device is turned on, holes can be extracted from the P-type base region between the first and second gates. Simultaneously, combined with the carrier blocking layer between the second gates, the hole extraction rate can be controlled, limiting the rise in the P-type base region potential between the first and second gates and suppressing EMI noise. When the device is turned off, the carrier blocking layer forms an inversion layer, creating hole paths between the first and second gates, and between the two second gates, accelerating the hole extraction rate, increasing the turn-off speed, and reducing turn-off losses.

[0113] Reference Figure 3 The diagram illustrates a logic diagram of a method for fabricating an insulated gate bipolar transistor device according to an embodiment of the present invention. To enable those skilled in the art to better understand the embodiments of the present invention, the following explanation is provided... Figure 3 The embodiments of the present invention are described below:

[0114] Step 301: Provide a silicon-based N-type doped substrate; clean the surface of the substrate; deposit an oxide layer on the surface of the substrate; perform N-type ion implantation and thermal annealing on the surface of the substrate to form a carrier storage layer; wherein the temperature of the thermal annealing on the surface of the substrate is higher than 1000°C, and the doping concentration of the carrier storage layer is higher than the doping concentration of the substrate.

[0115] In this embodiment of the invention, cleaning the substrate surface removes surface contaminants, preparing it for ion implantation. Depositing an oxide layer on the substrate surface reduces lattice damage and defects caused by subsequent ion implantation, thereby minimizing physical damage to the substrate. Furthermore, it prevents oxidation or contamination of the substrate surface at high temperatures during the annealing process after ion implantation, maintaining surface cleanliness and providing a good foundation for subsequent processes.

[0116] Step 302: A trench for fabricating a superjunction P-pillar is formed on the surface of the substrate; P-type silicon material is filled into the trench to form a superjunction P-pillar; the surface oxide layer is removed to form a P-type base region on the surface of the substrate; wherein the doping concentration of the superjunction P-pillar is higher than that of the N-type substrate, and the doping concentration of the P-type base region is higher than that of the substrate and the superjunction P-pillar.

[0117] In this embodiment of the invention, the specific process for fabricating the trenches of the superjunction P-pillar is as follows: an oxide layer is deposited on the surface of the substrate, and a layer of photoresist is spin-coated onto the oxide layer. The trench etching window of the superjunction P-pillar is formed through photolithography and etching processes. Then, the photoresist is removed, leaving the oxide layer as a mask, and the trenches for fabricating the superjunction P-pillar are formed through dry etching. The specific process for forming the P-type base region is as follows: a P-type epitaxial layer is grown on the surface of the substrate to form the P-type base region, or an N-type epitaxial layer is grown, and the P-type base region is formed through P-type ion implantation and thermal annealing. The P-type epitaxy method has advantages in doping control, process simplicity, and material quality, while the N-type epitaxy plus ion implantation method has advantages in flexibility and process compatibility. The actual choice can be made based on a comprehensive consideration of specific requirements.

[0118] Step 303: A first gate trench and a second gate trench are formed on the surface of the P-type base region; polysilicon is filled inside the first gate trench to form a first gate; polysilicon is filled inside the second gate trench to form a second gate; the polysilicon in the first gate trench is divided into upper and lower parts and isolated in the middle by an oxide layer; the upper part of the polysilicon in the first gate is connected to the gate electrode, the lower part of the polysilicon is floating, and the second gate is connected to the emitter.

[0119] In this embodiment of the invention, the specific process of forming a gate trench on the surface of the P-type base region is as follows: an oxide layer is deposited on the surface of the P-type base region, and a layer of photoresist is spin-coated on the oxide layer. A gate trench etching window is formed through photolithography and etching processes. The photoresist is removed, and the oxide layer is retained as a mask. The gate trench is then formed by dry etching. A sacrificial oxide layer is generated through thermal oxidation to repair surface damage in the trench.

[0120] The specific process for forming the first gate is as follows: The sacrificial oxide layer is removed, and a trench sidewall oxide layer is generated through thermal oxidation. Then, a layer of polysilicon is deposited on the surface of the P-type base region to fill the interior of the first gate trench, and excess polysilicon on the surface is removed. Next, an oxide layer is deposited on the surface of the P-type base region, and a layer of photoresist is spin-coated onto the oxide layer surface. The first gate etching window is formed through photolithography and etching processes. By controlling the dry etching depth, a certain depth of polysilicon and the corresponding depth of trench sidewall oxide layer within the first gate trench are removed, retaining the remaining polysilicon. An oxide layer is grown on the exposed polysilicon surface and trench sidewalls through thermal oxidation; this is the gate oxide layer of the first gate, which also serves to isolate the remaining polysilicon within the trench. Then, the surface oxide layer is removed. A layer of polysilicon is deposited on the surface to fill the interior of the first gate trench, and then the polysilicon on the surface of the P-type base region is removed by wet etching. The second gate can be formed using the same method described above.

[0121] Step 304: A carrier blocking layer and an N-type emitter region are formed on the surface of the P-type base region; an oxide layer is deposited on the surface of the P-type base region to form a dielectric layer; wherein the doping concentration of the carrier blocking layer and the N-type emitter region is higher than the doping concentration of the P-type base region, and the carrier blocking layer is located inside the P-type base region between the first gate and the second gate, and inside the P-type base region between the two second gates.

[0122] In this embodiment of the invention, the specific process of forming a carrier blocking layer and an N-type emitter region on the surface of the P-type base region is as follows: an oxide layer is deposited on the surface of the P-type base region, and a photoresist layer is spin-coated on the surface of the oxide layer. A carrier blocking layer injection window is formed through photolithography and etching processes. The carrier blocking layer is formed by N-type ion implantation. The photoresist is removed, and then the N-type emitter region is formed by implantation in the same way.

[0123] The carrier blocking layer located inside the P-type base region between the two second gates can adjust the injection window and control the hole extraction rate according to the actual application requirements of dI / dt and dV / dt when the IGBT is turned on, thereby enhancing the conductivity modulation effect and coordinating with the gate resistor to regulate dI / dt and dV / dt. This can suppress EMI noise while reducing the on-state voltage drop and turn-on loss.

[0124] Step 305: A P-type contact hole doped region and an emitter are formed on the surface of the dielectric layer; wherein the doping concentration of the P-type contact hole doped region is higher than the doping concentration of the P-type base region.

[0125] In this embodiment of the invention, the specific process of forming a P-type contact hole doped region and an emitter on the surface of the dielectric layer is as follows: a layer of photoresist is spin-coated on the surface of the dielectric layer, and an emitter metal contact hole etching window is formed by photolithography and etching processes; the dielectric layer is etched, and then a P-type contact hole doped region is formed by P-type ion implantation; the photoresist is removed, and emitter metal is sputtered on the surface of the dielectric layer to form an emitter that is in contact with the surface of the P-type base region.

[0126] Step 306: A field stop layer, a P-type collector region, and a collector are formed on the lower surface of the substrate; wherein the doping concentration of the field stop layer is higher than that of the substrate, and the doping concentration of the P-type collector region is higher than that of the field stop layer.

[0127] In this embodiment of the invention, the specific process of forming the field cutoff layer, the P-type collector region, and the collector is as follows: the lower surface of the substrate layer is thinned and high-energy N-type ion implantation is performed to form the field cutoff layer; then P-type ion implantation is performed to form the P-type collector region; then the lower surface of the substrate layer is laser annealed to activate the implanted ions; finally, collector metal is sputtered on the lower surface of the substrate layer to form the collector.

[0128] Thus, the fabrication of the IGBT in this embodiment of the invention is complete. The resulting IGBT can reduce device on-state voltage drop and switching losses while suppressing EMI noise, thereby better balancing the relationship between IGBT on-state voltage drop, switching losses, and EMI noise, and optimizing the performance of IGBT in high-frequency applications.

[0129] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0130] This invention also provides a chip, including the insulated gate bipolar transistor device described above.

[0131] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0132] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products embodied on one or more machine-readable media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0133] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0134] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0135] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0136] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0137] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0138] The above provides a detailed description of an insulated gate bipolar transistor device and its fabrication method provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An insulated-gate bipolar transistor device, characterized in that, include: Substrate layer; A carrier storage layer is disposed above the substrate layer; A superjunction P-pillar is disposed within a first trench; the first trench is disposed within the carrier storage layer and the substrate layer; A P-type base region is disposed above the superjunction P-pillar and the carrier storage layer; A first gate is disposed within a second trench; the second trench is disposed within a first region of the P-type base region and the carrier storage layer. The second gate is disposed within the third trench; the third trench is disposed within the second region of the P-type base region and the superjunction P-pillar. A carrier blocking layer is disposed within the P-type base region and located on both sides of the second gate; The N-type emitter region is located within the P-type base region and on the side of the first gate away from the second gate; A dielectric layer is disposed above the P-type base region in the region corresponding to the first gate and the second gate; The P-type contact hole doped region is located above the P-type base region and in the region other than the carrier blocking layer and the N-type emitter region; An emitter is disposed above the dielectric layer and the doped region of the P-type contact hole; A field cutoff layer is disposed below the substrate layer; The P-type collector region is located below the field cutoff layer; The collector is located below the P-type collector region.

2. The insulated-gate bipolar transistor device according to claim 1, characterized in that, The number of the first gate and the second gate is 2; the two second gates are arranged between the two first gates.

3. The insulated-gate bipolar transistor device according to claim 2, characterized in that, The carrier blocking layer is disposed within the P-type base region and located between the first gate and the second gate, and between the two second gates; The carrier blocking layer between the first gate and the second gate is configured to be a full blocking layer, and the carrier blocking layer between the two second gates is configured to be a partial blocking layer.

4. The insulated-gate bipolar transistor device according to claim 1, characterized in that, The first gate comprises upper and lower parts, with an oxide layer disposed between the upper half and the lower half of the first gate.

5. The insulated-gate bipolar transistor device according to claim 4, characterized in that, The upper half of the first gate is connected to the gate electrode, and the second gate is connected to the emitter.

6. The insulated-gate bipolar transistor device according to claim 2, characterized in that, The P-type base region is connected to the emitter.

7. The insulated-gate bipolar transistor device according to claim 1, characterized in that, The doping concentrations of the carrier storage layer, the superjunction P-pillar, and the field stop layer are higher than the doping concentration of the substrate layer. The doping concentration of the P-type collector region is higher than the doping concentration of the field stop layer; The doping concentration of the P-type base region is higher than that of the superjunction P-pillar; The doping concentrations of the N-type emitter region, the carrier blocking layer, and the P-type contact hole doped region are higher than the doping concentration of the P-type base region.

8. A method for fabricating an insulated-gate bipolar transistor device, characterized in that, The method includes: Provide a substrate layer; A carrier storage layer is formed above the substrate layer; The carrier storage layer and the substrate layer are etched to form a first trench, and P-type silicon material is filled in the first trench to form a superjunction P-pillar; A P-type base region is formed above the superjunction P-pillar and the carrier storage layer; A second trench is formed in the first region of the P-type base region and the carrier storage layer, and a first gate is filled in the second trench; A third trench is formed in the second region of the P-type base region and the superjunction P-pillar, and a second gate is filled in the third trench; N-type ions are implanted into the P-type base region to form a carrier blocking layer; the carrier blocking layer is located on both sides of the second gate. N-type ions are implanted into the P-type base region to form an N-type emitter region; the N-type emitter region is located on the side of the first gate away from the second gate; A dielectric layer is formed in the region above the P-type base region corresponding to the first gate and the second gate; Above the P-type base region, P-type ions are implanted into the region other than the carrier blocking layer and the N-type emitter region to form a P-type contact hole doped region. An emitter is formed above the dielectric layer and the doped region of the P-type contact hole; N-type ions are implanted beneath the substrate to form a field cutoff layer; P-type ions are injected below the field cutoff layer to form a P-type collector region; A collector electrode is formed below the P-type collector electrode region.

9. The method for fabricating an insulated-gate bipolar transistor device according to claim 8, characterized in that, The process of implanting N-type ions into the P-type base region to form a carrier blocking layer includes: N-type ions are implanted in the P-type base region and located between the first gate and the second gate and between the two second gates to form the carrier blocking layer; the carrier blocking layer between the first gate and the second gate is a full blocking layer, and the carrier blocking layer between the two second gates is a partial blocking layer.

10. The method for fabricating an insulated-gate bipolar transistor device according to claim 8, characterized in that, The method further includes: An oxide layer is provided in the first gate to divide the first gate into an upper half and a lower half.

11. The method for fabricating an insulated-gate bipolar transistor device according to claim 10, characterized in that, The method further includes: The upper half of the first gate is connected to the gate electrode, and the second gate is connected to the emitter.

12. A chip, characterized in that, Including the insulated gate bipolar transistor device as described in any one of claims 1-7 above.

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