Three-dimensional semiconductor device and manufacturing method thereof, electronic device

Abstract

The application discloses a three-dimensional semiconductor device and a manufacturing method thereof and an electronic device, and relates to the technical field of semiconductors, aiming to improve the integration and working performance of the three-dimensional semiconductor device. The three-dimensional semiconductor device comprises a semiconductor substrate, a first transistor, a second transistor, a gate side wall and a first isolation structure. The first transistor and the second transistor are arranged at intervals along the thickness direction of the semiconductor substrate. At least one of the first transistor and the second transistor is a ring gate transistor. The ring gate transistor comprises an inner side wall between a gate stack structure and a source-drain region. The gate side wall is arranged on at least two sides of the gate stack structure included in the first transistor and the gate stack structure included in the second transistor along the length direction. The first isolation structure is arranged between the gate stack structure included in the first transistor and the gate stack structure included in the second transistor. At least part of the material included in at least one of the inner side wall and the first isolation structure is the same as at least part of the material included in the gate side wall.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a three-dimensional semiconductor device and its manufacturing method, as well as an electronic device. Background Technology

[0002] Semiconductor devices are electronic components made from semiconductor materials and are an important part of modern electronic technology. Semiconductor devices have advantages such as small size, low power consumption, and high speed, and are widely used in computers, communications, consumer electronics, medical equipment, and building intelligence.

[0003] However, the low integration of existing semiconductor devices hinders their miniaturization. Summary of the Invention

[0004] The purpose of this invention is to provide a three-dimensional semiconductor device and its manufacturing method and electronic device, which can improve the integration of the three-dimensional semiconductor device and facilitate the miniaturization of the three-dimensional semiconductor device; at the same time, it can improve the working performance of the three-dimensional semiconductor device.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a three-dimensional semiconductor device, comprising: a semiconductor substrate, a first transistor, a second transistor, a gate sidewall, and a first isolation structure. The first transistor and the second transistor are disposed at a distance from each other on the semiconductor substrate along its thickness direction, with the second transistor positioned above the first transistor. At least one of the first transistor and the second transistor is a gate-around transistor. The gate-around transistor includes an inner sidewall located between a gate stack structure and source / drain regions. The gate sidewall is disposed on at least two sides along the length direction of the gate stack structure included in the first transistor and the gate stack structure included in the second transistor. The first isolation structure is disposed between the gate stack structure included in the first transistor and the gate stack structure included in the second transistor. Wherein, at least a portion of the material included in at least one of the inner sidewalls and the first isolation structure is the same as at least a portion of the material included in the gate sidewall.

[0006] With the above technical solution, in the three-dimensional semiconductor device provided by the present invention, the first transistor and the second transistor are spaced apart along the thickness direction of the semiconductor substrate. In this case, the first transistor and the second transistor can constitute a three-dimensional stacked transistor (CFET device), which helps to reduce the lateral dimension of the three-dimensional semiconductor device. Furthermore, the first isolation structure can isolate the gate stack structure included in the first transistor and the gate stack structure included in the second transistor, reducing electrical interference between them. Secondly, the gate sidewalls, at least on both sides of the gate stack structure along its length, can isolate the gate stack structure from part of the source / drain region and conductive structures such as the source / drain contact structure, preventing device failure and improving the operational reliability of the three-dimensional semiconductor device. As for the inner sidewalls, they can isolate the gate stack structure included in the ring-gate transistor from the source / drain region, preventing the etchant from affecting the source / drain region during the removal of the first semiconductor layer (i.e., the sacrificial layer); they also facilitate control of the gate length, improving the yield of the ring-gate transistor.

[0007] Furthermore, at least a portion of the material comprising at least one of the inner sidewalls and the first isolation structure is the same as at least a portion of the material comprising the gate sidewall. In this case, at least one of the inner sidewalls and the first isolation structure can be manufactured using the same insulating material with a low dielectric constant as the gate sidewall. This helps to reduce the parasitic capacitance between the gate stack structure and the source / drain regions. It can solve the problem in the prior art where at least one of the inner sidewalls and the first isolation structure is formed in different manufacturing processes than the gate sidewall, requiring a certain selection ratio when choosing manufacturing materials, resulting in a higher dielectric constant for at least one of them. This is beneficial for improving the working performance of three-dimensional semiconductor devices.

[0008] In one example, at least one of the inner sidewalls and the first isolation structure is made of the same material as the gate sidewalls.

[0009] In one example, the first isolation structure and the inner wall comprise at least a portion of the same material, and the portions of the first isolation structure and the adjacent inner wall made of the same material are integrally continuous.

[0010] In one example, the first isolation structure and the inner wall adjacent to it form a three-dimensional H-shaped structure.

[0011] In one example, the inner wall, the gate sidewall, and the first isolation structure are made of the same material.

[0012] In one example, the inner sidewall, the gate sidewall, and the first isolation structure are all multilayer structures. The interlayer interfaces extending along the thickness direction of the semiconductor substrate in each of the inner sidewall, the gate sidewall, and the first isolation structure are substantially aligned.

[0013] In one example, both the inner sidewall and the gate sidewall include at least one U-shaped dielectric layer and an intermediate filler dielectric layer filled in the U-shaped dielectric layer, with the openings of the U-shaped dielectric layers in the inner sidewall and the gate sidewall facing the source and drain regions; and / or, the first isolation structure includes at least one pair of U-shaped dielectric layers disposed opposite to each other along the thickness direction of the semiconductor substrate.

[0014] In one example, the top surface of the gate sidewall is planar.

[0015] In one example, the top surface of the gate sidewall is parallel to the surface extension direction of the semiconductor substrate.

[0016] In one example, the gate sidewalls are substantially parallel to the two outer surfaces of the gate stack structure and extend in a direction perpendicular to the surface of the semiconductor substrate.

[0017] In one example, the three-dimensional semiconductor device further includes a second isolation structure. The second isolation structure is located at least between the source / drain regions included in the first transistor and the source / drain regions included in the second transistor.

[0018] Secondly, the present invention provides a method for manufacturing a three-dimensional semiconductor device, the method further comprising: first, forming a fin-like structure on a semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin-like structure includes a lower fin, a semiconductor isolation portion, and an upper fin. In the fin-like structure, at least the lower fin and / or the upper fin includes alternately stacked first and second semiconductor layers. The film layer located at the bottom layer of the alternately stacked first and second semiconductor layers is the first semiconductor layer. Next, forming a first mask structure spanning the fin-like structure and a second mask structure located on the first mask structure. Next, laterally narrowing the first mask structure along the length direction of the fin-like structure; and forming third mask structures on both sides of the remaining first mask structure. Next, removing the portion of the fin-like structure exposed outside the second and third mask structures. Next, removing at least a portion of the semiconductor isolation portion to form a first filling space; and forming a fourth mask structure within the first filling space. Next, removing the fourth mask structure; and removing the two edge portions of the first semiconductor layer along the length direction and / or the third mask structure. Next, while forming inner sidewalls on both sides of the remaining first semiconductor layer and / or forming a first isolation structure in the area obtained by removing at least part of the semiconductor isolation portion, gate sidewalls are formed on both sides of the remaining first mask structure.

[0019] In one example, the thickness of the second mask structure is less than the height of the fin structure along the thickness direction of the semiconductor substrate.

[0020] In one example, the materials of the third and / or fourth mask structures include organic polymers and / or silicon dioxide.

[0021] In one example, the third mask structure is removed after the portion of the fin structure exposed outside the second and third mask structures is removed, and before the fourth mask structure is formed. Furthermore, the fourth mask structure fills both sides of the remaining first mask structure.

[0022] In one example, after forming the inner sidewall, gate sidewall, and first isolation structure, the method for manufacturing a three-dimensional semiconductor device further includes: epitaxially forming source / drain regions of a first transistor on both sides of the remaining lower fin; next, forming a second isolation structure on the source / drain regions of the first transistor; next, epitaxially forming source / drain regions of a second transistor on both sides of the remaining upper fin; next, removing the first mask structure and the remaining first semiconductor layer to obtain the channel regions of the first and second transistors; and next, forming a gate stack structure on the outer periphery of the channel regions.

[0023] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0024] Thirdly, the present invention provides an electronic device comprising: the three-dimensional semiconductor device provided in the first aspect and various implementations thereof. The electronic device includes a smartphone, personal computer, tablet computer, artificial intelligence device, wearable device, or power bank.

[0025] The beneficial effects of the third aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0027] Figure 1 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 1 ;

[0028] Figure 2 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 2 ;

[0029] Figure 3 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 3 ;

[0030] Figure 4 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 4 ;

[0031] Figure 5 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 5 ;

[0032] Figure 6 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 6 ;

[0033] Figure 7 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 7 ;

[0034] Figure 8 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 8 ;

[0035] Figure 9 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 9 ;

[0036] Figure 10 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 ;

[0037] Figure 11 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 one;

[0038] Figure 12 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 two;

[0039] Figure 13 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 three;

[0040] Figure 14 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 Four;

[0041] Figure 15 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 five;

[0042] Figure 16A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 six;

[0043] Figure 17 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 seven;

[0044] Figure 18 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 eight;

[0045] Figure 19 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 Nine;

[0046] Figure 20 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 2 ten;

[0047] Figure 21 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 2 eleven;

[0048] Figure 22 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 2 twelve;

[0049] Figure 23 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 2 Thirteen;

[0050] Figure 24 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 2 fourteen;

[0051] Figure 25 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 2 fifteen;

[0052] Figure 26 A schematic diagram of the structure of a three-dimensional semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 2 fifteen.

[0053] Reference numerals: 11 is a semiconductor substrate, 12 is a first transistor, 13 is a second transistor, 14 is a gate stack structure, 15 is a source / drain region, 16 is an inner sidewall, 17 is a channel region, 18 is a gate sidewall, 19 is a first isolation structure, 20 is a second isolation structure, 21 is a shallow trench isolation structure, 22 is an insulating dielectric layer, 23 is a fin structure, 24 is a lower fin, 25 is a semiconductor isolation portion, 26 is an upper fin, 27 is a first semiconductor layer, 28 is a second semiconductor layer, 29 is a first mask structure, 30 is a second mask structure, 31 is a third mask structure, 32 is a first filling space, and 33 is a fourth mask structure. Detailed Implementation

[0054] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0055] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0056] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0058] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0059] Semiconductor devices are electronic components made from semiconductor materials and are an important part of modern electronic technology. Semiconductor devices have advantages such as small size, low power consumption, and high speed, and are widely used in computers, communications, consumer electronics, medical equipment, and building intelligence.

[0060] However, the low integration of existing semiconductor devices hinders their miniaturization.

[0061] To address the aforementioned technical problems, embodiments of the present invention provide a three-dimensional semiconductor device and its manufacturing method, as well as an electronic device. In the three-dimensional semiconductor device provided by these embodiments, the first transistor and the second transistor are spaced apart along the thickness direction of the semiconductor substrate, thereby improving the integration density of the three-dimensional semiconductor device. Furthermore, at least a portion of the material included in the inner sidewall is the same as at least a portion of the material included in at least one of the gate sidewall and the first isolation structure, which helps to reduce the parasitic capacitance between the gate stack structure and the source / drain regions, thereby improving the operating performance of the three-dimensional semiconductor device.

[0062] In a first aspect, embodiments of the present invention provide a three-dimensional semiconductor device. For example... Figure 25 As shown, the three-dimensional semiconductor device includes: a semiconductor substrate 11, a first transistor 12, a second transistor 13, a gate sidewall 18, and a first isolation structure 19. The first transistor 12 and the second transistor 13 are disposed on the semiconductor substrate 11 at a distance along its thickness direction, with the second transistor 13 positioned above the first transistor 12. At least one of the first transistor 12 and the second transistor 13 is a gate-around transistor. The gate-around transistor includes an inner sidewall 16 located between a gate stack structure 14 and a source-drain region 15. The gate sidewall 18 is disposed on at least two sides along the length direction of the gate stack structure 14 included in the first transistor 12 and the gate stack structure 14 included in the second transistor 13. The first isolation structure 19 is disposed between the gate stack structure 14 included in the first transistor 12 and the gate stack structure 14 included in the second transistor 13. At least a portion of the material included in at least one of the inner sidewall 16 and the first isolation structure 19 is the same as at least a portion of the material included in the gate sidewall 18.

[0063] When the above technical solution is adopted, such as Figure 25 As shown, in the three-dimensional semiconductor device provided in this embodiment of the invention, the first transistor 12 and the second transistor 13 are spaced apart along the thickness direction of the semiconductor substrate 11. In this case, the first transistor 12 and the second transistor 13 can constitute a three-dimensional stacked transistor (CFET device), which helps to reduce the lateral dimension of the three-dimensional semiconductor device. Furthermore, the first isolation structure 19 can isolate the gate stack structure 14 included in the first transistor 12 and the gate stack structure 14 included in the second transistor 13, reducing electrical interference between them. Secondly, the gate sidewalls 18, at least on both sides of the gate stack structure 14 along its length, can isolate the gate stack structure 14 from a portion of the source / drain region 15 and conductive structures such as the source / drain contact structure, preventing device failure and improving the operational reliability of the three-dimensional semiconductor device. As for the inner sidewall 16, the inner sidewall 16 can isolate the gate stack structure 14 included in the ring-gate transistor from the source / drain region 15, preventing the etchant from affecting the source / drain region 15 during the removal of the first semiconductor layer 27 (i.e., the sacrificial layer); it also helps to control the gate length and improve the yield of the ring-gate transistor. Additionally, as... Figure 25 As shown, at least one of the inner sidewall 16 and the first isolation structure 19 comprises at least a portion of the same material as at least a portion of the material comprised of the gate sidewall 18. In this case, at least one of the inner sidewall 16 and the first isolation structure 19 can be manufactured using the same insulating material with a low dielectric constant as the gate sidewall 18. This helps to reduce the parasitic capacitance between the gate stack structure 14 and the source / drain region 15. It can solve the problem in the prior art where at least one of the inner sidewall 16 and the first isolation structure 19 is formed in different manufacturing processes than the gate sidewall 18, requiring a certain selection ratio when choosing manufacturing materials, resulting in a higher dielectric constant for at least one of them. This is beneficial to improving the working performance of the three-dimensional semiconductor device.

[0064] In the actual manufacturing process, the embodiments of the present invention do not specifically limit the structure and material of the semiconductor substrate, as long as it can be applied to the three-dimensional semiconductor device provided by the embodiments of the present invention. For example, the semiconductor substrate can be any semiconductor material such as silicon, silicon germanium, or germanium.

[0065] For the first transistor and the second transistor, which are spaced apart along the thickness direction of the semiconductor substrate, the conductivity types of the first transistor and the second transistor can be the same or opposite. The specific conductivity types of the first transistor and the second transistor can be set according to actual needs.

[0066] Furthermore, at least one of the first transistor and the second transistor is a gate-around transistor. Specifically, only the lower first transistor may be a gate-around transistor, while the second transistor may be a fin field-effect transistor or other non-gate-around transistor. Alternatively, only the upper first transistor may be a gate-around transistor, while the second transistor may be a fin field-effect transistor or other non-gate-around transistor. Or, as... Figure 25 As shown, both the first transistor 12 and the second transistor 13 can be gate-around transistors, which helps to improve the gate control capability of the three-dimensional semiconductor device, suppress the short-channel effect, and improve the working performance of the three-dimensional semiconductor device.

[0067] The specific structures of the first and second transistors can be determined based on their device types. Specifically, for example... Figure 25 As shown, in the first transistor 12 and the second transistor 13, at least one of the devices being a gate-to-ring transistor may include a channel region 17, a source-drain region 15, a gate stack structure 14, and an inner sidewall 16. The source-drain region 15 is disposed on both sides of the channel region 17 along its length. The channel region 17 includes at least one layer of nanostructure suspended between the source-drain region 15. The gate stack structure 14 surrounds the outer periphery of each nanostructure layer. This embodiment of the invention does not specifically limit the number of nanostructure layers included in the channel region 17. The inner sidewall 16 is located between the gate stack structure 14 and the drain region.

[0068] In addition, when one of the first transistors and the second transistor is a non-ring gate transistor, the device type can be determined based on the device type of that transistor.

[0069] For example, when the first or second transistor is a finned field-effect transistor, the first or second transistor includes a source / drain region, a channel region, and a gate stack structure. The source / drain regions are located on both sides of the channel region along its length, and the gate stack structure covers the top and both sides of the channel region.

[0070] It should be noted that a semiconductor structure is defined as a first transistor and a second transistor spaced apart along the thickness direction of the semiconductor substrate. Within the same semiconductor structure, the source region of the second transistor may be located on the same side as the source region of the first transistor along the length direction of the gate stack structure; alternatively, the drain region of the second transistor may be located on the same side as the source region of the first transistor along the length direction of the gate stack structure. Along the length direction of the gate stack structure, in different semiconductor structures, the source regions of the second transistor and the source regions of the first transistor may all be located on the same side (or the drain regions of the second transistor and the source regions of the first transistor may all be located on the same side); alternatively, in different semiconductor structures, some of the source regions of the second transistor and the source regions of the first transistor may be located on the same side, while the remaining drain regions of the second transistor and the source regions of the first transistor may be located on the same side.

[0071] The vertical relationship between the source and drain regions of the second transistor and the source and drain regions of the first transistor can be set according to actual needs, and no specific limitation is made here.

[0072] In terms of materials, the source / drain regions and channel regions of the first and second transistors can be made of any semiconductor material such as silicon, silicon germanium, or germanium. The gate stack structure can include a gate dielectric layer and a gate located on the gate dielectric layer. The gate dielectric layer can be made of insulating materials such as HfO2, ZrO2, TiO2, or Al2O3. The gate can be made of conductive materials such as TiN, TaN, or TiSiN.

[0073] As for the inner wall, such as Figure 25 As shown, the inner wall 16 can be a single-layer structure made of a single insulating material. Alternatively, the inner wall can be a multi-layer structure made of multiple materials; in this case, the distribution of different materials in the inner wall can be determined according to actual needs. For example, the different material layers in the inner wall can be arranged sequentially along the length of the grid stack structure.

[0074] For the gate sidewall, such as Figure 25 As shown, the gate sidewalls 18 may be provided only on both sides of the gate stack structure 14 along the length direction. Alternatively, the gate sidewalls may surround the outer periphery of the sidewalls of the gate stack structure.

[0075] As for the material of the gate sidewall, such as Figure 25 As shown, the gate sidewall 18 can be a single-layer structure made of an insulating material. Alternatively, the gate sidewall can be a multi-layer structure made of multiple materials; in this case, the distribution of different materials in the gate sidewall can be determined according to actual needs. For example, different material layers in the gate sidewall can be arranged sequentially along the length of the gate stack structure 14.

[0076] In addition, in practical applications, such as Figure 25 As shown, at least a portion of the material of the inner sidewall 16 may be the same as at least a portion of the material of the gate sidewall 18 (optionally, the material of the inner sidewall 16 is the same as the material of the gate sidewall 18); in this case, as Figure 18 and Figure 19As shown, the portions of the inner sidewall 16 and the gate sidewall 18 made of the same material can be formed simultaneously in the same operation step. In this case, both can be manufactured using insulating materials with the same and low dielectric constant, which helps reduce the parasitic capacitance between the gate stack structure 14 and the source / drain region 15. Simultaneously, it eliminates the need to select different materials for forming the two different structures, reducing the difficulty of material selection. Specifically, along the length of the gate stack structure 14, when the thicknesses of the inner sidewall 16 and the gate sidewall 18 are the same, the materials of the gate sidewall 18 and the inner sidewall 16 can be the same. Alternatively, when the thicknesses of the inner sidewall 16 and the gate sidewall 18 are different, the thicker one can include a different type of material than the thinner one; of course, in this case, the materials of the inner sidewall 16 and the gate sidewall 18 with different thicknesses can also be the same.

[0077] Wherein, if the second transistor is a gate ring transistor, and the film layers located at the bottom layer and the top layer of the first semiconductor layer and the second semiconductor layer alternately stacked in the upper fin during the manufacture of the second transistor are both first semiconductor layers, the portions of the gate sidewall and the inner sidewall located at the top layer that are made of the same material are integrally continuous.

[0078] In terms of appearance, such as Figure 25 As shown, the top surface of the gate sidewall 18 can be a plane; and / or, the top surface of the gate sidewall 18 can be parallel to the surface extension direction of the semiconductor substrate 11. In this case, during the actual manufacturing process, as... Figures 7 to 25 As shown, under the protection of the second mask structure 30, a filling space for forming the gate sidewall 18 can be obtained by laterally narrowing the first mask structure 29 (such as a sacrificial gate). At this time, the material forming the gate sidewall 18 is affected by the second mask structure 30 above it when deposited into this filling space; its top surface is planar and / or parallel to the surface extension direction of the semiconductor substrate 11. Furthermore, when the gate sidewall 18 is formed in the above manner, because the second mask structure 30 provides protection above the gate sidewall 18, it is not necessary to set a thick second mask structure 30 during anisotropic etching. The material on the outer periphery of the fin structure 23 corresponding to the source / drain region 15, as well as the material deposited on the semiconductor substrate 11, can be completely removed. This ensures the yield of the three-dimensional semiconductor device manufacturing process, reduces the amount of material used in manufacturing the second mask structure 30, reduces the aspect ratio during three-dimensional semiconductor device manufacturing, lowers the process difficulty, and expands the process window.

[0079] For example, such as Figure 25As shown, the gate sidewall 18 is substantially parallel to the two outer surfaces of the gate stack structure 14 and can extend in a direction perpendicular to the surface of the semiconductor substrate 11. As described above, Figures 7 to 25 As shown, under the protection of the second mask structure 30, a filling space for forming the gate sidewall 18 is obtained by laterally narrowing the first mask structure 29. When the material forming the gate sidewall 18 within the filling space is etched, the outer surface of the gate sidewall 18 is influenced by the upper second mask structure 30, causing its extension direction to be parallel to the direction perpendicular to the surface of the semiconductor substrate 11. This arrangement allows each part of the gate sidewall 18 to have a larger thickness, providing higher protection for the sacrificial gate and improving the yield of the three-dimensional semiconductor device. Furthermore, the angle between the extension directions of the two outer surfaces of the gate sidewall 18 away from the gate stack structure 14 is less than 2°, and these can be considered essentially parallel.

[0080] For the first isolation structure, the first isolation structure is disposed between the gate stack structure included in the first transistor and the gate stack structure included in the second transistor. For example... Figure 25 As shown, the first isolation structure 19 can be a continuous, integral structure; in this case, it can be a single-layer structure with different parts of the first isolation structure 19 made of the same material, or it can be a stacked structure with different materials alternately stacked. Alternatively, the first isolation structure can also include a multilayer structure spaced apart along the thickness direction of the semiconductor substrate, and the materials of different layers in the first isolation structure can be the same.

[0081] In addition, in practical applications, such as Figure 25 As shown, at least a portion of the materials used in the first isolation structure 19 and the inner wall 16 can be the same. In this case, the portions of the first isolation structure 19 and the adjacent inner wall 16 made of the same material can be integrally continuous. In other words, as... Figures 7 to 19 As shown, the portions of the inner sidewall 16 and the first isolation structure 19 made of the same material can be formed simultaneously in the same operation step. In this case, both can be manufactured using insulating materials with the same and low dielectric constant, which helps reduce the parasitic capacitance between the gate stack structure 14 and the source / drain region 15. Simultaneously, it eliminates the need to select different materials for forming the two different structures, the inner sidewall 16 and the first isolation structure 19, reducing the difficulty of material selection. Specifically, along the length of the gate stack structure 14, when the thicknesses of the inner sidewall 16 and the first isolation structure 19 are the same, the materials of the first isolation structure 19 and the inner sidewall 16 can be the same. Alternatively, when the thicknesses of the inner sidewall 16 and the first isolation structure 19 are different, the thicker one of the inner sidewall 16 and the first isolation structure 19 can include a different type of material than the one with the smaller thickness; of course, in this case, the materials of the inner sidewall 16 and the gate sidewall 18, which have different thicknesses, can also be the same.

[0082] In some cases, such as Figure 25 As shown, the first isolation structure 19 and the adjacent inner wall 16 can form a three-dimensional H-shaped structure. This arrangement can improve the isolation effect between the gate stack structure 14 included in the first transistor 12 and the second transistor 13, as well as the isolation effect between the gate stack structure 14 and the source / drain region 15, which is beneficial to improving the working performance of the three-dimensional semiconductor device.

[0083] For example, when the first isolation structure is a single-layer or multi-layer structure in which different parts are made of the same material, the materials of the first isolation structure and the inner wall can be the same.

[0084] For example, when the first isolation structure is a stacked structure with different materials alternately layered, some materials in the first isolation structure and the material of the inner wall can be the same.

[0085] It should be noted that in practical applications, at least a portion of the material comprising the inner sidewall may be identical to at least a portion of the material comprising either the gate sidewall or the first isolation structure. Alternatively, as... Figure 25 As shown, the inner sidewall 16, gate sidewall 18 and first isolation structure 19 may also be made of the same material; in this case, the inner sidewall 16, gate sidewall 18 and first isolation structure 19 can be formed simultaneously in the same operation step. In this case, all three can be made of insulating materials with small dielectric constant and the same material, thereby reducing the parasitic capacitance between the gate stack structure 14 and the source drain region 15.

[0086] For example, such as Figure 25 As shown, at least a portion of the materials used in the first isolation structure 19 and the gate sidewall 18 may be the same. The application principle of the beneficial effects in this case can be referred to above, and will not be repeated here.

[0087] For example, such as Figure 26 As shown, the inner sidewall 16, gate sidewall 18, and first isolation structure 19 can all be multilayer structures. The inner sidewall 16, gate sidewall 18, and first isolation structure 19 can each have the same number of layers, or all three can have the same number of layers. Each of the multilayer structures in the inner sidewall 16, gate sidewall 18, and first isolation structure 19 has an interface between each adjacent pair of layers. Furthermore, the number of insulating layers in the multilayer structure, as well as the material and thickness of each layer, can be set according to actual needs and are not specifically limited here. For example, the multilayer structure can be a two-layer structure, with the materials of SiOCN and SiN respectively. Alternatively, the multilayer structure can also be a three-layer structure, with the materials of SiN, SiOCN, and SiN respectively. Additionally, as... Figure 26As shown, the interlayer interfaces extending along the thickness direction of the semiconductor substrate in the inner sidewall 16, gate sidewall 18, and first isolation structure 19 can be substantially aligned. Specifically, when the distance between the interlayer interfaces extending along the thickness direction of the semiconductor substrate in the inner sidewall 16, gate sidewall 18, and first isolation structure 19 is less than the etching precision (e.g., 1 nm), they can be considered substantially aligned. With this configuration, the inner sidewall 16, gate sidewall 18, and first isolation structure 19 can be formed simultaneously in the same operation step. In this case, all three can be manufactured using insulating materials with low dielectric constants and the same properties, which helps to reduce the parasitic capacitance between the gate stack structure 14 and the source / drain region 15.

[0088] In addition, such as Figure 26 As shown, the inner sidewall 16 and the gate sidewall 18 can be U-shaped structures with source / drain regions 15 facing both ends along the channel length direction. This U-shaped structure includes at least one U-shaped dielectric layer and an intermediate filling dielectric layer located within the U-shaped dielectric layer. The shape of the first isolation structure 19 can be as follows... Figure 26 As shown, the two ends have the aforementioned U-shaped structures, and the middle can be a multi-layer structure consisting of a U-shaped dielectric layer and an intermediate filling dielectric layer extending into it. In other embodiments of the present invention, the portion of the first isolation structure located between the two U-shaped structures may also be formed by filling only the intermediate filling dielectric layer, or by filling only the U-shaped dielectric layer.

[0089] In one example, such as Figure 25 As shown, the three-dimensional semiconductor device may further include a second isolation structure 20. The second isolation structure 20 is located at least between the source / drain regions 15 included in the first transistor 12 and the source / drain regions 15 included in the second transistor 13.

[0090] The second isolation structure may be located only between the source / drain regions of the first transistor and the source / drain regions of the second transistor. Alternatively, as... Figure 25 As shown, the second isolation structure 20 can also cover the source / drain regions 15 and the semiconductor substrate 11 included in the first transistor 12.

[0091] As for the material of the second isolation structure, it can be set according to actual needs, and no specific limitation is made here. For example, the material of the second isolation structure can include any insulating material such as silicon oxide or silicon nitride.

[0092] In some cases, such as Figure 12 As shown, the three-dimensional semiconductor device provided in this embodiment of the invention may further include a shallow trench isolation structure 21. The shallow trench isolation structure 21 is formed on the semiconductor substrate 11 to define the active region of the semiconductor substrate 11, reduce leakage risk, and further improve the yield and performance of the three-dimensional semiconductor device.

[0093] In some cases, such as Figure 25 As shown, the three-dimensional semiconductor device provided in this embodiment of the invention may further include an insulating dielectric layer 22 to reduce the leakage risk of the three-dimensional semiconductor device and improve the yield of the source-drain regions 15 included in the second transistor 13, thereby improving the operating performance of the three-dimensional semiconductor device. The insulating dielectric layer 22 covers the second transistor 13.

[0094] As for the materials of the shallow trench isolation structure and the insulating dielectric layer, they can include any insulating material such as silicon oxide, silicon oxynitride, or silicon oxynitride, without specific limitations here.

[0095] Secondly, embodiments of the present invention provide a method for manufacturing a three-dimensional semiconductor device. The following will describe, based on... Figures 1 to 25 The illustrated perspective view or cross-sectional view describes the manufacturing process. Specifically, the method for manufacturing this three-dimensional semiconductor device includes the following steps:

[0096] First, such as Figures 1 to 6 As shown, a fin structure 23 is formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the fin structure 23 includes a lower fin 24, a semiconductor isolation portion 25, and an upper fin 26. In the fin structure 23, at least the lower fin 24 and / or the upper fin 26 include alternating layers of a first semiconductor layer 27 and a second semiconductor layer 28. The film layer located at the bottom layer of the alternating layers of the first semiconductor layer 27 and the second semiconductor layer 28 is the first semiconductor layer 27.

[0097] In the actual manufacturing process, the lower fin of the fin structure is used to manufacture the first transistor. Therefore, the specific structure of the lower fin of the fin structure can be determined according to the device type and structure of the first transistor. The upper fin of the fin structure is used for the second transistor. Therefore, the specific structure of the upper fin of the fin structure can be determined according to the device type and structure of the second transistor.

[0098] Since at least one of the first transistor and the second transistor is a gate-around transistor, in the fin structure, at least the lower fin and / or the upper fin include alternately stacked first semiconductor layers and second semiconductor layers. Specifically, as shown... Figure 2As shown, if only the first transistor is a gate-to-ring transistor (GMT) in the first transistor and the second transistor, then in the fin structure, at least the lower fin includes alternating layers of a first semiconductor layer 27 and a second semiconductor layer 28. In the lower fin, the first semiconductor layer 27 is a sacrificial layer, and the second semiconductor layer 28 is used to fabricate the channel region included in the first transistor. Furthermore, in this case, the structure of the upper fin can be determined according to the type of the second transistor. For example, when the second transistor is a finned field-effect transistor, the upper fin can be a single-layer elongated semiconductor structure; or it can be an elongated semiconductor structure including multiple semiconductor layers. It should be noted that Figure 2 shows a stacked structure used to fabricate the fin structure.

[0099] Or, such as Figure 3 As shown, if only the second transistor is a gate-to-ring transistor, then in the fin structure, at least the upper fin includes alternately stacked first semiconductor layers 27 and second semiconductor layers 28. In the upper fin, the first semiconductor layer 27 is a sacrificial layer, and the second semiconductor layer 28 is used to fabricate the channel region included in the second transistor. Furthermore, in this case, the structure of the lower fin can be determined according to the type of the first transistor. For example, when the first transistor is a fin field-effect transistor, the lower fin can be a single-layer elongated semiconductor structure; or it can be an elongated semiconductor structure including multiple semiconductor layers. It should be noted that Figure 3 shows a stacked structure used to fabricate the fin structure.

[0100] Or, as Figure 1 , Figures 4 to 6 As shown, if both the first transistor and the second transistor are gate-to-ring transistors, then in the fin structure 23, at least the upper fin 26 and the lower fin 24 include alternatingly stacked first semiconductor layers 27 and second semiconductor layers 28. In the upper fin 26 and the lower fin 24, the first semiconductor layer 27 is a sacrificial layer, and the second semiconductor layer 28 is used to fabricate the channel regions included in the first transistor and the second transistor, respectively. Specifically, in the lower fin 24, the top layer of the alternatingly stacked first semiconductor layer 27 and second semiconductor layer 28 is the first semiconductor layer 27. In the upper fin 26, the top layer of the alternatingly stacked first semiconductor layer 27 and second semiconductor layer 28 can be either the first semiconductor layer 27 or the second semiconductor layer 28.

[0101] The materials of the first and second semiconductor layers can be set according to actual needs, and no specific limitation is made here. For example, the material of the second semiconductor layer may be silicon, and the material of the first semiconductor layer may be germanium silicon (the germanium content in germanium silicon can be any value between 10% and 60%).

[0102] Regarding the semiconductor isolation portion included in the fin structure, this semiconductor isolation portion serves as a pre-positioning element. Subsequently, by removing the semiconductor isolation portion not covered by the first mask structure, a first isolation structure is formed between the upper and lower fins before forming the source / drain regions included in the first transistor. Furthermore, after forming the source / drain regions included in the first transistor, a second isolation structure is formed on the source / drain regions included in the first transistor and the semiconductor substrate. Therefore, the thickness of the semiconductor isolation portion can be determined based on the thickness requirements of the first and second isolation structures. As for the material of the semiconductor isolation portion, it can include any semiconductor material different from that of the lower and upper fins; no specific limitation is made here.

[0103] For example: Figure 2 As shown, the semiconductor isolation portion 25 may consist of only a single third semiconductor layer. The material of this third semiconductor layer differs from the materials of the first semiconductor layer 27 and the second semiconductor layer 28. For example, if the second semiconductor layer 28 is made of silicon and the first semiconductor layer 27 is made of germanium-silicon (the germanium content in the germanium-silicon can be any value from 10% to 60%), the material of the third semiconductor layer may include germanium-silicon (the germanium content in the germanium-silicon can be any value from 30% to 90%). Furthermore, the germanium content in the third semiconductor layer is higher than the germanium content in the first semiconductor layer 27.

[0104] For example: Figure 4 As shown, the semiconductor isolation portion 25 also includes alternating layers of a first semiconductor layer 27 and a second semiconductor layer 28. In this case, the material of the first semiconductor layer 27 in the semiconductor isolation portion 25 can be the same as the material of the first semiconductor layer 27 in the upper fin portion 26 and / or the lower fin portion 24, or it can be different. The material of the second semiconductor layer 28 in the semiconductor isolation portion 25 can refer to the material of the third semiconductor layer described above, and will not be repeated here.

[0105] For example, such as Figures 1 to 4 As shown, epitaxial growth and other processes can be used to form a first semiconductor layer 27 and a second semiconductor layer 28 for manufacturing the lower fin 24 and the upper fin 26 along the thickness direction of the semiconductor substrate 11, and to form a semiconductor isolation layer for manufacturing the semiconductor isolation portion 25. Then, as... Figure 5 As shown, photolithography and etching processes are used to pattern the first semiconductor layer 27, the second semiconductor layer 28, the semiconductor isolation layer, and a portion of the semiconductor substrate 11 to form at least two spaced Fin structures. Next, as... Figure 6As shown, shallow trench isolation structures 21 for defining active regions can be formed between adjacent Fin structures using processes such as deposition and etching. The top height of the shallow trench isolation structure 21 is less than or equal to the bottom height of the first semiconductor layer 27 located at the bottom layer. The portion of the Fin structure exposed outside the shallow trench isolation structure 21 includes fin-like structures 23.

[0106] It should be noted that when the manufactured three-dimensional semiconductor device does not include the above-mentioned shallow trench isolation structure, only the first semiconductor layer, the second semiconductor layer and the semiconductor isolation layer can be patterned; and the fin structure can be directly obtained after the patterning process.

[0107] Next, as Figure 7 As shown, deposition and etching processes can be used to form a first mask structure 29 spanning the fin structure 23 and a second mask structure 30 located on the first mask structure 29. The specific structure and materials of the first mask structure 29 and the second mask structure 30 can be set according to actual needs, as long as they can provide mask protection in the future. The materials of the first mask structure 29 and the second mask structure 30 are different.

[0108] For example: Figure 7 As shown, the first mask structure 29 may include a sacrificial gate. The material of the sacrificial gate may include an easily removable material such as polysilicon. Alternatively, the first mask structure 29 may also include a gate oxide layer and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include a material such as silicon oxide.

[0109] For example, the second mask structure may include a hard mask.

[0110] For example, such as Figure 7 As shown, along the thickness direction of the semiconductor substrate 11, the thickness of the second mask structure 30 can be less than the height of the fin structure 23. In this case, while ensuring the manufacturing yield of the three-dimensional semiconductor device, not only can the amount of consumables used in manufacturing the second mask structure 30 be reduced, but the aspect ratio of the three-dimensional semiconductor device can also be reduced, thereby reducing the process difficulty and expanding the process window.

[0111] Of course, the thickness of the second mask structure can also be equal to or greater than the height of the fin structure.

[0112] Next, as Figure 8 and Figure 9 As shown, dry etching or wet etching processes can be used to narrow the first mask structure 29 laterally along the length of the fin structure 23.

[0113] The etchant and etching process used to narrow the first mask structure laterally can be set according to the material of the first mask structure and actual needs, and are not specifically limited here.

[0114] For example, at least one of dry etching, pure gas etching, and wet etching can be used, and the etching reagent can include, but is not limited to, gases or THMA solutions such as NH3, NF3, H2, N2, F2, CH4, CHF3, CH2F2, CF4, C4F8, SF6, and HBr.

[0115] Next, as Figure 10 and Figure 11 As shown, a third mask structure 31 can be formed on both sides of the remaining first mask structure 29 using processes such as deposition and etching. The material of the third mask structure 31 is different from the materials of the first mask structure 29 and the second mask structure 30.

[0116] The specific materials of the third mask structure, as well as the growth process and growth agent used to form the third mask structure, can be set according to actual needs, and no specific restrictions are made here.

[0117] For example, the material of the third mask structure includes organic polymers and / or silicon dioxide, etc.

[0118] For example, when the material of the third mask structure includes an organic polymer, the formation process of the third mask structure includes, but is not limited to, plasma-enhanced chemical vapor deposition, inductively coupled plasma deposition, and atomic layer deposition, and the growth agent of the third mask structure includes, but is not limited to, SF6, CF4, C4F6, C4F8, CH2F2, CHF3, CH4, HBr, etc.

[0119] Next, as Figure 12 and Figure 13 As shown, dry etching or wet etching processes can be used to remove the portion of the fin structure exposed outside the second mask structure 30 and the third mask structure 31.

[0120] Next, as Figures 14 to 16 As shown, at least a portion of the semiconductor isolation portion 25 is formed by etching and other processes to form a first filling space 32; and a fourth mask structure 33 is formed in the first filling space 32 by deposition and etching and other processes.

[0121] The extent of the first filling space can be determined based on whether the materials of the subsequently formed inner sidewall and the first isolation structure are the same as the materials of the gate sidewall.

[0122] When the inner sidewall, gate sidewall, and first isolation structure are made of the same material, since the third mask structure corresponds to the location of the gate sidewall and at least a portion of the semiconductor isolation portion corresponds to the location of the first isolation structure, it is necessary to remove the third mask structure and at least a portion of the semiconductor isolation portion to form a first filling space. In this case, if the material of the subsequently formed fourth mask structure is the same as the material of the third mask structure, it is not necessary to remove the third mask structure. Optionally, the portion of the fin structure exposed outside the second and third mask structures can be removed, and the third mask structure can be removed before forming the fourth mask structure. In this case, the fourth mask structure also fills both sides of the remaining first mask structure, thereby making at least a portion of the materials of the inner sidewall, gate sidewall, and first isolation structure the same.

[0123] When the inner sidewall is made of the same material as the gate sidewall, only the third mask structure needs to be removed. In this case, if the material of the subsequently formed fourth mask structure is the same as the material of the third mask structure, then the third mask structure does not need to be removed.

[0124] When the gate sidewall is made of the same material as the first isolation structure, only a portion of the semiconductor isolation portion needs to be removed. Furthermore, the third and fourth mask structures can be made of different materials so that the inner sidewall can be manufactured separately from the gate sidewall and the first isolation structure.

[0125] In addition, the etching process and etchant used when etching the third mask structure and / or semiconductor isolation portion can be set according to the materials of both and the actual requirements, and no specific limitation is made here.

[0126] For example, when the material of the third mask structure includes organic polymers, etching is not limited to gases such as CF4, C4F6, C4F8, CH2F2, CHF3, CH4, O2, Ar, and SF6.

[0127] For example, when the material of the third mask structure includes organic polymers, the removal is not limited to being completed by etching with gases such as CF4, C4F6, C4F8, CH2F2, CHF3, CH4, O2, Ar, SF6, or chemical solutions such as HF, BOE, H3PO4.

[0128] It should be noted that, when it is necessary to remove at least part of the semiconductor isolation portion, the extent to which the semiconductor isolation portion is etched can be determined based on the structure of the semiconductor isolation portion and the specific structure of the subsequently formed first isolation structure. Specifically, when the semiconductor isolation portion is a single-layer structure, the entire semiconductor isolation portion can be removed. When the semiconductor isolation portion is a multilayer structure, only the second semiconductor layer included in the semiconductor isolation portion can be removed.

[0129] As for the material of the fourth mask structure, it can be set according to actual needs, and no specific limitations are made here. The material of the fourth mask structure can be the same as or different from the material of the third mask structure. When the material of the fourth mask structure is the same as the material of the third mask structure, the growth process and growth agent for forming the fourth mask structure can be referred to the previous text, and will not be repeated here.

[0130] For example, the material of the fourth mask structure may include organic polymers and / or silicon dioxide, etc.

[0131] Next, as Figure 17 and Figure 18 As shown, an etching process is used to remove the fourth mask structure; and the two edge portions of the first semiconductor layer 27 along the length direction and / or the third mask structure are removed.

[0132] It should be noted that if the third mask structure has been removed before the step of forming the fourth mask structure, then the step of removing the third mask can be ignored here.

[0133] The etching process and etchant used for etching the first semiconductor layer and the third mask structure can be set according to the materials of both and the actual requirements, and are not specifically limited here. When the material of the fourth mask structure is the same as that of the third mask structure, the etching process and etchant used to remove the fourth mask structure can be referred to the previous text, and will not be repeated here.

[0134] Next, as Figure 19 As shown, by employing deposition and etching processes, inner sidewalls 16 are formed on both sides of the remaining first semiconductor layer 27 and / or a first isolation structure 19 is formed in the area obtained by removing at least part of the semiconductor isolation portion, while gate sidewalls 18 are formed on both sides of the remaining first mask structure 29.

[0135] It should be noted that when the materials of the inner sidewall, the gate sidewall, and the first isolation structure are the same, this step can simultaneously form the inner sidewall, the gate sidewall, and the first isolation structure.

[0136] When the inner sidewall is made of the same material as the gate sidewall, this step only forms the inner sidewall and the gate sidewall. As for the first isolation structure, it can be formed using an etching-deposition-etching process after the inner sidewall and the gate sidewall are formed.

[0137] When the gate sidewall is made of the same material as the first isolation structure, this step only forms the gate sidewall and the first isolation structure. As for the inner sidewall, it can be formed before or after forming the gate sidewall and the first isolation structure (e.g., after removing the two edge portions of the first semiconductor layer along the length direction and before forming the gate sidewall and the first isolation structure).

[0138] Next, as Figure 20 As shown, epitaxial processes can be used to epitaxially form the source and drain regions 15 of the first transistor 12 on both sides of the remaining lower fin.

[0139] Next, as Figure 21 As shown, a second isolation structure 20 can be formed on the source and drain regions 15 included in the first transistor 12 using processes such as deposition and etching.

[0140] Next, as Figure 22 As shown, epitaxial processes can be used to epitaxially form the source and drain regions 15 of the second transistor 13 on both sides of the remaining upper fin.

[0141] Next, as Figure 23 As shown, at least deposition and planarization processes can be used to form an insulating dielectric layer 22 covering the formed structure. The top of the insulating dielectric layer 22 is flush with the top of the first mask structure 29.

[0142] Next, as Figure 24 As shown, the first mask structure and the remaining first semiconductor layer 27 are removed by using dry etching or wet etching processes to obtain the channel region 17 included in the first transistor 12 and the channel region 17 included in the second transistor 13.

[0143] Next, as Figure 25 As shown, a gate stack structure 14 is formed on the outer periphery of the channel region 17 using processes such as atomic layer deposition.

[0144] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0145] Thirdly, embodiments of the present invention provide an electronic device comprising: the three-dimensional semiconductor device provided in the first aspect and its various implementations described above. The electronic device includes a smartphone, personal computer, tablet computer, artificial intelligence device, wearable device, or power bank.

[0146] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0147] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0148] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A method for manufacturing a three-dimensional semiconductor device, characterized in that, include: A fin-like structure is formed on a semiconductor substrate; Along the thickness direction of the semiconductor substrate, the fin structure includes a lower fin, a semiconductor isolation portion, and an upper fin; In the fin-like structure, at least the lower fin and / or the upper fin include alternatingly stacked first semiconductor layers and second semiconductor layers; the film layer located at the bottom layer of the alternatingly stacked first semiconductor layers and second semiconductor layers is the first semiconductor layer; A first mask structure is formed that spans the fin-like structure, and a second mask structure is located on the first mask structure; The first mask structure is laterally narrowed along the length of the fin-like structure; And a third mask structure is formed on both sides of the remaining first mask structure; Remove the portion of the fin structure exposed outside the second and third mask structures; At least a portion of the semiconductor isolation portion is removed to form a first filling space; A fourth mask structure is formed within the first filling space; The materials of the third mask structure and the fourth mask structure include organic polymers and / or silicon dioxide; Remove the fourth mask structure; And remove the two edge portions of the first semiconductor layer along its length and / or the third mask structure; While forming inner sidewalls on both sides of the remaining first semiconductor layer and / or forming a first isolation structure in the area obtained by removing at least a portion of the semiconductor isolation portion, gate sidewalls are formed on both sides of the remaining first mask structure. Specifically, after removing the portion of the fin structure exposed outside the second and third mask structures, and before forming the fourth mask structure, the third mask structure is removed; Furthermore, the fourth mask structure also fills both sides of the remaining first mask structure.

2. The method for manufacturing a three-dimensional semiconductor device according to claim 1, characterized in that, Along the thickness direction of the semiconductor substrate, the thickness of the second mask structure is less than the height of the fin structure.

3. The method for manufacturing a three-dimensional semiconductor device according to claim 1, characterized in that, After forming the inner sidewall, the gate sidewall, and the first isolation structure, the method for manufacturing the three-dimensional semiconductor device further includes: The source and drain regions of the first transistor are formed on both sides of the remaining lower fin. A second isolation structure is formed on the source and drain regions included in the first transistor; The source and drain regions of the second transistor are formed on both sides of the remaining upper fin. Remove the first mask structure and the remaining first semiconductor layer to obtain the channel region included in the first transistor and the channel region included in the second transistor; A grid stack structure is formed on the outer periphery of the channel region.

4. A three-dimensional semiconductor device, characterized in that, The three-dimensional semiconductor device is formed using the manufacturing method of the three-dimensional semiconductor device according to any one of claims 1 to 3; The three-dimensional semiconductor device includes: a semiconductor substrate; A first transistor and a second transistor are disposed at a distance from each other on the semiconductor substrate along the thickness direction, with the second transistor located above the first transistor; at least one of the first transistor and the second transistor is a gate-around transistor; the gate-around transistor includes an inner wall located between the gate stack structure and the source-drain region; Gate sidewalls are disposed on at least both sides along the length direction of the gate stack structure included in the first transistor and the gate stack structure included in the second transistor; A first isolation structure is disposed between the gate stack structure included in the first transistor and the gate stack structure included in the second transistor; Wherein, at least one of the inner sidewall and the first isolation structure comprises at least a portion of the same material as the gate sidewall.

5. The three-dimensional semiconductor device according to claim 4, characterized in that, The material of at least one of the inner sidewall and the first isolation structure is the same as the material of the gate sidewall.

6. The three-dimensional semiconductor device according to claim 4, characterized in that, The first isolation structure and the inner wall are made of at least a portion of the same material, and the portions of the first isolation structure and the adjacent inner wall made of the same material are integrally continuous.

7. The three-dimensional semiconductor device according to claim 4, characterized in that, The inner sidewall and the gate sidewall are an integrated structure, wherein the nanostructures included in the ring gate transistor are sandwiched between two adjacent inner sidewalls located on the same side of the three-dimensional semiconductor device and belonging to the same ring gate transistor.

8. The three-dimensional semiconductor device according to claim 7, characterized in that, Both the first transistor and the second transistor are ring-gate transistors; on the same side of the three-dimensional semiconductor device, the lowermost inner wall of the second transistor, the first isolation structure, and the uppermost inner wall of the first transistor form a whole.

9. The three-dimensional semiconductor device according to claim 4, characterized in that, The inner sidewall, the gate sidewall, and the first isolation structure are made of the same material.

10. The three-dimensional semiconductor device according to claim 4, characterized in that, The inner sidewall, the gate sidewall, and the first isolation structure are all multi-layer structures; Wherein, the interlayer interfaces extending along the thickness direction of the semiconductor substrate in the inner sidewall, the gate sidewall, and the first isolation structure are aligned.

11. The three-dimensional semiconductor device according to claim 4, characterized in that, Both the inner sidewall and the gate sidewall include at least one U-shaped dielectric layer and an intermediate filling dielectric layer filled in the U-shaped dielectric layer; the openings of the U-shaped dielectric layers included in the inner sidewall and the gate sidewall face the source and drain regions; And / or, the first isolation structure includes at least one pair of U-shaped dielectric layers disposed opposite each other along the thickness direction of the semiconductor substrate.

12. The three-dimensional semiconductor device according to claim 4, characterized in that, The top surface of the gate sidewall is a plane; And / or, the top surface of the gate sidewall is parallel to the surface extension direction of the semiconductor substrate; And / or, the gate sidewalls are parallel to the two outer surfaces of the gate stack structure and extend in a direction perpendicular to the surface of the semiconductor substrate.

13. The three-dimensional semiconductor device according to claim 4, characterized in that, The three-dimensional semiconductor device further includes a second isolation structure; the second isolation structure is located at least between the source / drain regions included in the first transistor and the source / drain regions included in the second transistor.

14. An electronic device, characterized in that, include: The three-dimensional semiconductor device as described in any one of claims 4 to 13; The electronic devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, or power banks.

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