Silicon carbide power device robustness test circuit and method

Abstract

The application relates to a silicon carbide power device robustness test circuit and method. The silicon carbide power device robustness test circuit comprises a controller module, a driving module and a power loop module. The controller module is used for generating a test control signal and sending the test control signal to the driving module. The driving module is used for generating a bipolar degradation pulse signal and an avalanche pulse signal according to the test control signal. The power loop module is used for generating a bipolar degradation current based on the bipolar degradation pulse signal, applying bipolar stress to a target device, and generating an avalanche voltage based on the avalanche pulse signal, applying avalanche stress to the target device. The power loop module is also used for collecting test data corresponding to the target device, and the test data is used for determining the avalanche robustness of the target device. The test current in the application can improve the accuracy of the test result.

Description

Technical Field

[0001] This application relates to the field of silicon carbide power device technology, and in particular to a robustness testing circuit and method for silicon carbide power devices. Background Technology

[0002] Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been widely adopted as power devices in high-performance power electronic systems for applications such as rail transportation and new energy vehicles, thanks to their superior high-power, high-frequency characteristics and thermal management capabilities. To ensure their stable operation under extreme conditions, such as short circuits, surges, and avalanche energy impacts, accurate reliability assessment is crucial.

[0003] Recent studies have confirmed that SiC MOSFETs undergo progressive damage such as bipolar degradation during operation. The increased leakage current caused by bipolar degradation directly weakens the device's static blocking capability. Avalanche tolerance, a core indicator of dynamic blocking characteristics, lacks a means to quickly and accurately characterize the impact of decreased static blocking capability due to body diode degradation on the device's dynamic blocking characteristics, and its correlation mechanism with the bipolar degradation process remains unclear. The insidious nature of this degradation poses a severe challenge to high-reliability systems, especially in applications where avalanche conditions and body diode conduction degradation are coupled.

[0004] Current traditional testing systems have two major limitations: First, existing schemes struggle to simulate the physical process of sudden avalanche after a device undergoes specific bipolar degradation, as the single stress loading mode severs the coupling effect between cumulative damage to the bulk diode and avalanche impact. Second, artificially triggered degradation control lacks precision and dynamic adaptability, failing to reproduce the temporal correlation between degradation stages and transient avalanches in actual systems. More seriously, long-term operating conditions leading to bulk diode degradation significantly exacerbate the risk of avalanche failure, and traditional methods are currently lacking in assessing the synergistic effects across stress modes, directly hindering accurate prediction of the reliability of power electronic systems throughout their entire lifecycle. Summary of the Invention

[0005] Therefore, it is necessary to provide a robustness test circuit and method for silicon carbide power devices that can accurately simulate the avalanche transient response after bipolar degradation and simultaneously complete stress loading and real-time voltage and current monitoring.

[0006] In a first aspect, a robustness test circuit for silicon carbide power devices is provided, comprising: a controller module, a drive module, and a power loop module, wherein the controller module is connected to the drive module, the drive module is connected to the power loop module and the target device respectively, and the power loop module is connected to the target device.

[0007] The controller module is used to generate test control signals and send them to the driver module.

[0008] The driver module is used to generate bipolar degradation pulse signals and avalanche pulse signals based on the test control signals;

[0009] The power loop module is used to generate a bipolar degradation current based on a bipolar degradation pulse signal to apply bipolar stress to the target device, and to generate an avalanche voltage based on an avalanche pulse signal to apply avalanche stress to the target device; the power loop module is also used to collect test data corresponding to the target device, and the test data is used to determine the avalanche robustness of the target device.

[0010] In one embodiment, the driving module includes a first switch driving module, a second switch driving module, and a device driving module. The first switch driving module is connected to a first output terminal of the controller module and the power loop module, respectively. The second switch driving module is connected to a second output terminal of the controller module and the power loop module, respectively. The device driving module is connected to a third output terminal of the controller module and the gate of the target device, respectively.

[0011] The first switch driving module is used to generate the bipolar degradation pulse signal according to the first test control signal output by the first output terminal of the controller module;

[0012] The second switch driver module is used to generate the avalanche pulse signal based on the second test control signal output from the second output terminal of the controller module;

[0013] The device driving module is used to generate a gate pulse signal based on the third test control signal output from the third output terminal of the controller module and output it to the gate of the target device, so that the target device is turned on or off.

[0014] In one embodiment, the first switch driving module includes:

[0015] The system comprises a driver chip U1, a first signal input unit, a first power input unit, a second power input unit, and a first signal output unit. The first signal input unit is connected to the first output terminal of the controller module and the driver chip U1, respectively. The first power input unit is connected to the first power supply and the driver chip U1, respectively. The second power input unit is connected to the second power supply and the driver chip U1, respectively. The first signal output unit is connected to the driver chip U1 and the power circuit module, respectively.

[0016] The first signal input unit is used to input the first test control signal to the driver chip U1;

[0017] The first power input unit is used to receive a first power signal, filter the first power signal, and use the filtered first power signal to drive the driver chip U1.

[0018] The second power input unit is used to receive the second power signal, filter the second power signal, and send the filtered second power signal to the driver chip U1;

[0019] The driver chip U1 is used to convert the first test control signal into a first pulse signal;

[0020] The first signal output unit is used to perform voltage division processing on the first pulse signal to obtain the bipolar degraded pulse signal.

[0021] In one embodiment, the first signal output unit includes: resistors R3, R4, and R5. The first end of resistor R3 is connected to the non-inverting output terminal of the driver chip U1, and the second end of resistor R3 is connected to the power circuit module. The first end of resistor R4 is connected to the inverting output terminal of the driver chip U1, and the second end of resistor R4 is connected to the power circuit module. The first end of resistor R5 is connected to resistors R3, R4, and the power circuit module, and the second end of resistor R5 is grounded.

[0022] In one embodiment, the device driving module includes: a driving chip U2, a second signal input unit, a third power input unit, a fourth power input unit, and a second signal output unit. The second signal input unit is connected to the third output terminal of the controller module and the driving chip U2, respectively. The third power input unit is connected to the third power supply and the driving chip U2, respectively. The fourth power input unit is connected to the fourth power supply and the driving chip U2, respectively. The second signal output unit is connected to the driving chip U2 and the gate of the target device, respectively.

[0023] The second signal input unit is used to input the third test control signal output from the third output terminal of the controller module to the driver chip U2;

[0024] The third power input unit is used to receive the third power signal, filter the third power signal, and use the filtered third power signal to drive the driver chip U2.

[0025] The fourth power input unit is used to receive the fourth power signal, filter the fourth power signal, and send the filtered fourth power signal to the driver chip U2.

[0026] The driver chip U2 is used to convert the third test control signal into a second pulse signal;

[0027] The second signal output unit is used to perform voltage division processing on the second pulse signal to obtain the gate pulse signal.

[0028] In one embodiment, the power loop module includes a test circuit and a data acquisition circuit. The test circuit is connected to the output terminals of the first switch driving module and the second switch driving module, respectively, and is also connected to the target device. The data acquisition circuit is connected to the test circuit and is also connected to the target device.

[0029] The test circuit is used to generate the avalanche voltage based on the avalanche pulse signal, and also to generate the bipolar degradation current based on the bipolar degradation pulse signal;

[0030] The acquisition circuit is used to acquire the test data.

[0031] In one embodiment, the test circuit includes a bipolar stress test circuit, which includes: a switching element IGBT1, the gate of which is connected to the output terminal of the first switch driving module, the collector of which is connected to the first terminal of the constant current source ISD, and the emitter of which is connected to the source of the target device; and the second terminal of the constant current source ISD is connected to the drain of the target device.

[0032] The switching element IGBT1 is used to turn on the constant current source ISD and the target device based on the bipolar degradation pulse signal, and generate the bipolar degradation current at the drain of the target device.

[0033] In one embodiment, the test circuit includes an avalanche stress test circuit, which includes: a switching element IGBT2, an inductor L1, a diode D1, and a capacitor C. DC1 ;

[0034] The gate of the IGBT2 switching element is connected to the output terminal of the second switch driving module. The emitter of the IGBT2 switching element is connected to the drain of the target device through the inductor L1, and to the source of the target device through the diode D1. The collector of the IGBT2 switching element is connected to the DC power supply DC1, and to the capacitor C. DC1 connect;

[0035] The switching element IGBT2 is used to turn on the DC power supply DC1 and the capacitor C based on the avalanche pulse signal. DC1 The avalanche voltage is generated at the drain of the target device in conjunction with the inductor L1.

[0036] In one embodiment, the test data includes transient characteristic parameters and static electrical parameters;

[0037] The acquisition circuit includes an oscilloscope G1, a differential probe, a coaxial resistor S1, and a semiconductor parameter analyzer; the first terminal of the oscilloscope G1 is connected to the target device in sequence through the differential probe and the coaxial resistor S1; the semiconductor parameter analyzer is connected to the target device.

[0038] An oscilloscope is used to monitor the transient characteristic parameters of a target device.

[0039] Semiconductor parameter analyzers are used to monitor the static electrical parameters of target devices.

[0040] Secondly, a robustness testing method for silicon carbide power devices is provided, applied to the robustness testing circuit for silicon carbide power devices in the first aspect, the method comprising the following steps:

[0041] Generate a test control signal and send the test control signal to the drive module;

[0042] Based on the test control signal, a bipolar degradation pulse signal and an avalanche pulse signal are generated;

[0043] A bipolar degradation current is generated based on the bipolar degradation pulse signal to apply bipolar stress to the target device, and an avalanche voltage is generated based on the avalanche pulse signal to apply avalanche stress to the target device.

[0044] Test data corresponding to the target device is collected, and the test data is used to determine the avalanche robustness of the target device.

[0045] Collect test data corresponding to the target device. The test data is used to determine the avalanche robustness of the target device.

[0046] The aforementioned robustness testing circuit and method for silicon carbide power devices utilizes a controller module to control the drive module and power loop module to work collaboratively according to a preset stress sequence. This enables precise simulation of the coupling effect of avalanche transient response after bipolar degradation. By observing and analyzing test data during the stress application process through the power loop module, the technical limitations of traditional testing methods, such as the disconnect between stress modes and the lack of temporal correlation, are overcome. This allows for a comprehensive, accurate, and time-controllable quantitative evaluation of the target device under the combined stress of bipolar degradation and avalanche, effectively improving the accuracy of silicon carbide power device test results. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of a module of a silicon carbide power device robustness test circuit in one embodiment;

[0049] Figure 2 The test control signal corresponding to the "single avalanche-bipolar degradation-single avalanche" test mode;

[0050] Figure 3 This refers to the test control signal corresponding to the "bipolar degradation-single avalanche-recovery" cyclic test mode.

[0051] Figure 4 This refers to the test control signal corresponding to the "bipolar degradation-repeated avalanche" test mode;

[0052] Figure 5 This is a circuit diagram of the first switch driving module in one embodiment;

[0053] Figure 6 This is a circuit diagram of the second switch driving module in one embodiment;

[0054] Figure 7 This is a circuit diagram of the device driving module in one embodiment;

[0055] Figure 8 This is a circuit diagram of a power loop module in one embodiment;

[0056] Figure 9 This is a flowchart of a robustness testing method for silicon carbide power devices in one embodiment;

[0057] Figure 10 This is a flowchart of a robustness testing method for silicon carbide power devices in another embodiment.

[0058] Explanation of reference numerals in the attached figures:

[0059] 100. Controller module; 200. Drive module; 210. First switch drive module; 220. Second switch drive module; 230. Device drive module; 300. Power loop module; 310. Avalanche stress test loop; 320. Bipolar stress test loop; 330. Acquisition circuit; 400. Target device. Detailed Implementation

[0060] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0062] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0063] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0064] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0065] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0066] like Figure 1As shown, the robustness test circuit for silicon carbide power devices in one embodiment of this application includes: a controller module 100, a drive module 200, and a power loop module 300. The controller module 100 is connected to the drive module 200, the drive module 200 is connected to the power loop module 300 and the target device 400, and the power loop module 300 is connected to the target device 400. The controller module 100 is used to generate a test control signal and send the test control signal to the drive module 200. The drive module 200 is used to generate a bipolar degradation pulse signal and an avalanche pulse signal according to the test control signal. The power loop module 300 is used to generate a bipolar degradation current based on the bipolar degradation pulse signal to apply bipolar stress to the target device 400, and to generate an avalanche voltage based on the avalanche pulse signal to apply avalanche stress to the target device 400. The power loop module 300 is also used to collect test data corresponding to the target device 400, and the test data is used to determine the avalanche robustness of the target device 400.

[0067] Among them, the target device 400 is the silicon carbide metal oxide semiconductor field-effect transistor under test.

[0068] The controller module 100 can be an FPGA (Field Programmable Gate Array) controller or an MCU (Micro Control Unit). The controller module 100 can dynamically adjust key parameters such as bipolar degradation DC test time, single avalanche test time, number of repeated avalanche tests, and various delay times by adjusting the test control signals.

[0069] The drive module 200 dynamically adjusts the output bipolar degradation pulse signal and avalanche pulse signal based on the test control signal generated by the controller module 100; the power loop module 300 applies bipolar stress to the target device 400 based on the bipolar degradation pulse signal to simulate the scenario of long-term conduction degradation of the body diode in the target device 400; and applies avalanche stress to the target device 400 based on the avalanche pulse signal to control the application sequence and duration of microsecond-level avalanche impact, thereby realizing the real coupling of degradation accumulation effect and sudden dynamic stress in the physical process.

[0070] For example, the controller module 100 is further configured to receive control commands, determine a target test mode based on the control commands, and generate test control signals corresponding to the target test mode. The control commands can be pre-stored in the form of a Verilog HDL program or sent to the controller module 100. The target test mode is at least one of "single avalanche-bipolar degradation-single avalanche", "bipolar degradation-single avalanche-recovery" loop, or "bipolar degradation-repeated avalanche".

[0071] Specifically, in the "single avalanche-bipolar degradation-single avalanche" test mode, the test control signal can be as follows: Figure 2 As shown, the bipolar degradation duration, avalanche duration, and various delay times can be freely set; in the "bipolar degradation-single avalanche-recovery" cyclic test mode, the test control signal can be set as follows: Figure 3 As shown, the bipolar degradation duration, avalanche duration, and various delay times can be freely set. Furthermore, the number of cycles can be freely set. In the "bipolar degradation-repeated avalanche" test mode, the test control signal can be as follows: Figure 4 As shown, the bipolar degradation duration, avalanche duration, and various delay times can be freely set. Here, Delayi represents various delay times, Voltage represents voltage amplitude, and DUT represents the target device 400.

[0072] Meanwhile, the number of repeated avalanche cycles can be freely set, enabling the temporal correlation reproduction of long-term degradation effects and transient avalanche impacts, thus overcoming the shortcomings of insufficient accuracy in previous manually triggered degradation testing. Through configurable test modes, the full-scenario reliability verification of the target device 400, from progressive degradation to final transient failure, can be completed on a single test platform. This accelerates the reliability verification process, effectively shortening the R&D cycle and reducing testing costs, thereby mitigating system risk throughout its entire lifecycle from the design stage.

[0073] In this embodiment, the controller module 100 controls the drive module 200 and the power loop module 300 to work collaboratively according to a preset stress sequence, which can accurately simulate the coupling effect of the avalanche transient response after bipolar degradation. By observing and analyzing the test data during the stress application process, the power loop module 300 overcomes the technical limitations of traditional test methods where stress modes are isolated and lack temporal correlation. This enables a comprehensive, accurate, and time-controllable quantitative evaluation of the target device 400 under the combined stress of bipolar degradation and avalanche, improving the accuracy of silicon carbide power device test results and providing an intrinsically safe design basis for the optimization of avalanche protection and the prediction of failure throughout the entire life cycle of high-reliability power electronic systems.

[0074] Furthermore, the method provided in this application embodiment can simultaneously apply bipolar DC stress and avalanche impact, capturing the dynamic influence of the degradation degree of the body diode in the target device 400 on the avalanche tolerance, thereby filling the technical gap in the evaluation of synergistic effects across different stress modes.

[0075] Continue reading Figure 1In one embodiment of this application, the driving module 200 includes a first switch driving module 210, a second switch driving module 220, and a device driving module 230. The first switch driving module 210 is connected to the first output terminal of the controller module 100 and the power loop module 300, respectively. The second switch driving module 220 is connected to the second output terminal of the controller module 100 and the power loop module 300, respectively. The device driving module 230 is connected to the third output terminal of the controller module 100 and the gate of the target device 400, respectively.

[0076] The first switch driving module 210 is used to generate the bipolar degradation pulse signal according to the first test control signal output from the first output terminal of the controller module 100; the second switch driving module 220 is used to generate the avalanche pulse signal according to the second test control signal output from the second output terminal of the controller module 100; the device driving module 230 is used to generate a gate pulse signal according to the third test control signal output from the third output terminal of the controller module 100 and output it to the gate of the target device 400, so that the target device 400 is turned on or off.

[0077] The controller module 100 is connected to the first switch drive module 210, the second switch drive module 220 and the device drive module 230 respectively via power supply cables. The first switch drive module 210, the second switch drive module 220 and the device drive module 230 are connected to the power circuit module 300 respectively via reserved sockets.

[0078] In one possible implementation, such as Figure 5 As shown, the first switch driving module 210 includes: a driving chip U1, a first signal input unit, a first power input unit, a second power input unit, and a first signal output unit. The first signal input unit is connected to the first output terminal of the controller module and the driving chip U1, respectively. The first power input unit is connected to the first power supply and the driving chip U1, respectively. The second power input unit is connected to the second power supply and the driving chip U1, respectively. The first signal output unit is connected to the driving chip U1 and the power circuit module 300, respectively. The first signal input unit is used to input a first test control signal to the driving chip U1. The first power input unit is used to receive the first power signal, filter the first power signal, and use the filtered first power signal to drive the driving chip U1. The second power input unit is used to receive the second power signal, filter the second power signal, and send the filtered second power signal to the driving chip U1. The driving chip U1 is used to convert the first test control signal into a first pulse signal. The first signal output unit is used to perform voltage division processing on the first pulse signal to obtain a bipolar degraded pulse signal.

[0079] The driver chip U1 is connected to the first power supply and the second power supply via power supply cables. Figure 5 In the diagram, Power1 is the first power supply; Power2 is the second power supply. Signal1 is the first test control signal sent by the controller module 100, and IGBT_Driver1 is the bipolar degradation pulse signal.

[0080] In one possible implementation, the first signal input unit includes a resistor R2, with the first end of the resistor R2 connected to the first output terminal of the controller module 100 and the second end of the resistor R2 connected to the driver chip U1, for transmitting the test control signal output by the controller module 100 to the driver chip U1.

[0081] In one possible implementation, the first power input unit includes: a resistor R1, a capacitor C1, and a capacitor C2; the first end of the resistor R1 is connected to the power supply terminal of the driver chip U1, the second end of the resistor R1 is connected to the enable terminal of the driver chip U1 and the first end of the capacitor C1, and the second end of the capacitor C1 is grounded; the first end of the capacitor C2 is connected to the first power supply, and the second end of the capacitor C2 is grounded.

[0082] In one possible implementation, the second power input unit includes a capacitor C3, with the first end of the capacitor C3 connected to the driver chip U1 and the second power supply, and the second end of the capacitor C3 grounded.

[0083] In one possible implementation, the first signal output unit includes: resistors R3, R4, and R5. The first end of resistor R3 is connected to the non-inverting output terminal of driver chip U1, and the second end of resistor R3 is connected to power circuit module 300. The first end of resistor R4 is connected to the inverting output terminal of driver chip U1, and the second end of resistor R4 is connected to power circuit module 300. The first end of resistor R5 is connected to resistors R3, R4, and power circuit module 300, and the second end of resistor R5 is grounded.

[0084] Specifically, when the driver chip U1 outputs a high level, R3 controls the gate charging speed, making the turn-on slope of the power circuit module 300 adjustable; when the driver chip U1 outputs a low level, R4 controls the discharge speed, making the current drop slope at the moment the power circuit module 300 is turned off adjustable.

[0085] In one possible implementation, such as Figure 6 As shown, the structure of the second switch driving module 220 is the same as that of the first switch driving module 210. Figure 6 In the diagram, Power6 is marked as the sixth power supply; Power7 is marked as the seventh power supply. Signal2 is the second test control signal sent by the controller module 100, and IGBT_Driver2 is the avalanche pulse signal.

[0086] The second switch driver module 220 includes: a driver chip U3, a third signal input unit, a sixth power input unit, a seventh power input unit, and a third signal output unit, wherein:

[0087] The third signal input unit includes a resistor R11. The first end of the resistor R11 is connected to the second output terminal of the controller module 100, and the second end of the resistor R11 is connected to the driver chip U3. It is used to transmit the second test control signal output by the controller module 100 to the driver chip U1.

[0088] The sixth power input unit includes a resistor R12, a capacitor C8, and a capacitor C9. The first end of the resistor R12 is connected to the power supply terminal of the driver chip U3 and the sixth power supply. The second end of the resistor R12 is connected to the enable terminal of the driver chip U3 and the first end of the capacitor C8. The second end of the capacitor C8 is grounded. The first end of the capacitor C9 is connected to the sixth power supply. The second end of the capacitor C9 is grounded.

[0089] The seventh power input unit includes a capacitor C9. The first end of the capacitor C9 is connected to the driver chip U3 and the seventh power supply, and the second end of the capacitor C9 is grounded.

[0090] The third signal output unit includes resistors R13, R14, and R15. The first end of resistor R13 is connected to the non-inverting output terminal of driver chip U3, and the second end of resistor R13 is connected to power circuit module 300. The first end of resistor R14 is connected to the inverting output terminal of driver chip U3, and the second end of resistor R14 is connected to power circuit module 300. The first end of resistor R15 is connected to resistors R13, R14, and power circuit module 300, and the second end of resistor R15 is grounded.

[0091] The third signal input unit is used to input the second test control signal to the driver chip U3; the sixth power input unit is used to receive the sixth power signal, filter the sixth power signal, and use the filtered sixth power signal to drive the driver chip U3; the seventh power input unit is used to receive the seventh power signal, filter the seventh power signal, and send the filtered seventh power signal to the driver chip U3; the driver chip U3 is used to convert the second test control signal into a third pulse signal; the third signal output unit is used to perform voltage division processing on the third pulse signal to obtain an avalanche pulse signal.

[0092] In this embodiment, the first switch driving module 210 and the second switch driving module 220 can convert the low-voltage, weak-current first test control signal and the second test control signal into a high-voltage, strong-current bipolar degradation pulse signal and an avalanche pulse signal, thereby achieving precise control over the switching process of the switching elements in the power circuit module 300.

[0093] In one exemplary embodiment, such as Figure 7 As shown, the device driving module 230 includes: a driving chip U2, a second signal input unit, a third power input unit, a fourth power input unit, and a second signal output unit. The second signal input unit is connected to the third output terminal of the controller module and the driving chip U2, respectively. The third power input unit is connected to the third power supply and the driving chip U2, respectively. The fourth power input unit is connected to the fourth power supply and the driving chip U2, respectively. The second signal output unit is connected to the driving chip U2 and the gate of the target device 400, respectively. The second signal input unit is used to input the third test control signal output from the third output terminal of the controller module to the driving chip U2. The third power input unit is used to receive the third power supply signal, filter the third power supply signal, and use the filtered third power supply signal to drive the driving chip U2. The fourth power input unit is used to receive the fourth power supply signal, filter the fourth power supply signal, and send the filtered fourth power supply signal to the driving chip U2. The driving chip U2 is used to convert the third test control signal into a second pulse signal. The second signal output unit is used to perform voltage division processing on the second pulse signal to obtain a gate pulse signal.

[0094] Figure 7 In the diagram, Power3 is the third power supply; Power4 is the fourth power supply; and Power5 is the fifth power supply. Signal3 is the third test control signal sent by the controller module 100, and DUT_Driver is the gate pulse signal.

[0095] For example, the second signal input unit may include a resistor R7, with the first end of the resistor R7 connected to the controller module 100 and the second end of the resistor R7 connected to the driver chip U2.

[0096] The third power input unit may include a resistor R6, a capacitor C4, and a capacitor C5; the first end of the resistor R6 is connected to the power supply terminal of the driver chip U2, the second end of the resistor R6 is connected to the enable terminal of the driver chip U2 and the first end of the capacitor C5, and the second end of the capacitor C5 is grounded; the first end of the capacitor C4 is connected to the third power supply, and the second end of the capacitor C4 is grounded.

[0097] The fourth power input unit may include a capacitor C6. The first end of the capacitor C6 is connected to the driver chip U2 and the fourth power supply, and the second end of the capacitor C6 is grounded.

[0098] The second signal output unit may include resistors R8, R9, and R10, and capacitor C7. The first end of resistor R8 is connected to the non-inverting output terminal of driver chip U2, and the second end of resistor R8 is connected to the gate of target device 400. The first end of resistor R9 is connected to the inverting output terminal of driver chip U2, and the second end of resistor R9 is connected to the gate of target device 400. The first end of resistor R10 is connected to resistors R8 and R9, as well as the gate of target device 400, and the second end of resistor R10 is grounded together with the first end of capacitor C7. The second end of capacitor C7 and driver chip U2 are respectively connected to the fifth power supply.

[0099] The driver chip U2 is connected to the third, fourth, and fifth power supplies via power supply cables.

[0100] In this embodiment, the device driving module 230 converts the third test control signal output by the controller module 100 into a gate pulse signal and outputs it to the gate of the target device 400. During the test, it accurately controls the working state of the target device 400, so that the power circuit module 300 and the target device 400 form the required stress environment. In this embodiment, the first switch driving module 210, the second switch driving module 220 and the device driving module 230 cooperate to control the power circuit module 300, which can ensure that different working conditions can be flexibly switched and combined during the test, and perform dynamic, adjustable and flexible reliability testing on the target device.

[0101] In one exemplary embodiment, see further... Figure 1 The power loop module 300 includes a test circuit and a data acquisition circuit 330. The test circuit is connected to the output terminals of the first switch drive module 210 and the second switch drive module 220, respectively, and is also connected to the target device 400. The data acquisition circuit 330 is connected to the test circuit and the target device 400. The test circuit is used to generate an avalanche voltage based on an avalanche pulse signal and to generate a bipolar degradation current based on a bipolar degradation pulse signal. The data acquisition circuit 330 is used to acquire test data.

[0102] In one possible implementation, such as Figure 8 As shown, the test circuit includes a bipolar stress test circuit 310, which includes a switching element IGBT1. The gate of the switching element IGBT1 is connected to the output terminal of the first switch driving module 210, and the collector of the switching element IGBT1 is connected to the constant current source I. SD The first terminal is connected, with the emitter of the switching element IGBT1 connected to the source of the target device 400; constant current source I SD The second terminal is connected to the drain of the target device 400; the switching element IGBT1 is used to turn on the constant current source I based on the bipolar degradation pulse signal.SD With the target device 400, a bipolar degradation current is generated at the drain of the target device 400.

[0103] During the test, the device driver module 230 controls the target device 400 to be negatively biased and turned off, the switching element IGBT1 is turned on under control, and the constant current source I... SD Applying current to the target device 400 turns on its body diode, forming a current channel and triggering the minority carrier injection effect, resulting in bipolar conduction. Under prolonged or high-current conditions, this leads to defect state accumulation, shortened carrier lifetime, and increased leakage current, a phenomenon known as bipolar degradation.

[0104] In one possible implementation, such as Figure 8 As shown, the test circuit includes an avalanche stress test circuit 320, which includes: a switching element IGBT2, an inductor L1, a diode D1, and a capacitor C. DC1 The gate of the switching element IGBT2 is connected to the second output terminal of the first switch drive module 210. The emitter of the switching element IGBT2 is connected to the drain of the target device 400 through inductor L1 and to the source of the target device 400 through diode D1. The collector of the switching element IGBT2 is connected to the DC power supply DC1 and to the capacitor C. DC1 Connection; the switching element IGBT2 is used to turn on the DC power supply DC1 and capacitor C based on the avalanche pulse signal. DC1 With inductor L1, an avalanche voltage is generated at the drain of target device 400. Here, DUT is target device 400.

[0105] During the test, the device drive module 230 controls the target device 400 to be negatively biased and turned off, while the avalanche stress test circuit 320 is turned on. The DC power supply DC1 and capacitor C... DC1 An avalanche current is applied to the target device 400 through inductor L1, and the avalanche voltage is generated at the drain of the target device 400.

[0106] In this embodiment, the degradation duration and current magnitude can be adjusted by the controller module 100 to influence the bipolar degradation process. Furthermore, the voltage of the DC power supply DC1 can be adjusted and / or the constant current source I can be limited based on the target test mode. SD The magnitude of the output current.

[0107] In this embodiment, DC power supply DC1 and capacitor C DC1 It can provide a smooth and stable current to the target device 400, ensuring that the body diode of the target device 400 conducts under "quasi-DC" conditions and is subjected to stable and pure avalanche stress; diode D1 can provide a freewheeling path, allowing the current of inductor L1 to return to capacitor C through diode D1. DC1It will not allow DC power supply DC1 to flow in, thus preventing DC power supply DC1 from being subjected to backflow.

[0108] In one possible implementation, see further. Figure 8 The test data includes transient characteristic parameters and static electrical parameters; the acquisition circuit 330 includes an oscilloscope G1, a differential probe, a coaxial resistor S1, and a semiconductor parameter analyzer; the first terminal of the oscilloscope G1 is connected to the target device 400 in sequence through the differential probe and the coaxial resistor S1; the semiconductor parameter analyzer is connected to the target device 400; the oscilloscope is used to monitor the transient characteristic parameters corresponding to the target device 400; the semiconductor parameter analyzer is used to monitor the static electrical parameters corresponding to the target device 400.

[0109] During the testing of the target device 400, initial parameter tests were performed using a semiconductor parameter analyzer before the drive module was powered on; after the test, the power circuit module 300 was disconnected from the constant current source I. SD In addition to connecting the DC power supply DC1, disconnecting the auxiliary power supply of the drive module, and after the device stops working, use a semiconductor parameter analyzer to perform post-stress parameter testing to obtain the static electrical parameters of the target device 400 before and after testing.

[0110] The oscilloscope acquires bipolar and avalanche test waveforms of the target device 400 according to preset sampling coupling methods, probe attenuation ratios, trigger modes, trigger types, time bases, horizontal positions, trigger levels, trigger slopes, and reference line positions. The oscilloscope's time base, slope, and reference line parameters are all adjustable.

[0111] In this embodiment, for transient characteristic capture, the oscilloscope is connected to the target device 400 via a differential probe and a coaxial resistor, enabling simultaneous monitoring of key parameters such as drain-source voltage, drain-source current, and gate-source voltage during the avalanche process, and complete recording of its dynamic evolution trajectory. Combined with the oscilloscope triggering strategy, it can capture high-risk signals such as transient overshoot and oscillation. For degradation mechanism analysis, a semiconductor parameter analyzer can be used to compare static electrical parameters such as leakage current and threshold voltage before and after stress application to quantify the weakening effect of bipolar degradation on the device's static blocking capability. This allows for the simultaneous recording and correlation analysis of multiple electrical parameters throughout the entire process from progressive device degradation to dynamic avalanche failure, quantifying the mapping relationship between "body diode degradation degree" and "avalanche failure threshold." This provides a basis for optimizing the design of avalanche clamping circuit parameters in applications such as motor drives and battery protection, helping to avoid "over-design" or "under-protection" problems in protection circuit design. Furthermore, by correlating static parameter degradation data with dynamic avalanche robustness attenuation data, the physical mechanism of hidden failures can be obtained, providing support for constructing a more accurate failure model.

[0112] See Figures 1 to 8The robustness test circuit for silicon carbide power devices in one embodiment of this application includes: a controller module 100, a drive module 200, and a power loop module 300.

[0113] The controller module 100 is used to generate test control signals and send the test control signals to the drive module.

[0114] The drive modules include a first switch drive module 210, a second switch drive module 220, and a device drive module 230. The first switch drive module 210 includes a drive chip U1, a first signal input unit, a first power input unit, a second power input unit, and a first signal output unit. The first signal input unit is connected to the first output terminal of the controller module and the drive chip U1, respectively. The first power input unit is connected to the first power supply and the drive chip U1, respectively. The second power input unit is connected to the second power supply and the drive chip U1, respectively. The first signal output unit is connected to the drive chip U1 and the power loop module 300, respectively. The first signal input unit is used to input the first test control signal output from the first output terminal of the controller module to the drive chip U1. The first power input unit is used to receive the first power signal, filter the first power signal, and use the filtered first power signal to drive the drive chip U1. The second power input unit is used to receive the second power signal, filter the second power signal, and send the filtered second power signal to the drive chip U1. The drive chip U1 is used to convert the first test control signal into a first pulse signal. The first signal output unit is used to perform voltage division processing on the first pulse signal to obtain a bipolar degraded pulse signal. The first signal output unit includes resistors R3, R4, and R5. The first end of resistor R3 is connected to the non-inverting output of driver chip U1, and the second end of resistor R3 is connected to power circuit module 300. The first end of resistor R4 is connected to the inverting output of driver chip U1, and the second end of resistor R4 is connected to power circuit module 300. The first end of resistor R5 is connected to resistors R3, R4, and power circuit module 300, and the second end of resistor R5 is grounded.

[0115] The structure of the second switch driver module 220 is the same as that of the first switch driver module 210, including: a driver chip U3, a third signal input unit, a sixth power input unit, a seventh power input unit, and a third signal output unit. The third signal input unit is used to input the second test control signal to the driver chip U3; the sixth power input unit is used to receive the sixth power signal, filter the sixth power signal, and use the filtered sixth power signal to drive the driver chip U3; the seventh power input unit is used to receive the seventh power signal, filter the seventh power signal, and send the filtered seventh power signal to the driver chip U3; the driver chip U3 is used to convert the second test control signal into a third pulse signal; the third signal output unit is used to perform voltage division processing on the third pulse signal to obtain an avalanche pulse signal.

[0116] The device driving module 230 includes: a driving chip U2, a second signal input unit, a third power input unit, a fourth power input unit, and a second signal output unit. The second signal input unit is connected to the third output terminal of the controller module and the driving chip U2, respectively. The third power input unit is connected to the third power supply and the driving chip U2, respectively. The fourth power input unit is connected to the fourth power supply and the driving chip U2, respectively. The second signal output unit is connected to the driving chip U2 and the gate of the target device 400, respectively. The second signal input unit is used to input the third test control signal output from the third output terminal of the controller module to the driving chip U2. The third power input unit is used to receive the third power supply signal, filter the third power supply signal, and use the filtered third power supply signal to drive the driving chip U2. The fourth power input unit is used to receive the fourth power supply signal, filter the fourth power supply signal, and send the filtered fourth power supply signal to the driving chip U2. The driving chip U2 is used to convert the third test control signal into a second pulse signal. The second signal output unit is used to perform voltage division processing on the second pulse signal to obtain a gate pulse signal and output it to the gate of the target device 400, so that the target device 400 is turned on or off.

[0117] The power circuit module 300 includes a test circuit and a data acquisition circuit 330. The test circuit includes a bipolar stress test circuit 310, which includes a switching element IGBT1. The gate of the switching element IGBT1 is connected to the output terminal of the first switch drive module 210, and the collector of the switching element IGBT1 is connected to a constant current source I. SD The first terminal is connected, with the emitter of the switching element IGBT1 connected to the source of the target device 400; constant current source I SD The second terminal is connected to the drain of the target device 400; the switching element IGBT1 is used to turn on the constant current source I based on the bipolar degradation pulse signal. SD With the target device 400, a bipolar degradation current is generated at the drain of the target device 400.

[0118] The test circuit includes an avalanche stress test circuit 320, which includes: a switching element IGBT2, an inductor L1, a diode D1, and a capacitor C. DC1 The gate of the switching element IGBT2 is connected to the output terminal of the second switch drive module 220. The emitter of the switching element IGBT2 is connected to the drain of the target device 400 through inductor L1 and to the source of the target device 400 through diode D1. The collector of the switching element IGBT2 is connected to the DC power supply DC1 and to the capacitor C. DC1 Connection; the switching element IGBT2 is used to turn on the DC power supply DC1 and capacitor C based on the avalanche pulse signal. DC1 With inductor L1, an avalanche voltage is generated at the drain of target device 400.

[0119] The acquisition circuit 330 includes an oscilloscope G1, a differential probe, a coaxial resistor S1, and a semiconductor parameter analyzer. The first terminal of the oscilloscope G1 is connected to the target device 400 in sequence through the differential probe and the coaxial resistor S1. The semiconductor parameter analyzer is connected to the target device 400. The oscilloscope is used to monitor the transient characteristic parameters corresponding to the target device 400. The semiconductor parameter analyzer is used to monitor the static electrical parameters corresponding to the target device 400.

[0120] like Figure 9 As shown, one embodiment of this application provides a robustness testing method for silicon carbide power devices, applied to the robustness testing circuit of the silicon carbide power devices in the above embodiment. The method includes the following steps 902 to 908:

[0121] Step 902: Generate a test control signal and send the test control signal to the driver module.

[0122] Step 904: Generate bipolar degradation pulse signal and avalanche pulse signal based on the test control signal.

[0123] Step 906: Generate a bipolar degradation current based on the bipolar degradation pulse signal to apply bipolar stress to the target device 400, and generate an avalanche voltage based on the avalanche pulse signal to apply avalanche stress to the target device 400.

[0124] Step 908: Collect test data corresponding to the target device 400. The test data is used to determine the avalanche robustness of the target device 400.

[0125] In some embodiments, the method may further include: testing the feasibility of the driver module by a switching timing test before the test begins.

[0126] In some embodiments, such as Figure 10As shown, the method may further include: performing initial parameter tests using a semiconductor parameter analyzer before powering on the drive module; turning on the auxiliary power supply of the drive module to ensure the drive circuit is working properly before turning on the high-voltage power supply and constant current source in the power loop module 300. After the power supply stabilizes, the controller module 100 generates corresponding test control signals according to the target test mode, which is at least one of "single avalanche-bipolar degradation-single avalanche", "bipolar degradation-single avalanche-recovery" cycle, or "bipolar degradation-repeated avalanche". During the test, an oscilloscope is used to display and acquire waveforms and voltage and current changes.

[0127] In the target test mode, determine whether the termination condition is met. The termination condition can be whether the ratio of the avalanche current drop slope to the avalanche duration exceeds a preset value. If it exceeds the preset value, the test ends, and the DC power supply DC1 and constant current source I connected to the power loop module 300 are turned off. SD The target device 400 stops working, along with the auxiliary power supply connected to the drive module; post-stress parameter testing is performed using a semiconductor parameter analyzer; if the preset value is not exceeded, the controller module 100 continues to generate the corresponding test control signal according to the target test mode and continues the test.

[0128] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0129] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A robustness testing circuit for silicon carbide power devices, characterized in that, The robustness test circuit for silicon carbide power devices includes: a controller module, a drive module, and a power loop module. The controller module is connected to the drive module, the drive module is connected to the power loop module and the target device, and the power loop module is connected to the target device. The controller module is used to generate test control signals and send the test control signals to the drive module; The driving module is used to generate bipolar degradation pulse signals and avalanche pulse signals according to the test control signal; The power loop module is used to generate a bipolar degradation current based on the bipolar degradation pulse signal to apply bipolar stress to the target device, and to generate an avalanche voltage based on the avalanche pulse signal to apply avalanche stress to the target device; the power loop module is also used to collect test data corresponding to the target device, and the test data is used to determine the avalanche robustness of the target device; The driving module includes a first switch driving module, a second switch driving module, and a device driving module. The first switch driving module is connected to the first output terminal of the controller module and the power loop module, respectively. The second switch driving module is connected to the second output terminal of the controller module and the power loop module, respectively. The device driving module is connected to the third output terminal of the controller module and the gate of the target device, respectively. The first switch driving module is used to generate the bipolar degradation pulse signal according to the first test control signal output by the first output terminal of the controller module; The second switch driver module is used to generate the avalanche pulse signal based on the second test control signal output from the second output terminal of the controller module; The device driving module is used to generate a gate pulse signal based on the third test control signal output from the third output terminal of the controller module and output it to the gate of the target device, so that the target device is turned on or off.

2. The robustness test circuit for silicon carbide power devices according to claim 1, characterized in that, The controller module is also used to receive control commands, determine a target test mode according to the control commands, and generate a test control signal corresponding to the target test mode; the target test mode is at least one of "single avalanche-bipolar degradation-single avalanche", "bipolar degradation-single avalanche-recovery" cycle, and "bipolar degradation-repeated avalanche".

3. The robustness test circuit for silicon carbide power devices according to claim 2, characterized in that, The first switch driver module includes: The system comprises a driver chip U1, a first signal input unit, a first power input unit, a second power input unit, and a first signal output unit. The first signal input unit is connected to the first output terminal of the controller module and the driver chip U1, respectively. The first power input unit is connected to the first power supply and the driver chip U1, respectively. The second power input unit is connected to the second power supply and the driver chip U1, respectively. The first signal output unit is connected to the driver chip U1 and the power circuit module, respectively. The first signal input unit is used to input the first test control signal to the driver chip U1; The first power input unit is used to receive a first power signal, filter the first power signal, and use the filtered first power signal to drive the driver chip U1. The second power input unit is used to receive the second power signal, filter the second power signal, and send the filtered second power signal to the driver chip U1; The driver chip U1 is used to convert the first test control signal into a first pulse signal; The first signal output unit is used to perform voltage division processing on the first pulse signal to obtain the bipolar degraded pulse signal.

4. The robustness test circuit for silicon carbide power devices according to claim 3, characterized in that, The first signal output unit includes resistors R3, R4, and R5. The first end of resistor R3 is connected to the non-inverting output terminal of the driver chip U1, and the second end of resistor R3 is connected to the power circuit module. The first end of resistor R4 is connected to the inverting output terminal of the driver chip U1, and the second end of resistor R4 is connected to the power circuit module. The first end of resistor R5 is connected to resistors R3, R4, and the power circuit module, and the second end of resistor R5 is grounded.

5. The robustness test circuit for silicon carbide power devices according to claim 2, characterized in that, The device driving module includes: a driving chip U2, a second signal input unit, a third power input unit, a fourth power input unit, and a second signal output unit. The second signal input unit is connected to the third output terminal of the controller module and the driving chip U2, respectively. The third power input unit is connected to the third power supply and the driving chip U2, respectively. The fourth power input unit is connected to the fourth power supply and the driving chip U2, respectively. The second signal output unit is connected to the driving chip U2 and the gate of the target device, respectively. The second signal input unit is used to input the third test control signal output from the third output terminal of the controller module to the driver chip U2; The third power input unit is used to receive the third power signal, filter the third power signal, and use the filtered third power signal to drive the driver chip U2. The fourth power input unit is used to receive the fourth power signal, filter the fourth power signal, and send the filtered fourth power signal to the driver chip U2. The driver chip U2 is used to convert the third test control signal into a second pulse signal; The second signal output unit is used to perform voltage division processing on the second pulse signal to obtain the gate pulse signal.

6. The robustness test circuit for silicon carbide power devices according to claim 2, characterized in that, The power loop module includes a test circuit and a data acquisition circuit. The test circuit is connected to the output terminals of the first switch driving module and the second switch driving module, respectively, and is also connected to the target device. The data acquisition circuit is connected to the test circuit and is also connected to the target device. The test circuit is used to generate the avalanche voltage based on the avalanche pulse signal, and also to generate the bipolar degradation current based on the bipolar degradation pulse signal; The acquisition circuit is used to acquire the test data.

7. The robustness test circuit for silicon carbide power devices according to claim 6, characterized in that, The test circuit includes a bipolar stress test circuit, which includes a switching element IGBT1. The gate of the switching element IGBT1 is connected to the output terminal of the first switch driving module, and the collector of the switching element IGBT1 is connected to a constant current source I. SD The first terminal is connected, and the emitter of the switching element IGBT1 is connected to the source of the target device; the constant current source I SD The second end is connected to the drain of the target device; The switching element IGBT1 is used to turn on the constant current source I based on the bipolar degradation pulse signal. SD The bipolar degradation current is generated at the drain of the target device.

8. The robustness test circuit for silicon carbide power devices according to claim 6, characterized in that, The test circuit includes an avalanche stress test circuit, which comprises: a switching element IGBT2, an inductor L1, a diode D1, and a capacitor C. DC1 ; The gate of the IGBT2 switching element is connected to the output terminal of the second switch driving module. The emitter of the IGBT2 switching element is connected to the drain of the target device through the inductor L1, and to the source of the target device through the diode D1. The collector of the IGBT2 switching element is connected to the DC power supply DC1, and to the capacitor C. DC1 connect; The switching element IGBT2 is used to turn on the DC power supply DC1 and the capacitor C based on the avalanche pulse signal. DC1 The avalanche voltage is generated at the drain of the target device in conjunction with the inductor L1.

9. The robustness test circuit for silicon carbide power devices according to claim 6, characterized in that, The test data includes transient characteristic parameters and static electrical parameters; The acquisition circuit includes an oscilloscope G1, a differential probe, a coaxial resistor S1, and a semiconductor parameter analyzer; the first terminal of the oscilloscope G1 is connected to the target device in sequence through the differential probe and the coaxial resistor S1. The semiconductor parameter analyzer is connected to the target device; The oscilloscope is used to monitor the transient characteristic parameters corresponding to the target device; The semiconductor parameter analyzer is used to monitor the static electrical parameters corresponding to the target device.

10. A robustness testing method for silicon carbide power devices, characterized in that, The method, applied to the robustness test circuit of the silicon carbide power device according to any one of claims 1-9, comprises the following steps: Generate a test control signal and send the test control signal to the drive module; Based on the test control signal, a bipolar degradation pulse signal and an avalanche pulse signal are generated; A bipolar degradation current is generated based on the bipolar degradation pulse signal to apply bipolar stress to the target device, and an avalanche voltage is generated based on the avalanche pulse signal to apply avalanche stress to the target device. Test data corresponding to the target device is collected, and the test data is used to determine the avalanche robustness of the target device.

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