A data writing method, device, equipment and computer readable storage medium

Abstract

The application discloses a data writing method, device and equipment and a computer readable storage medium, and is applied to the technical field of data storage, and comprises the following steps: loading a secondary queue list; the secondary queue list comprises a primary candidate queue and a secondary high-frequency confirmation queue; selecting a first target block and a second target block from a block; the update frequency of data in the first target block is higher than that of data in the second target block; when it is determined that data is written to a logical block address in the block, it is determined whether the current logical block address is in the secondary queue list; if the current logical block address is in the secondary queue list, the data is written into the first target block, otherwise the data is written into the second target block. Compared with randomly storing data into a data block, the application writes data with a low update frequency and data with a high update frequency into different target blocks based on the secondary queue list as much as possible, ensures that there are few invalid data in a block with a low update frequency, and thus the frequency of garbage collection and defragmentation operations is significantly reduced.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a data writing method, apparatus, device, and computer-readable storage medium. Background Technology

[0002] Since solid-state storage devices primarily use NAND Flash to store data, the smallest unit of erasure for NAND Flash is a block, and the smallest unit of programming is a page. During the data writing process, the same logical block address may be written multiple times, resulting in only the last write being a valid page, while the data from the previous writes becomes invalid. This leads to a lot of invalid data in the receiving block. When many such blocks accumulate, there won't be enough free blocks to receive new data. At this point, garbage collection is needed to release free blocks. Garbage collection involves moving valid pages from garbage blocks to new free blocks, which increases the overall number of erase and program cycles for NAND Flash, thus shortening the lifespan of NAND Flash.

[0003] It is evident that reducing the frequency of garbage collection and the overall number of erase and program cycles for NAND Flash is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a data writing method, apparatus, device and computer-readable storage medium, which solves the problems of high garbage collection frequency and high number of erase and program cycles of NAND Flash in the prior art.

[0005] To address the aforementioned technical problems, this invention provides a data writing method, comprising:

[0006] When the flash controller is powered on, the secondary queue list is loaded; wherein, the secondary queue list is a table that dynamically tracks the addresses of logic blocks with high update frequency based on the primary candidate queue and the secondary high-frequency confirmation queue, the primary candidate queue is the queue that first confirms that data is written to the logic block address and stores the logic block address, and the secondary high-frequency confirmation queue is the queue that stores the current logic block address when the current logic block address is stored in the primary candidate queue a set number of times;

[0007] Select a first target block and a second target block from the blocks; wherein the data in the first target block is updated more frequently than the data in the second target block;

[0008] When it is determined that data should be written to the logical block address in the block, it is determined whether the current logical block address corresponding to the current data is in the secondary queue list;

[0009] If the current logical block address is in the secondary queue list, the data is written to the first target block; otherwise, the data is written to the second target block, so as to perform garbage collection based on the number of valid pages corresponding to each block.

[0010] Optionally, before loading the secondary queue list when the flash controller is powered on, the method further includes:

[0011] When it is determined that the host is writing data to the flash storage device, receive the logical block address sent by the host;

[0012] When the data writing is finished, calculate the data length of the logical block address;

[0013] Determine whether the data length is not greater than the set data length threshold for a single write operation;

[0014] If the data length is not greater than the threshold, then determine whether the current logical block address is in the first-level candidate queue;

[0015] If the current logical block address is not in the first-level candidate queue, then the current logical block address is directly written into the first-level candidate queue to obtain the second-level queue list;

[0016] If it is in the first-level candidate queue, the current logical block address is written into the second-level high-frequency confirmation queue to obtain the second-level queue list.

[0017] Optionally, if the current logical block address is in the primary candidate queue, then the current logical block address is written into the secondary high-frequency confirmation queue to obtain the secondary queue list, including:

[0018] If it is in the first-level candidate queue, then determine whether the current logical block address is in the second-level high-frequency confirmation queue;

[0019] If the current logical block address is in the secondary high-frequency confirmation queue, then the current logical block address is placed back at the head of the secondary high-frequency confirmation queue, and other addresses are moved forward in the previous order.

[0020] If the current logical block address is not in the secondary high-frequency confirmation queue, then the current logical block address is written into the secondary high-frequency confirmation queue in sequence.

[0021] Write the secondary team list into the NAND flash memory and ensure that it is loaded each time the power is turned on again.

[0022] Optionally, after writing data to the first target block if the current logical block address is in the secondary queue list, and otherwise writing data to the second target block, the method further includes:

[0023] The number of valid pages corresponding to each block is determined by the valid page count table;

[0024] When the number of empty blocks is lower than a set threshold, the blocks with the number of valid pages lower than the set threshold are designated as target garbage blocks.

[0025] The target waste block is recycled.

[0026] Optionally, before determining the number of valid pages corresponding to each block through the valid page count table, the following steps are also included:

[0027] Assign a variable to each block to record the number of valid pages in the block, forming the valid page count table;

[0028] Write the effective page count table into the NAND flash memory, and confirm that the effective page count table is loaded each time the power is restarted.

[0029] Optionally, the length of the primary candidate queue is less than the length of the secondary high-frequency confirmation queue.

[0030] The present invention also provides a data writing device applied to a flash memory controller, comprising:

[0031] The secondary queue list loading module is used to load the secondary queue list when the flash controller is powered on; wherein, the secondary queue list is a table that dynamically tracks the addresses of logic blocks with high update frequency based on the primary candidate queue and the secondary high-frequency confirmation queue, the primary candidate queue is the queue that first confirms that data is written to the logic block address and stores the logic block address, and the secondary high-frequency confirmation queue is the queue that stores the current logic block address when the current logic block address is stored in the primary candidate queue a set number of times;

[0032] A target block determination module is used to select a first target block and a second target block from the blocks; wherein the update frequency of the data in the first target block is higher than the update frequency of the data in the second target block;

[0033] The judgment module is used to determine whether the current logical block address corresponding to the current data is in the secondary queue list when it is determined that data should be written to the logical block address in the block.

[0034] The data writing module is used to write data to the first target block if the current logical block address is in the secondary queue list, and otherwise write data to the second target block, so as to perform garbage collection based on the number of valid pages corresponding to each block.

[0035] Optionally, the above-mentioned data writing device further includes:

[0036] The logical block address determination module is used to receive the logical block address sent by the host when it is determined that the host is writing data to the flash storage device;

[0037] The data length determination module is used to calculate the data length of the logical block address when the data writing is finished;

[0038] The data length determination module is used to determine whether the data length is not greater than the set data length threshold for a single write operation.

[0039] The first-level candidate queue judgment module is used to determine whether the current logical block address is in the first-level candidate queue when it is not greater than the data length threshold.

[0040] The first and second-level queue list construction module is used to directly write the current logical block address into the first-level candidate queue if it is not in the first-level candidate queue, so as to obtain the second-level queue list.

[0041] The second-level queue list construction module is used to write the current logical block address into the second-level high-frequency confirmation queue if it is in the first-level candidate queue, so as to obtain the second-level queue list.

[0042] The present invention also provides a data writing device, comprising:

[0043] Memory, used to store computer programs;

[0044] A processor for executing the computer program to implement the steps of the data writing method described above.

[0045] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the above-described data writing method.

[0046] A computer program product includes a computer program / instructions that, when executed by a processor, implement the steps of the above-described data writing method.

[0047] As can be seen, this invention loads a secondary queue list when the flash memory controller is powered on. The secondary queue list is a table that dynamically tracks the addresses of logic blocks with high update frequencies based on a primary candidate queue and a secondary high-frequency confirmation queue. The primary candidate queue is the queue that confirms and stores the logic block address for the first time, and the secondary high-frequency confirmation queue is the queue that stores the current logic block address when it has been recorded in the candidate queue a set number of times. A first target block and a second target block are selected from the blocks. The first target block is a data block that receives data at a first update frequency, and the second target block is a data block that receives data at a second update frequency, where the first update frequency is greater than the second update frequency. When it is determined that data should be written to the logic block address in a block, it is determined whether the current logic block address corresponding to the current data is in the secondary queue list. If the current logic block address is in the secondary queue list, the data is written to the first target block; otherwise, the data is written to the second target block, thus performing garbage collection based on the number of valid pages corresponding to each block. Compared to the current practice of arbitrarily storing all data into data blocks, this invention uses a secondary queue list to write data with low update frequency and data with high update frequency to different target blocks as much as possible. This ensures that there is very little invalid data in the blocks with low update frequency, thereby significantly reducing the frequency of garbage collection (GC) and defragmentation operations, reducing the overall number of erase and program operations for NAND Flash, and improving the overall write efficiency and lifespan of solid-state storage devices.

[0048] In addition, the present invention also provides a data writing device, apparatus, and computer-readable storage medium, which also have the above-mentioned beneficial effects. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0050] Figure 1 A flowchart of a data writing method provided in an embodiment of the present invention;

[0051] Figure 2 A schematic diagram of data in a block provided in an embodiment of the present invention;

[0052] Figure 3 A flowchart illustrating a data writing process provided in an embodiment of the present invention;

[0053] Figure 4 A schematic diagram of a target block provided in an embodiment of the present invention;

[0054] Figure 5This is a schematic diagram of the structure of a data writing device provided in an embodiment of the present invention;

[0055] Figure 6 This is a schematic diagram of a data writing device provided in an embodiment of the present invention. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0057] Please refer to Figure 1 , Figure 1 A flowchart illustrating a data writing method provided in an embodiment of the present invention. This method is applied to a flash memory controller and may include:

[0058] S101, When the flash controller is powered on, the secondary queue list is loaded; wherein, the secondary queue list is a table that dynamically tracks the addresses of logic blocks with high update frequency based on the primary candidate queue and the secondary high-frequency confirmation queue. The primary candidate queue is the queue that first confirms that data is written to the logic block address and stores the logic block address. The secondary high-frequency confirmation queue is the queue that stores the current logic block address when the current logic block address is stored in the primary candidate queue a set number of times.

[0059] The execution entity in this embodiment is a flash memory controller. A flash memory controller, also known as a storage controller or master controller, is an embedded processor system dedicated to managing and operating flash memory (such as NAND Flash). The secondary queue list in this embodiment is a real-time updated table. This secondary queue list contains two queues: a first-level candidate queue, which is the queue where data is first written to and the logical block address is stored. For example, when writing data to the flash memory device, the host sends an LBA (Logical Block Address) to the flash memory controller. After writing, the current LBA is determined and stored in this secondary queue list. If the LBA is not in the first-level candidate queue, it is directly written to the first-level candidate queue in sequence (e.g., first-in-first-out order). If the LBA exists in the first-level candidate queue, it is written to the secondary high-frequency confirmation queue. In this embodiment, the secondary high-frequency confirmation queue is the queue where the current logical block address is stored in the first-level candidate queue a set number of times. This embodiment does not limit the specific value of the set number; for example, the set number in this embodiment can be 1 time or 2 times.

[0060] It should be further noted that, based on any of the above embodiments, the process of loading the secondary queue list when the flash controller is powered on may further include:

[0061] S1011, When it is determined that the host is writing data to the flash memory storage device, receive the logical block address sent by the host;

[0062] S1012, when the data writing is finished, calculate the data length of the logical block address;

[0063] S1013, Determine whether the data length is not greater than the set data length threshold for a single write;

[0064] S1014, if the data length is not greater than the threshold, determine whether the current logical block address is in the first-level candidate queue;

[0065] S1015, if it is not in the first-level candidate queue, then directly write the current logical block address into the first-level candidate queue to obtain the second-level queue list;

[0066] S1016, if it is in the first-level candidate queue, then write the current logical block address into the second-level high-frequency confirmation queue to obtain the second-level queue list.

[0067] This embodiment does not limit a specific data length threshold. For example, the data length threshold in this embodiment can be 4K. Based on the file system, the LBA length of the FAT (File Allocation Table) will not exceed 4K, so the threshold can be 4K. It is understandable that, according to the operating habits of the file system, when copying a file to a flash storage device, the file data is placed in the data area of ​​the file system. Updating a piece of data will update part of the FAT (File Allocation Table). Therefore, after copying a large file, the FAT table will be updated many times. Moreover, the FAT table is fixedly allocated in a small segment of LBA addresses (corresponding to one FAT table, one LBA address for each FAT table, normally corresponding to multiple addresses), which will cause this segment of LBA addresses to be written repeatedly, and the LBA length of each write to the FAT table will not exceed 4K. In this embodiment, during the process of writing the LBA address to the secondary queue list, it will determine whether the data length is not greater than the set single write data length threshold. Only when the data length is not greater than the data length threshold will the write operation proceed. The data is written to the secondary queue list. It's important to note that in a file system (such as FAT), the file data itself is stored in the data area, but file metadata (such as the FAT table and directory entries) is updated frequently and on a small scale. The FAT table tracks the allocation of clusters occupied by files, and each file operation (such as creating, modifying, or deleting a file) may cause a partial update to the FAT table. A single FAT table update typically writes only one sector or one block, and the data length will not exceed 4KB. For example, when copying a large file, the file data may be written continuously, but the FAT table will be updated multiple times to allocate new data. Clusters are updated with only a small amount of data (≤4K) written each time. This causes the LBA addresses corresponding to the FAT table (such as LBA0) to be written repeatedly, but with small amounts written each time. This implementation aims to identify LBA addresses with high update frequency to optimize the data placement strategy of the flash controller (such as storing high-frequency updated data in specific blocks to reduce fragmentation). Large data writes (such as file content) are usually updated infrequently and in large amounts, making them unsuitable for secondary queues. This is because: queue space is limited, and large data writes will quickly exhaust queue resources, causing truly high-frequency small data LBAs to be squeezed out. The update pattern of large data writes is often one-off or sequential, not as frequent as metadata updates. Small data writes (≤4K) are more likely to come from metadata updates (such as the FAT table), which are frequent and prone to write amplification and garbage collection overhead. Therefore, limiting it to no more than 4K can accurately capture these high-value LBAs. The purpose of the secondary queue list is to dynamically track the update frequency of LBA addresses. Queue 1 (primary confirmation queue) is used to initially capture potential high-frequency LBAs (small data written for the first time), and queue 2 (secondary high-frequency confirmation queue) is used to confirm high-frequency LBAs (multiple updates).If writes larger than 4KB were allowed into the queue, the queue would be consumed by infrequent large LBAs, thus reducing queue efficiency. For example, when copying a large file, the LBA corresponding to the file data might only be written once, but the data volume is large. If this data were queued, it would crowd out the truly high-frequency small data LBAs (such as FAT table LBAs). By limiting writes to no more than 4KB, the queue can more effectively focus on frequently updated small data, improving identification accuracy and reducing controller processing overhead. In short, only LBA data lengths no greater than 4KB are written to the secondary queue list because file system metadata updates are typically small-scale, and these updates are the root cause of high frequency. This design ensures that secondary queue resources are used where optimization is most needed, improving the management efficiency of the flash controller.

[0068] It should be further explained that, based on any of the above embodiments, if the current logical block address is in the primary candidate queue, then writing it into the secondary high-frequency confirmation queue to obtain the secondary queue list may include:

[0069] Step 1: If it is in the first-level candidate queue, then determine whether the current logical block address is in the second-level high-frequency confirmation queue;

[0070] Step 2: If it is in the secondary high-frequency confirmation queue, then put the current logical block address back at the head of the secondary high-frequency confirmation queue, and move other addresses to the front in the previous order;

[0071] Step 3: If the current logical block address is not in the secondary high-frequency confirmation queue, write it into the secondary high-frequency confirmation queue in sequence.

[0072] Step 4: Write the secondary team list determined based on the above process into the NAND flash memory, and ensure that it is loaded every time the power is turned on again.

[0073] Understandably, in this embodiment, if the queue space of the primary candidate queue and the secondary high-frequency acknowledgment queue in the secondary queue list is full, the LBA address at the end of the queue is released, and the new LBA address is stored at the head of the queue. In this embodiment, each time a write operation ends, it determines whether the LBA needs to be recorded in the secondary queue based on the data length threshold. First, it checks if the LBA exists in the primary candidate queue. If it doesn't, it's directly written to the primary candidate queue. If the LBA already exists in the primary candidate queue, it indicates that the LBA's update frequency is very high, so it's written to queue 2. If the LBA also exists in queue 2, it's placed back at the head of queue 2, and other addresses are moved sequentially. The flash memory controller writes this secondary queue list data into the NAND Flash according to certain rules, and this table is loaded every time power is restarted. In this embodiment, with limited queue space, a "release the end, put the new address at the head" strategy is adopted to ensure that only the most recent or most active LBAs are retained in the queue. When storing in the secondary high-frequency acknowledgment queue, existing LBAs are moved to the head, prioritizing the LBAs with the highest access frequency. This prevents queues from being occupied by low-value LBAs, improving queue accuracy and efficiency. This is crucial for flash controllers with high real-time requirements, as memory resources are limited and rapid decision-making is essential. Furthermore, the secondary queue list is periodically written to NAND Flash and loaded upon each power-on, ensuring the queue state is restored after a system restart. This maintains long-term optimization and prevents queue information loss due to restarts, avoiding the need to relearn LBA update patterns. This improves system reliability and stability.

[0074] It should be further noted that, based on any of the above embodiments, the length of the primary candidate queue in this embodiment is less than the length of the secondary high-frequency confirmation queue. In this embodiment, the secondary high-frequency confirmation queue is used to store confirmed high-update-frequency LBAs. By setting the secondary high-frequency confirmation queue to be longer, the system can retain more such LBAs, ensuring they are continuously tracked, thereby more accurately guiding data placement. The primary candidate queue is used to store potentially high-frequency LBAs. If queue 1 is too long, it may contain many LBAs that are only written once and not updated again; these LBAs will occupy space but will not truly be high-frequency. Setting queue 1 to be shorter can reduce such "false alarms," ​​preventing queue 1 from being overwhelmed by low-frequency LBAs, thus allowing queue 2 to focus more on truly high-frequency LBAs.

[0075] S102, select a first target block and a second target block from the blocks; wherein the update frequency of the data in the first target block is higher than the update frequency of the data in the second target block.

[0076] In this embodiment, the flash controller needs to select two blocks to receive new data. The data block with a higher update frequency is called the first target block (block1), and the data block with a lower update frequency is called the second target block (block2). In this embodiment, the update frequency of the first target block is higher than that of the data in the second target block. Specifically, the data in the first target block can be data with a lower update frequency, and the data in the second target block can be data with a higher update frequency. If the LBA address to which the current data is written is in the aforementioned secondary queue list, then the update frequency is considered high; otherwise, it is considered low.

[0077] S103, when it is determined that data will be written to the logical block address in the block, determine whether the current logical block address corresponding to the current data is in the secondary queue list.

[0078] Each time new data is written, the controller needs to determine whether the LBA address being written is in the secondary queue list. If it is in the list, the data is written to block1; otherwise, the data is written to block2.

[0079] S104. If the current logical block address is in the secondary queue list, the data is written to the first target block; otherwise, the data is written to the second target block, so as to perform garbage collection based on the number of valid pages corresponding to each block.

[0080] This embodiment does not limit the method for determining the number of valid pages corresponding to each block. For example, this embodiment can count the number of valid pages corresponding to each block when garbage collection is needed, or it can update the number of valid pages corresponding to each block during data writing. In this embodiment, the flash memory controller continuously writes data to the flash memory storage device. As many blocks with invalid pages are generated, the number of empty blocks decreases. When the number of empty blocks drops to a certain threshold, garbage collection will be initiated to avoid insufficient empty blocks due to continued data writing. The blocks to be garbage collected can be determined first by the number of valid pages corresponding to each block. Since invalid pages are concentrated in one block, fewer valid pages can be collected to release empty blocks, thereby reducing the frequency of garbage collection and improving the overall write efficiency and lifespan of the solid-state storage device.

[0081] It should be further noted that, based on any of the above embodiments, after writing the data to the first target block if the current logical block address is in the secondary queue list, and otherwise writing the data to the second target block, the method may further include:

[0082] S1: Determine the number of valid pages corresponding to each block using the valid page count table;

[0083] S2: When the number of empty blocks is lower than the set threshold for the number of empty blocks, the blocks with the number of valid pages lower than the set threshold for the number of valid pages will be designated as target garbage blocks.

[0084] S3: Perform garbage recycling on the target garbage block.

[0085] In this embodiment, to facilitate finding the number of valid data in each block, the physical page within the block is used as the basic unit. When the LBA recorded for a page is the latest data, this page is called a valid page. A variable is assigned to each block to record the number of valid pages in the block, forming a table that records the number of valid pages in each block. This table is called the VPC table (Valid Page Count Table). The flash memory controller writes the VPC table data into the NAND Flash according to certain rules, and the VPC table is loaded every time power is restarted. The number of valid pages in a block is called the VPC value of that block. When the first target block and the second target block are filled with all pages and are released, the VPC value of the first target block will be very small, while the VPC value of the second target block will be very large. Garbage collection in this embodiment is a key process in flash memory management, requiring the erasure of blocks to reclaim space. Before erasure, the valid data in the block must be moved to a new block. Blocks with smaller VPC values ​​(such as block1) have less valid data, resulting in less moving overhead and faster erasure, thereby improving garbage collection efficiency and reducing write amplification and latency. By concentrating frequently updated data in block1, garbage collection becomes more efficient, reducing unnecessary erase operations and data movement, thereby reducing block wear and extending overall device lifespan. The VPC table allows the controller to quickly identify which blocks are suitable for garbage collection (blocks with smaller VPC values ​​are prioritized), reducing search overhead and improving real-time response capabilities. Persistent VPC tables ensure immediate state recovery after power-on, avoiding recalculation and accelerating initialization.

[0086] It should be further explained that, based on any of the above embodiments, before determining the number of valid pages corresponding to each block through the valid page count table, the method may further include: assigning a variable to each block to record the number of valid pages in the block, forming an valid page count table; writing the valid page count table into the NAND flash memory, and confirming that the valid page count table is loaded each time power is restored. In this embodiment, assigning a variable to each block to record the number of valid pages is a space-for-time strategy, using minimal metadata management overhead to achieve a significant improvement in performance, lifespan, and power consumption across the board.

[0087] An embodiment of the present invention provides a data writing method, which may include: S101, loading a secondary queue list when the flash memory controller is powered on; wherein, the secondary queue list is a table that dynamically tracks the addresses of logical blocks with high update frequency based on a primary candidate queue and a secondary high-frequency confirmation queue, the primary candidate queue is the queue that first confirms that data is written to a logical block address and stores the logical block address, and the secondary high-frequency confirmation queue is the queue that stores the current logical block address when the current logical block address is stored in the primary candidate queue a set number of times. S102, selecting a first target block and a second target block from the blocks; wherein, the update frequency of the data in the first target block is higher than the update frequency of the data in the second target block. S103, when it is determined that data is to be written to a logical block address in the block, determining whether the current logical block address corresponding to the current data is in the secondary queue list. S104, if the current logical block address is in the secondary queue list, then the data is written to the first target block; otherwise, the data is written to the second target block, so as to perform garbage collection based on the number of effective pages corresponding to each block. Compared to the current practice of arbitrarily storing all data into data blocks, this invention uses a secondary queue list to write data with low update frequency and data with high update frequency to different target blocks as much as possible. This ensures that there is very little invalid data in the blocks with low update frequency, thereby significantly reducing the frequency of garbage collection (GC) and defragmentation operations, and improving the overall write efficiency and lifespan of solid-state storage devices.

[0088] like Figure 2 , Figure 2 This is a schematic diagram of data within a block provided in an embodiment of the present invention. Each box represents a page. The data writing order of this block is: LBA0->LBA1~LBA5->LBA0->LBA6~LBA7->LBA0->LBA8~LBA11->LBA0. Assuming each LBA data occupies one physical page, the green pages represent valid data, the gray pages represent invalid data, and the white pages represent empty pages. It can be clearly seen that there are many pages with invalid data in this block. When many such blocks accumulate, there will be not enough empty blocks to accept new data. At this time, garbage collection is required to release empty blocks. Garbage collection involves moving valid data from garbage blocks to new empty blocks, which increases the overall number of erase and program cycles for the NAND Flash, resulting in a shorter lifespan for the NAND Flash.

[0089] To address the above shortcomings, the purpose of this invention is to reduce the generation of garbage blocks during the write process, thereby reducing the number of garbage collection cycles and extending the lifespan of NAND Flash. To solve these problems, this invention proposes a flash memory controller write data splitting algorithm. The flash memory controller identifies the update frequency of the user's write command data according to a certain rule, and writes data with low update frequency and data with high update frequency to different blocks as much as possible. This ensures that there is as little invalid data as possible in the blocks receiving low update frequency data.

[0090] For a clearer understanding of this invention, please refer to the following details. Figure 3 , Figure 3 A flowchart illustrating a data writing process provided in this embodiment of the invention may specifically include:

[0091] S201, Select the first target block and the second target block to accept the data to be written.

[0092] S202: Each time data to be written is written, determine whether the address of the logical block being written is in the secondary queue list.

[0093] The list of secondary teams in this embodiment is the same as the list of secondary teams mentioned above, and will not be explained further here.

[0094] S203, if it is in the secondary team list, write the data to the first target block.

[0095] S204, if not in the secondary team list, write the data to the secondary target block.

[0096] S205, assign a variable to each block to record the number of valid pages in the block, forming a valid page count table.

[0097] S206, when the number of empty blocks drops to a certain threshold, the block with the smallest number of valid pages is searched through the valid page count table and used as a garbage block for garbage collection.

[0098] If the current write order of data to the logical block is LBA0->LBA1~LBA5->LBA0->LBA6~LBA7->LBA0->LBA8~LBA11->LBA0, the resulting data distribution of the first and second target blocks is as follows: Figure 4 As shown, Figure 4 The diagram illustrates a target block according to an embodiment of the present invention. It can be seen that the number of invalid pages in the first target block is higher than the number of invalid pages in the second target block.

[0099] In this embodiment of the invention, the current data is dynamically determined to be data in the secondary queue list (high-frequency updated data), and the data is written to different blocks respectively. Among them, the data with high update frequency is preferentially allocated to the first target block, and the data with low update frequency is stored in the second target block. Through this diversion strategy, the frequency of garbage collection (GC) and defragmentation operations can be significantly reduced, thereby improving the overall write efficiency and lifespan of solid-state storage devices.

[0100] The data writing device provided in the embodiments of the present invention will be described below. The data writing device described below and the data writing method described above can be referred to each other.

[0101] Please refer to the details. Figure 5 , Figure 5 A schematic diagram of a data writing device provided in an embodiment of the present invention may include:

[0102] The secondary queue list loading module 100 is used to load the secondary queue list when the flash controller is powered on; wherein, the secondary queue list is a table that dynamically tracks the addresses of logic blocks with high update frequency based on the primary candidate queue and the secondary high-frequency confirmation queue, the primary candidate queue is the queue that first confirms that data is written to the logic block address and stores the logic block address, and the secondary high-frequency confirmation queue is the queue that stores the current logic block address when the current logic block address is stored in the primary candidate queue a set number of times;

[0103] The target block determination module 200 is used to select a first target block and a second target block from the blocks; wherein the update frequency of the data in the first target block is higher than the update frequency of the data in the second target block;

[0104] The judgment module 300 is used to determine whether the current logical block address corresponding to the current data is in the secondary queue list when it is determined that data should be written to the logical block address in the block.

[0105] The data writing module 400 is used to write data to the first target block if the current logical block address is in the secondary queue list, and otherwise write data to the second target block, so as to perform garbage collection based on the number of valid pages corresponding to each block.

[0106] Furthermore, based on any of the above embodiments, the data writing device may further include:

[0107] The logical block address determination module is used to receive the logical block address sent by the host when it is determined that the host is writing data to the flash storage device;

[0108] The data length determination module is used to calculate the data length of the logical block address when the data writing is finished;

[0109] The data length determination module is used to determine whether the data length is not greater than the set data length threshold for a single write operation.

[0110] The first-level candidate queue judgment module is used to determine whether the current logical block address is in the first-level candidate queue when it is not greater than the data length threshold.

[0111] The first and second-level queue list construction module is used to directly write the current logical block address into the first-level candidate queue if it is not in the first-level candidate queue, so as to obtain the second-level queue list.

[0112] The second-level queue list construction module is used to write the current logical block address into the second-level high-frequency confirmation queue if it is in the first-level candidate queue, so as to obtain the second-level queue list.

[0113] Furthermore, based on any of the above embodiments, the second-level team list construction module may include:

[0114] The determination unit for whether the current logical block address is in the secondary high-frequency confirmation queue is used to determine whether the current logical block address is in the secondary high-frequency confirmation queue if it is in the primary candidate queue.

[0115] The repositioning unit is used to, if the current logical block address is in the secondary high-frequency acknowledgment queue, reposition the current logical block address to the head of the secondary high-frequency acknowledgment queue, and move other addresses sequentially to the next address in the previous order.

[0116] The direct write unit is used to write the current logical block address into the secondary high-frequency confirmation queue in sequence if it is not in the secondary high-frequency confirmation queue.

[0117] A power-on loading unit is identified, which is used to write the secondary queue list into the NAND flash memory and confirms that loading occurs each time the power is restored.

[0118] Furthermore, based on any of the above embodiments, the data writing device may further include:

[0119] The effective page count determination module is used to determine the effective page count for each block using the effective page count table.

[0120] The target garbage block determination module is used to identify blocks with a number of valid pages that are lower than a set threshold for the number of empty blocks when the number of empty blocks is lower than a set threshold for the number of valid pages.

[0121] The waste recycling module is used to recycle the target waste block.

[0122] Furthermore, based on any of the above embodiments, the data writing device may further include:

[0123] The effective page count table determination module is used to assign a variable to each block to record the number of effective pages in the block, forming the effective page count table;

[0124] The valid page count table power-on recording determination module is used to write the valid page count table into the NAND flash memory and confirm that the valid page count table is loaded each time the power is restarted.

[0125] Furthermore, based on any of the above embodiments, the length of the primary candidate queue is less than the length of the secondary high-frequency confirmation queue.

[0126] It should be noted that the order of the modules and units in the aforementioned data writing device can be changed without affecting the logic.

[0127] An embodiment of the present invention provides a data writing device, which may include: a secondary queue list loading module 100, used to load a secondary queue list when the flash memory controller is powered on; wherein, the secondary queue list is a table that dynamically tracks the addresses of logical blocks with high update frequency based on a primary candidate queue and a secondary high-frequency confirmation queue, the primary candidate queue is a queue that first confirms that data is written to a logical block address and stores the logical block address, and the secondary high-frequency confirmation queue is a queue that stores the current logical block address when the current logical block address is stored in the primary candidate queue a set number of times; a target block determination module 200, used to select a first target block and a second target block from the blocks; wherein, the update frequency of the data in the first target block is higher than the update frequency of the data in the second target block; a judgment module 300, used to determine whether the current logical block address corresponding to the current data is in the secondary queue list when it is determined that data is written to the logical block address in the block; and a data writing module 400, used to write the data to the first target block if the current logical block address is in the secondary queue list, otherwise write the data to the second target block, so as to perform garbage collection based on the number of effective pages corresponding to each block. Compared to the current practice of arbitrarily storing all data into data blocks, this invention uses a secondary queue list to write data with low update frequency and data with high update frequency to different target blocks as much as possible. This ensures that there is very little invalid data in the blocks with low update frequency, thereby significantly reducing the frequency of garbage collection (GC) and defragmentation operations, and improving the overall write efficiency and lifespan of solid-state storage devices.

[0128] The following describes a data writing device provided by an embodiment of the present invention. The data writing device described below and the data writing method described above can be referred to each other.

[0129] Please refer to Figure 6 , Figure 6A schematic diagram of a data writing device provided in an embodiment of the present invention may include:

[0130] Memory 10 is used to store computer programs;

[0131] Processor 20 is used to execute computer programs to implement the data writing method described above.

[0132] The memory 10, processor 20, and communication interface 30 all communicate with each other through the communication bus 40.

[0133] In this embodiment of the invention, the memory 10 is used to store one or more programs. The programs may include program code, which includes computer operation instructions. In this embodiment of the invention, the memory 10 may store programs for implementing the following functions:

[0134] When the flash controller is powered on, the secondary queue list is loaded. The secondary queue list is a table that dynamically tracks the addresses of logic blocks with high update frequency based on the primary candidate queue and the secondary high-frequency confirmation queue. The primary candidate queue is the queue that first confirms that data has been written to the logic block address and stores the logic block address. The secondary high-frequency confirmation queue is the queue that stores the current logic block address when the current logic block address has been stored in the primary candidate queue a set number of times.

[0135] Select a first target block and a second target block from the blocks; wherein the data in the first target block is updated more frequently than the data in the second target block.

[0136] When it is determined that data should be written to the logical block address, it is determined whether the current logical block address corresponding to the current data is in the secondary queue list.

[0137] If the current logical block address is in the secondary queue list, the data is written to the first target block; otherwise, the data is written to the second target block, so that garbage collection is performed based on the number of valid pages corresponding to each block.

[0138] In one possible implementation, the memory 10 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; and the data storage area may store data created during use.

[0139] Furthermore, memory 10 may include read-only memory and random access memory, providing instructions and data to the processor. A portion of the memory may also include NVRAM. The memory stores operating systems and operating instructions, executable modules, or data structures, or subsets thereof, or extended sets thereof, wherein the operating instructions may include various operating instructions for implementing various operations. The operating system may include various system programs for implementing various basic tasks and handling hardware-based tasks.

[0140] Processor 20 can be a central processing unit (CPU), an application-specific integrated circuit, a digital signal processor, a field-programmable gate array, or other programmable logic device. Processor 20 can be a microprocessor or any conventional processor. Processor 20 can call programs stored in memory 10.

[0141] The communication interface 30 can be an interface for the communication module, used to connect with other devices or systems.

[0142] Of course, it should be noted that, Figure 6 The structure shown does not constitute a limitation on the data writing device in the embodiments of the present invention. In practical applications, the data writing device may include devices such as... Figure 6 More or fewer components as shown, or combinations of certain components.

[0143] The computer-readable storage medium provided in the embodiments of the present invention is described below. The computer-readable storage medium described below and the data writing method described above can be referred to in correspondence.

[0144] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the above-described data writing method.

[0145] The computer-readable storage medium may include various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0146] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0147] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0148] Finally, it should be noted that in this document, relationships such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0149] The above provides a detailed description of a data writing method, apparatus, device, and computer-readable storage medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A data writing method, characterized in that, Applied to flash memory controllers, including: When the flash controller is powered on, the secondary queue list is loaded; wherein, the secondary queue list is a table that dynamically tracks the addresses of logic blocks with high update frequency based on the primary candidate queue and the secondary high-frequency confirmation queue, the primary candidate queue is the queue that first confirms that data is written to the logic block address and stores the logic block address, and the secondary high-frequency confirmation queue is the queue that stores the current logic block address when the current logic block address is stored in the primary candidate queue a set number of times; Select a first target block and a second target block from the blocks; wherein the data in the first target block is updated more frequently than the data in the second target block; When it is determined that data should be written to the logical block address in the block, it is determined whether the current logical block address corresponding to the current data is in the secondary queue list; If the current logical block address is in the secondary queue list, the data is written to the first target block; otherwise, the data is written to the second target block, so as to perform garbage collection based on the number of valid pages corresponding to each block. The process, which includes loading the secondary queue list when the flash controller is powered on, further includes: When it is determined that the host is writing data to the flash storage device, receive the logical block address sent by the host; When the data writing is finished, calculate the data length of the logical block address; Determine whether the data length is not greater than the set data length threshold for a single write operation; If the data length is not greater than the threshold, then determine whether the current logical block address is in the first-level candidate queue; If the current logical block address is not in the first-level candidate queue, then the current logical block address is directly written into the first-level candidate queue to obtain the second-level queue list; If it is in the first-level candidate queue, then the current logical block address is written into the second-level high-frequency confirmation queue to obtain the second-level queue list; If the current logical block address is in the primary candidate queue, it is written to the secondary high-frequency confirmation queue to obtain the secondary queue list, which includes: If it is in the first-level candidate queue, then determine whether the current logical block address is in the second-level high-frequency confirmation queue; If the current logical block address is in the secondary high-frequency confirmation queue, then the current logical block address is placed back at the head of the secondary high-frequency confirmation queue, and other addresses are moved forward in the previous order. If the current logical block address is not in the secondary high-frequency confirmation queue, then the current logical block address is written into the secondary high-frequency confirmation queue in sequence. The secondary team list is written into NAND flash memory so that it is loaded each time power is restored.

2. The data writing method according to claim 1, characterized in that, After writing data to the first target block if the current logical block address is in the secondary queue list, and otherwise writing data to the second target block, the method further includes: The number of valid pages corresponding to each block is determined by the valid page count table; When the number of empty blocks is lower than a set threshold for the number of empty blocks, the blocks with the number of valid pages lower than the set threshold for the number of valid pages are designated as target garbage blocks; The target waste block is recycled.

3. The data writing method according to claim 2, characterized in that, Before determining the number of valid pages for each block using the valid page count table, the following steps are also included: Assign a variable to each block to record the number of valid pages in the block, forming the valid page count table; The effective page count table is written into the NAND flash memory so that the effective page count table is loaded each time the power is restored.

4. The data writing method according to claim 1, characterized in that, The length of the primary candidate queue is less than the length of the secondary high-frequency confirmation queue.

5. A data writing device, characterized in that, An application to a flash memory controller, based on the data writing method according to any one of claims 1 to 4, comprising: The secondary queue list loading module is used to load the secondary queue list when the flash controller is powered on; wherein, the secondary queue list is a table that dynamically tracks the addresses of logic blocks with high update frequency based on the primary candidate queue and the secondary high-frequency confirmation queue, the primary candidate queue is the queue that first confirms that data is written to the logic block address and stores the logic block address, and the secondary high-frequency confirmation queue is the queue that stores the current logic block address when the current logic block address is stored in the primary candidate queue a set number of times; A target block determination module is used to select a first target block and a second target block from the blocks; wherein the update frequency of the data in the first target block is higher than the update frequency of the data in the second target block; The judgment module is used to determine whether the current logical block address corresponding to the current data is in the secondary queue list when it is determined that data should be written to the logical block address in the block. The data writing module is used to write data to the first target block if the current logical block address is in the secondary queue list, and otherwise write data to the second target block, so as to perform garbage collection based on the number of valid pages corresponding to each block.

6. A data writing device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the data writing method as described in any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the data writing method as described in any one of claims 1 to 4.

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