A method, medium and device for generating a PLC drive file for interlocking performance testing

Abstract

A method for generating PLC driver files for interlocking performance testing includes the following steps: obtaining the original files of the interlocking station, the original files including the original data file of the interlocking station and the pre-configuration file of the interlocking station; determining whether the interlocking station information is complete; generating a hardware description file according to the data type of the interlocking station; generating a driver configuration file according to the node information in the pre-configuration file of the interlocking station; reading the pre-configuration file of the interlocking station again to generate a test station configuration file; and storing the generated hardware description file, driver configuration file, and test station configuration file in a specified directory of an industrial control computer to complete the generation of the PLC driver file. This invention can effectively improve the usability and maintainability of the interlocking performance testing platform, and also greatly improve the testing efficiency and capability of interlocking performance testing, thus possessing significant practical value.

Description

Technical Field

[0001] This invention relates to the field of computer interlocking performance testing technology for rail transit, specifically to a method, medium, and device for generating PLC driver files for interlocking performance testing. Background Technology

[0002] As a form of public transportation, rail transit relies heavily on its core computer interlocking system, a real-time control system that enables interlocking functions at railway stations and is crucial for ensuring train operation safety. In recent years, with the continuous expansion of my country's railway construction, the conflict between on-site testing and operational needs for interlocking performance has become increasingly prominent, placing more stringent demands on indoor testing of signaling products. Currently, interlocking performance testing platforms utilize PLC modules connected to data acquisition and driver boards to more accurately simulate on-site operational scenarios, thereby improving the reliability of indoor interlocking performance testing.

[0003] Although the interlocking performance testing platform can achieve its testing objectives, the deployment process of its testing environment is exceptionally complex. The platform primarily relies on manual configuration of data for each station, which is not only inefficient but also prone to errors. Once a problem occurs, troubleshooting often requires starting from scratch, resulting in a significant amount of repetitive work. Therefore, under the dual pressures of limited interlocking product performance in field applications and accelerated product update cycles, the usability issue of existing interlocking performance testing platforms urgently needs to be addressed. To this end, this invention proposes an automatic PLC driver file generation method, aiming to effectively solve the aforementioned technical challenges.

[0004] It is understood that the above statements only provide background information related to the present invention and do not necessarily constitute prior art. Summary of the Invention

[0005] The purpose of this invention is to provide a method for generating PLC driver files for interlocking performance testing, which automatically generates all PLC driver files, solving the problems of low efficiency and high error rate in the existing technology, which can only rely on manual methods to generate each file sequentially.

[0006] To achieve the above objectives, a first aspect of the present invention provides a method for generating PLC driver files for interlocking performance testing, comprising the following steps: S1. Obtain the original files of the interlocking yard; the original files include the original data file of the interlocking yard and the pre-configuration file of the interlocking yard; obtain the interlocking yard information according to the original data file of the interlocking yard, including: interlocking yard name, interlocking yard ID and interlocking yard data type; S2. Determine if the interlocking station information is complete; if yes, proceed to S3 to continue operation; if no, proceed to S1 to reacquire the interlocking station information. S3. Generate a hardware description file based on the data type of the interlocking station; S4. Generate a driver configuration file based on the node information in the interlocking station pre-configuration file and by parsing the hardware description file generated in S3; S5. Read the interlocking station pre-configuration file again and generate the test station configuration file; S6. Save the generated hardware description file, driver configuration file, and test station configuration file into the specified directory of the industrial control computer to complete the generation of the PLC driver file.

[0007] Preferably, in step S2, the step of determining whether the interlocking station information is complete includes: determining whether the interlocking station name and interlocking station ID are not empty, and whether the interlocking station data type is a valid type.

[0008] Preferably, in step S3, the step of generating the hardware description file includes: S31. Obtain the interlocking station data type from the interlocking station information based on the original data file of the interlocking station; S32. If the data type of the interlocking station is a first data type, then the RACK value of the layer number in the original data file of the interlocking station is corrected; if the data type of the interlocking station is a second data type, then the RACK value of the layer number remains unchanged. S33. Output the corrected data according to the predetermined format and generate a hardware description file.

[0009] Preferably, in step S32, the principle for correcting the RACK value of the layer number is as follows: delete the data containing the specific string "RACK=1" in the first layer of the original data file of the interlocking station, and then subtract one from the RACK value of the layer number and assign it to the layer number RACK.

[0010] Preferably, in step S4, the step of generating the driver configuration file includes: S41. Based on the interlocking station pre-configuration file, obtain the station node information, interlocking test platform communication parameter node information, and PLC communication parameter node information; S42. Create the interlock configuration root element and corresponding node of the driver configuration file; S43. Write the node information obtained in S41 into the corresponding nodes of the driver configuration file created in S42. S44. Parse the hardware description file generated in S3, obtain the layer number, board type, slot value and the number of code bits occupied by each board in the hardware description file, load them into the dictionary and save them. S45. Based on the layer number and channel value in the dictionary, parse the starting base address of the PLC device, load it into the dictionary and save it; S46. Create a PLC device parameter node in the driver configuration file. Fill in the PLC device parameter node information according to the dictionary to complete the generation of the driver configuration file.

[0011] Preferably, the layer number is an integer greater than or equal to 1 and less than 13; the board type is a data acquisition board or a driver board; and the slot value is an integer greater than or equal to 0 and less than 15.

[0012] Preferably, the calculation method for the number of code positions varies depending on the type of the board and whether the interlocking station is a national railway station or a subway station; specifically, if the board type is a data acquisition board, when the original test station data is a national railway station, the number of code positions occupied by this layer of boards is 192; when the original test station data is a subway station, the number of code positions occupied by this layer of boards is 208; if the board type is a drive board, when the test station data is a national railway station, the number of code positions occupied by this layer of boards is 96; when the test station data is a subway station, the number of code positions occupied by this layer of boards is 104.

[0013] Preferably, the step of parsing and calculating the starting base address of the PLC device includes calculating the corresponding first PLC starting base address and second PLC starting base address for the first interlocking device and the second interlocking device, respectively.

[0014] Preferably, in step S5, the step of generating the test station configuration file includes: S51. Read station node information and network configuration node information from the interlocking station pre-configuration file; S52. Write the station ID and station name into the test station configuration node of the test station configuration file; S53. Write the local IP and port number information of the automated testing software into the test station network configuration node of the test station configuration file; S54. Complete the writing of the test station configuration file information and generate the test station configuration file.

[0015] Preferably, the PLC driver file is loaded into an industrial computer, which is communicatively connected to the interlocking equipment and the PLC equipment. The industrial computer is used to control the PLC equipment by reading the PLC driver file, thereby performing performance tests on the interlocking equipment.

[0016] A second aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, it implements the method for generating PLC driver files for interlocking performance testing.

[0017] A third aspect of the present invention provides an electronic device, including a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, it implements the method for generating PLC driver files for interlocking performance testing.

[0018] In summary, compared with the prior art, the PLC driver file generation method for interlocking performance testing provided by the present invention has at least the following beneficial effects: (1) The method of the present invention can automatically generate all PLC driver files, including HDW files, XML files and TS_Config files, solving the problem that in the existing technology, each file can only be generated manually in sequence and the generation process of each file is inefficient and has a high error rate. (2) The method of the present invention can solve the problem that the original interlocking battlefield file cannot be adapted to the PLC environment. It is not only applicable to the deployment of PLC drive environment for interlocking national railway performance testing, but also compatible with the deployment of PLC drive environment for metro performance testing. (3) The method of the present invention can effectively improve the availability and maintainability of the interlocking performance test platform, and can also greatly improve the testing efficiency and capability of interlocking performance testing, and has great practical value; (4) The method of the present invention can be applied to any person who performs interlocking performance testing, no longer relying on the experience of the personnel, and solves the usability problem of the PLC drive environment for interlocking performance testing from the source. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the interlocking performance testing system according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating the generation process of a PLC driver file according to an embodiment of the present invention. Figure 3 This is a flowchart illustrating the HDW file generation process according to an embodiment of the present invention. Figure 4 This is a flowchart illustrating the XML file generation process according to an embodiment of the present invention; Figure 5 This is a flowchart of HDW file parsing according to an embodiment of the present invention; Figure 6 This is a flowchart of the PLC base address resolution process according to an embodiment of the present invention; Figure 7 This is a flowchart illustrating the generation process of a TS_Config file according to an embodiment of the present invention. Detailed Implementation

[0020] The following is in conjunction with the appendix Figure 1 -Appendix Figure 7 The present invention will be further illustrated by describing a preferred embodiment in detail.

[0021] It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions. They are only used to facilitate and clarify the purpose of illustrating the embodiments of the present invention, and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationship, or adjustments to the size should still fall within the scope of the technical content disclosed in the present invention, provided that they do not affect the effects and objectives that the present invention can produce.

[0022] It should be noted that, in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only the expressly listed elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0023] Figure 1 This is a schematic diagram of an interlocking performance testing system according to an embodiment of the present invention. The interlocking performance testing system includes: interlocking equipment, a PLC (Programmable Logic Controller) device, and an industrial PC. The PLC device is connected to the interlocking equipment via a cable to transmit control signals and data, ensuring that the PLC device can effectively control and interact with the interlocking equipment. This allows the interlocking equipment to perform corresponding operations based on the control signals sent by the PLC device and to feed back its own status data and other information to the PLC device. The industrial PC is connected to both the interlocking equipment and the PLC device to issue various operation commands to the interlocking equipment and the PLC device, as well as to monitor and manage their respective operating states, ensuring that the entire interlocking performance testing system can accurately and stably perform testing work according to predetermined requirements and procedures.

[0024] Specifically, in this embodiment, the interlocking device includes a first interlocking device and a second interlocking device connected to each other, and the PLC device includes a first PLC device and a second PLC device connected to each other; and the first interlocking device is correspondingly connected to the first PLC device, and the second interlocking device is correspondingly connected to the second PLC device.

[0025] It should be noted that configuring two interlocking devices and two PLC devices not only avoids single points of failure, but also enables verification interaction between devices, ensuring the safety, reliability, and test integrity of the interlocking performance testing system.

[0026] In this embodiment, the interlocking equipment, PLC equipment, and industrial control computer are located on the same local area network. This invention provides a method for generating PLC driver files for interlocking performance testing. The PLC driver file generated by this method is loaded into the industrial control computer, which reads the PLC driver file to achieve driver communication with the interlocking equipment and the PLC equipment. It should be noted that in this invention, the interlocking equipment is equivalent to general-purpose equipment; the interlocking station is equivalent to a simulation environment constructed under a specific data file (such as the internal information of a high-speed rail station or subway station); interlocking performance testing through the interlocking equipment can test various data of the interlocking station.

[0027] like Figure 2 As shown, this invention provides a method for generating PLC driver files for interlocking performance testing, specifically including the following steps: S1. Obtain the original file of a certain interlocking station, the original file including the interlocking station original data file and the interlocking station pre-configuration file; obtain the interlocking station information according to the interlocking station original data file, including: interlocking station name, interlocking station ID and interlocking station data type; S2. Determine if the interlocking station information is complete; if yes, proceed to S3 to continue operation; if no, proceed to S1 to reacquire the interlocking station information. S3. Generate HDW files (hardware description files) based on the data types of the interlocking stations. S4. Based on the node information in the interlocking station pre-configuration file and by parsing the HDW file generated in S3, generate an XML file (drive configuration file). S5. Read the interlocking station pre-configuration file again and generate the TS_Config (test station configuration file) file; S6. Save the generated HDW file, XML file, and TS_Config file to the specified directory of the industrial control computer to complete the generation of the PLC driver file.

[0028] Furthermore, in step S2, the conditions for determining whether the interlocking station information is complete are: the interlocking station name (Station_name) is not empty, the interlocking station ID (Station_ID) is not empty, and the interlocking station data type (Station_HDW_type) is RACK or EXT. If all of the above conditions are met, the obtained interlocking station information is valid and complete, and the next step can be performed. Otherwise, the process returns to step S1, and the interlocking station information is retrieved again until it is complete. Here, RACK and EXT are two data types present in the original file. If the data type is not one of these two, it is invalid, indicating that the obtained interlocking station information is invalid and incomplete, and the next step cannot be performed. The process must return to step S1, and the interlocking station information must be retrieved again until it is complete.

[0029] It should be noted that the PLC driver files used for interlocking performance testing in this invention include: HDW files, XML files, and TS_Config files. The HDW file provides a standardized hardware configuration method for the PLC device. Because the input interlocking station's original data file and the PLC device are incompatible, the original data file needs to be corrected to generate an HDW file to adapt to the PLC driver, enabling the PLC device to recognize and operate the connected interlocking devices. Understandably, through the HDW file, the PLC device can easily perform status monitoring and control operations on the interlocking devices, thereby achieving precise control of the interlocking system. The XML file stores various configuration data and test scripts, including parameter configurations for the interlocking devices and the PLC device, test scenario settings, and data structures to be recorded during the test. Furthermore, the XML file allows data transmission between different devices and software, thereby improving the flexibility and interoperability of the entire system. The TS_Config file is a configuration file specific to the interlocking performance testing system of this invention, used to configure the communication parameters of the test equipment. It can be customized according to different test requirements, such as the communication parameters of the PLC device server.

[0030] Furthermore, S3 is used to convert the original data file of the interlocking station into a hardware configuration description that can be recognized by the PLC equipment, such as... Figure 3 As shown, generating an HDW file involves the following steps: S31. Based on the input interlocking station raw data file, obtain the interlocking station data type from the interlocking station information; S32. If the data type of the interlocking station is RACK (first data type), the RACK value of the layer number in the original data file of the interlocking station needs to be corrected; if the data type of the interlocking station is EXT (second data type), the RACK value of the layer number does not need to be corrected. S33. Output the corrected data according to the predetermined format and generate an HDW file.

[0031] Specifically, in S32, the correction principle is as follows: delete all data containing the specific string "RACK=1" in the first layer of the interlocking yard original data file, and then sequentially decrement the layer number RACK value by one and reassign it to the layer number RACK, i.e., "RACK=RACK-1". This can be explained as follows: each layer of data in the interlocking yard original data file has a flag, i.e., "RACK=n", but it does not match the PLC device. Therefore, this flag "RACK=n" in the interlocking yard original data file needs to be corrected to "RACK=RACK-1" to match the PLC device.

[0032] Specifically, in S33, the predetermined format is understood to be an HDW file formatted according to the specifications of the PLC device, which includes board hierarchy, slot distribution and type identification.

[0033] Furthermore, it should be noted that the interlocking device is equipped with a drive code bit, and the PLC device is equipped with a PLC base address. In this invention, the XML file is the file that directly drives the PLC device. This file can map the drive code bit in the interlocking device to the PLC base address in the PLC device one-to-one, enabling the PLC device to accurately control and operate each drive code bit of the interlocking device, thereby realizing complex control logic and functions, and ensuring data transmission and status synchronization between the PLC device and the interlocking device.

[0034] Based on the above, S4 is used to establish the drive mapping relationship between the interlocking device and the PLC device, such as... Figure 4 As shown, generating an XML file specifically includes the following steps: S41. Based on the interlocking station pre-configuration file, obtain the [Station] (station) node information, [ISTP_NET] (interlocking test platform communication parameters) node information, and [QPLC_NET] (PLC communication parameters) node information; wherein, the industrial control computer controls the interlocking equipment by reading the information of the three nodes respectively; S42. Create the root element of the XML file. <ciadapter>(Interlocking configuration), and create three nodes corresponding to the interlocking station pre-configuration file, namely: <station>(Station) nodes, <istp>(Interlocking test platform) nodes and<QPLC_Net> (PLC) node; S43. Write the node information obtained in S41 into the corresponding nodes created in S42. S44. Parse the HDW file generated in S3, obtain the layer number RACK, board type Type, slot value Slot, and the number of code bits occupied by each board in the HDW file, load them into the dictionary Dict and save them; wherein, the board is a physical module or unit that constitutes the hardware architecture of the PLC device or interlocking device, and the board type is consistent with the data type of the interlocking station; the slot value Slot is the number of boards; S45. Based on the layer number RACK and slot value Slot in the dictionary Dict, parse the starting base address of the PLC device, sequentially obtain the starting base address Sys_A_Addr of the first PLC device of the first interlocking device and the starting base address Sys_B_Addr of the second PLC device of the second interlocking device corresponding to each layer of the board, and load the obtained starting base address Sys_A_Addr of the first PLC device of the first interlocking device and the starting base address Sys_B_Addr of the second PLC device of the second interlocking device into the dictionary Dict, and save the dictionary Dict; S46, Recreate<QPLC_Oper> In the (PLC device parameters) node, the layer number RACK is used as the key of the dictionary Dict, and the board type Type is used as the value of the dictionary Dict. Based on the key RACK in the dictionary Dict, the value Type corresponding to the key RACK is written to the dictionary.<QPLC_Oper> Node type child node <type>Write the first PLC start base address Sys_A_Addr or the second PLC start base address Sys_B_Addr to the PLC.<QPLC_Oper> The base address of the node's child nodes<Head_device> Write the code point count Dev_count to<QPLC_Oper> Quantum nodes with the most code bits<Device_count> ; Use the layer number RACK as the key of the dictionary Dict, and the slot value as the value of the dictionary Dict. Based on the key RACK in the dictionary Dict, fill in the slot values ​​corresponding to the key RACK in sequence.<QPLC_Oper> Node hardware board sub-node <board>The attribute values ​​ensure that the generated XML file accurately corresponds to the board according to the slot, guaranteeing that the subsequently generated PLC driver file can precisely control the board according to the slot; where, when the slot value is 0 and the board type is Write, <board>The attribute value is filled with "bit_num="16""; when the slot value is 0 and the board type is Read, <board>The attribute value is filled with "bit_num="8""; when the slot value Slot is not 0, the Station_ID (station ID) obtained in S41 is written to <board>The attribute value of station, write the RACK value to <board>The attribute value ext is set, and the current Slot value is written to it. <board>The attribute value slot; Read the keys and values ​​of the dictionary Dict sequentially to complete the XML file.<QPLC_Oper> (PLC device parameters) Fill in the node information until all node information in the XML file is filled in, and generate the XML file.

[0035] It is understood that in this embodiment, the final format of the dictionary Dict is Dict{Rack:Type,slot,Sys_A_Addr,Sys_B_Addr,dev_count}, that is, in this dictionary Dict, the key is RACK, and the values ​​are Type, slot, Sys_A_Addr, Sys_B_Addr and dev_count.

[0036] Furthermore, in S41, the [Station] node information includes Station_type, Station_name, Station_ID, and Station_HDW_type (interlocking station data type); the [ISTP_NET] node information includes Local_IP, Local_Port, ISTPServer_IP, and ISTPServer_Port; and the [QPLC_NET] node information includes Local_IP, Local_Port, PLC_IP, and PLC_Port.

[0037] Furthermore, in S44, as Figure 6 As shown, parsing the HDW file generated in S3 specifically includes the following steps: S441. Read the HDW file generated in S3; S442. Obtain the layer number RACK for each board in the generated HDW file; where, due to hardware limitations, the value of RACK is an integer greater than or equal to 1 and less than 13. S443. Obtain the board type Type for each layer in the generated HDW file; where, if the board is a data acquisition board, i.e., VIIB board, then the type Type value for the board is Write; if the board is a driver board, i.e., VOOB board, then the type Type value for the board is Read. S444. Obtain the slot where each board is located in the file. If a slot is not configured with a board, the slot value Slot is 0. Due to hardware limitations, the slot value Slot is an integer greater than or equal to 0 and less than 15. S445. Based on the layer number RACK and board type Type corresponding to each board obtained from S442 and S443, calculate the number of code bits occupied by each board: Dev_count. S446. Load the layer number RACK, board type Type, slot value (number of boards) Slot and the number of code bits occupied by each board obtained from the parsing in S442, S443, S444 and S445 into the dictionary Dict, and then save the dictionary Dict.

[0038] Furthermore, in S445, if the board type Type is Write, then when the original test station file is a national railway station, the number of code positions occupied by the board at this layer is Dev_count=16*12=192; when the original test station file is a subway station, the number of code positions occupied by the board at this layer is Dev_count=16*13=208.

[0039] Furthermore, in S445, if the board type Type is Read, then when the test station data is a national railway station, the number of code positions occupied by the board on this layer is Dev_count=8*12=96; when the test station data is a subway station, the number of code positions occupied by the board on this layer is Dev_count=8*13=104.

[0040] Furthermore, in S5, the TS_Config file is used to configure the communication parameters of the PLC device. Its generation includes two parts: [Station_TS] (test station configuration) node and [NetWork] (test station network configuration) node, such as... Figure 7 As shown, the specific steps include: S51. Read the pre-configuration file again to obtain the [Station] (site) node information and the [EGGPLANT_NET] (network configuration for communication with the automated test software) node information. The [STATION] node information includes Station_name (site name) and Station_ID (site ID), and the [EGGPLANT_NET] node information includes Local_IP (local IP of the automated test software) and Local_Port (local port number of the automated test software). S52. Write the Station_ID and Station_name obtained in S51 into the [Station_TS] section of the TS_Config file, where Station ID=Station_ID, HDW Name=Station_name+".HDW”; S53. Write the [EGGPLANT_NET] node information obtained in S51 into the [NetWork] section of the TS_Config file; wherein, the Local_IP and Local_Port of the [EGGPLANT_NET] node information are written into the FEP_Local_IP (FEP server local IP) and FEP_Local_Port (FEP server local port number) of [NetWork]; the significance of this step is to configure the communication address between the local end and the remote end; S54. Complete the writing of TS_Config file information and generate the TS_Config file.

[0041] Furthermore, in step S6, the HDW file, XML file, and TS_Config file are combined and stored in a designated directory on the industrial control computer, which becomes the PLC driver file. This means that the PLC device cannot be directly operated manually; it needs to be controlled through the PLC driver file. The interlocking device, the PLC device, and the industrial control computer are all on the same local area network. The industrial control computer reads the information from the HDW file, XML file, and TS_Config file to control the PLC device, thereby enabling interaction between the PLC device and the interlocking device.

[0042] Furthermore, the present invention also provides a computer-readable storage medium storing a computer program thereon, characterized in that, when the computer program is executed by a processor, it implements the PLC driver file generation method for interlocking performance testing.

[0043] Furthermore, the present invention also provides an electronic device, including a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, it implements the PLC driver file generation method for interlocking performance testing.

[0044] In summary, the PLC driver file generation method for interlocking performance testing provided by this invention can automatically generate all PLC driver files, including data HDW files, code position driver XML files, and network driver TS_Config files. This solves the problems of low efficiency and high error rates in existing technologies where each file can only be generated manually. The method is not only applicable to the deployment of PLC driver environments for interlocking performance testing of national railways, but also compatible with the deployment of PLC driver environments for metro performance testing. It effectively improves the availability and maintainability of the interlocking performance testing platform, while also significantly enhancing the testing efficiency and capabilities of interlocking performance testing, ensuring the quality of interlocking product releases, and possesses great practical value.

[0045] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.< / board> < / board> < / board> < / board> < / board> < / board> < / type> < / istp> < / station> < / ciadapter>

Claims

1. A PLC drive file generation method for interlocking performance test, characterized by, Includes the following steps: S1. Obtain the original files of the interlocking station; the original files include the original data file of the interlocking station and the pre-configuration file of the interlocking station; The interlocking station information is obtained from the original data file of the interlocking station, including: interlocking station name, interlocking station ID, and interlocking station data type; wherein, the interlocking station data type includes a first data type and a second data type; the first data type is RACK, and the second data type is EXT; S2. Determine if the interlocking station information is complete; if yes, proceed to S3 to continue operation; if no, proceed to S1 to reacquire the interlocking station information. S3. Generate a hardware description file based on the data type of the interlocking station; S4. Generate a driver configuration file based on the node information in the interlocking station pre-configuration file and by parsing the hardware description file generated in S3; S5. Read the interlocking station pre-configuration file again and generate the test station configuration file; S6. Save the generated hardware description file, driver configuration file and test station configuration file into the specified directory of the industrial computer to complete the generation of PLC driver files; In step S3, the step of generating the hardware description file includes: S31. Obtain the interlocking station data type from the interlocking station information based on the original data file of the interlocking station; S32. If the data type of the interlocking station is a first data type, then the RACK value of the layer number in the original data file of the interlocking station is corrected; if the data type of the interlocking station is a second data type, then the RACK value of the layer number remains unchanged. S33. Output the corrected data according to the predetermined format and generate a hardware description file; In step S4, the step of generating the driver configuration file includes: S41. Based on the interlocking station pre-configuration file, obtain the station node information, interlocking test platform communication parameter node information, and PLC communication parameter node information; S42. Create the interlock configuration root element and corresponding node of the driver configuration file; S43. Write the node information obtained in S41 into the corresponding nodes of the driver configuration file created in S42. S44. Parse the hardware description file generated in S3, obtain the layer number, board type, slot value and the number of code bits occupied by each board in the hardware description file, load them into the dictionary and save them. S45. Based on the layer number and channel value in the dictionary, parse the starting base address of the PLC device, load it into the dictionary and save it; S46. Create a PLC device parameter node in the driver configuration file, and fill in the PLC device parameter node information according to the dictionary to complete the generation of the driver configuration file; In step S5, the step of generating the test station configuration file includes: S51. Read station node information and network configuration node information from the interlocking station pre-configuration file; S52. Write the station ID and station name into the test station configuration node of the test station configuration file; S53. Write the local IP and port number information of the automated testing software into the test station network configuration node of the test station configuration file; S54. Complete the writing of the test station configuration file information and generate the test station configuration file.

2. The PLC drive file generation method for interlocking performance test according to claim 1, wherein, In step S2, the step of determining whether the interlocking station information is complete includes: determining whether the interlocking station name and interlocking station ID are not empty, and whether the interlocking station data type is a valid type.

3. The PLC driver file generation method for interlocking performance testing as described in claim 1, characterized in that, In step S32, the principle for correcting the RACK value of the layer number is as follows: Delete the data containing the specific string "RACK=1" in the first layer of the original data file of the interlocking station, and then decrement the layer number RACK value by one and reassign it to the layer number RACK.

4. The method for generating a PLC drive file for interlocking performance test according to claim 1, wherein, The layer number is an integer greater than or equal to 1 and less than 13; The board type is either a data acquisition board or a driver board; The channel value is an integer greater than or equal to 0 and less than 15.

5. The method for generating a PLC drive file for interlocking performance test according to claim 4, wherein, The calculation method for the number of code positions varies depending on the type of the card and whether the interlocking station is a national railway station or a subway station. Specifically, if the board type is a data acquisition board, when the original test station file is a national railway station, the number of code positions occupied by this board is 192; when the original test station file is a subway station, the number of code positions occupied by this board is 208. If the board type is a driver board, then when the test station data is a national railway station, the number of code positions occupied by this board is 96; when the test station data is a subway station, the number of code positions occupied by this board is 104.

6. The method for generating a PLC drive file for interlocking performance test according to claim 1, wherein, The step of resolving the starting base address of the PLC device includes calculating the corresponding first PLC starting base address and second PLC starting base address for the first interlocking device and the second interlocking device, respectively.

7. The method for generating a PLC drive file for interlocking performance test according to claim 1, wherein, The PLC driver file is loaded into the industrial control computer, which is communicatively connected to the interlocking equipment and the PLC equipment. The industrial control computer is used to control the PLC equipment by reading the PLC driver file, and then to perform performance testing on the interlocking equipment.

8. A computer readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by the processor, it implements the PLC driver file generation method for interlocking performance testing as described in any one of claims 1 to 7.

9. An electronic device, comprising: It includes a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, it implements the PLC driver file generation method for interlocking performance testing as described in any one of claims 1 to 7.

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