A risc-v processor, subsystem, and method to accelerate sparse left-looking lu decomposition

Abstract

The application discloses a RISC-V processor, a system and a method for accelerating sparse left look LU decomposition, aiming at solving the problem of low efficiency of non-continuous memory access in sparse matrix calculation. The processor comprises a processor control unit, a scalar core, a vector processing unit and an input / output interface. The scalar core is based on the RV32IMF instruction set and supports the ZFINX extension; the vector processing unit is equipped with a 128-bit vector register stack, supports 4-channel vector operation, and integrates a custom instruction GmacS for merging vector gather load, scalar-vector multiply-accumulate and scatter storage operation, thereby reducing instruction overhead. The system cooperates with the main CPU through DMA to efficiently offload the computationally intensive task. Experiments show that the scheme has a performance improvement of up to 3.8 times compared with the original algorithm, is suitable for sparse matrix calculation scenes such as circuit simulation, and has the advantages of high energy efficiency and low delay.

Description

Technical Field

[0001] This invention belongs to the field of computer architecture technology, and in particular relates to a RISC-V processor, subsystem and method for accelerating sparse left-look LU decomposition. Background Technology

[0002] Solving sparse linear equation systems Ax = b (where A is a known sparse matrix, b is a known vector, and x is the vector to be solved) is a crucial component of many scientific and engineering problems. There are two approaches to solving Ax = b: one is the iterative method, which obtains an exact solution continuously through iteration; the other is the direct method, which obtains an exact solution directly in a finite number of steps. The core of the direct method is typically to perform LU decomposition on A to obtain a lower triangular matrix L and an upper triangular matrix U (A = LU), and then obtain the final solution x through two triangular decompositions (i.e., Ly = b, Ux = y). Because the direct method can obtain more accurate solutions, it is widely used in fields such as SPICE (Simulation Program with Integrated Circuit Emphasis) circuit simulation, and the LU decomposition of the sparse matrix, as its core, is particularly crucial.

[0003] A typical sparse LU decomposition process consists of three stages: preprocessing, symbolic decomposition, and numerical decomposition. In circuit simulation applications, the preprocessing and symbolic decomposition stages are usually executed only once, their purpose being to reorder the matrices and obtain the non-zero element structure of the LU matrix. In contrast, the numerical decomposition stage needs to be executed repeatedly in each iteration, involving a large number of floating-point operations. Therefore, the numerical decomposition stage accounts for the majority of the time in the entire sparse LU decomposition process and is the core part that determines its performance.

[0004] In sparse LU decomposition algorithms, left-looking and right-looking algorithms are two classic and efficient methods. For sparse matrices commonly found in circuit simulation, the distribution of their non-zero elements is usually extremely sparse and irregular, making it difficult to effectively form the large-size dense submatrices required by the right-looking algorithm. Therefore, left-looking algorithms are more widely used due to their better adaptability. For example, the sparse left-looking LU decomposition algorithm (G / P algorithm) proposed by Gilbert and Peierls has become the computational core of several mainstream sparse linear solvers (such as KLU and its parallel version NICSLU).

[0005] Currently, commonly used solvers incorporating sparse left-look LU decomposition algorithms typically run on GPUs and CPUs. On one hand, the massive computing units of GPU platforms provide favorable conditions for accelerating and optimizing the solution process; however, the complex data dependencies in sparse matrix decomposition make it difficult to improve GPU computing power utilization and hardware scheduling efficiency, making software scheduling indispensable in applications. On the other hand, with the advent of the post-Moore's Law era, CPUs, in pursuit of versatility, have complex microarchitectures, making it increasingly difficult for software to fully utilize hardware performance, and the energy efficiency of traditional general-purpose architecture design methods is approaching its limit. Therefore, there is still considerable room for optimization in the specific implementation of solvers incorporating sparse left-look LU decomposition algorithms.

[0006] Processors can accelerate sparse left-look LU decomposition using data-level parallelism based on vector instruction sets, but vectorization introduces challenges in data access. The core of the performance-determining numerical decomposition part of the sparse left-look LU decomposition algorithm lies in the frequent data exchange between compressed sparse matrices (such as L and U matrices) and an uncompressed column vector used to temporarily store computation results. This means the processor needs to repeatedly load data from non-contiguous addresses in memory and store the results in the same non-contiguous address after computation. Within the framework of existing vector instruction sets, this part must be decomposed into a series of independent instructions, including "aggregation" instructions for loading non-contiguous data and "scattering" instructions for storage. This frequent access to non-contiguous addresses is a key technical obstacle restricting the performance improvement of sparse computing.

[0007] This invention addresses the issues of significant optimization potential in solvers based on sparse left-look LU decomposition and the high memory access instruction overhead during the numerical decomposition stage of vectorized sparse left-look LU decomposition, which restricts performance improvement. It proposes a RISC-V processor to accelerate sparse left-look LU decomposition. Summary of the Invention

[0008] The purpose of this invention is to provide a RISC-V processor, subsystem, and method for accelerating sparse left-look LU decomposition, so as to solve the above-mentioned technical problems.

[0009] To address the aforementioned technical problems, the specific technical solution of the RISC-V processor, subsystem, and method for accelerating sparse left-look LU decomposition according to the present invention is as follows: A RISC-V processor for accelerating sparse left-look LU decomposition includes a processor control unit, a scalar core, a vector processing unit tightly coupled to the scalar core, and an input / output interface. The processor control unit sends instructions to the scalar core. The scalar core adopts the RV32IMF instruction set architecture, a three-stage pipelined architecture, and ZFINX extensions, and includes a scalar register file consisting of 32 integer / single-precision floating-point registers. The vector processing unit supports 128-bit vector operations with a 4-channel configuration, includes a vector register file consisting of eight 128-bit vector registers, a scalar-vector multiplier-adder and a vector adder, and a data path supporting the custom instruction GmacS. The input / output interface is used for reading and writing back scalar and vector data.

[0010] Furthermore, the semantics of GmacS are GmacS rs1, rs2, vs1, vs2. GmacS is a 32-bit instruction, where bits 30-31 and 12-14 are unused, and bits 0-7 are the opcode, using the custom-0 value in the RISC-V standard to avoid conflict with existing instructions. GmacS contains four source operands: bits 15-19 represent scalar register rs1, used to provide the base address for memory access; bits 25-29 represent scalar register rs2, used to provide the scalar multiplier in multiply-accumulate operations; bits 8-10 represent vector register vs1, used to provide the vector operand in multiply-accumulate operations; and bits 20-24 represent vector register vs2, used to provide the vector index for memory access.

[0011] Furthermore, the processor executes GmacS instructions through a GmacS-enabled data path in the vector processing unit. Its internal data flow is as follows: ① The vector adder in the vector processing unit adds the base address and the vector index to generate a set of vector addresses; ② The processor reads data from memory based on these addresses. This read data is not written to the vector register file but is directly fed as an operand into the single-precision floating-point scalar-vector multiply-accumulate unit; ③ The calculation result of the single-precision floating-point scalar-vector multiply-accumulate unit is also not written to the vector register file; ④ The processor writes this result back to the same set of memory addresses generated in ① as write data.

[0012] Furthermore, the input / output interface includes a 32-bit wide scalar input / output interface and a 128-bit wide vector input / output interface. The 32-bit wide scalar input / output interface is used for reading and writing back scalar data; the 128-bit wide vector input / output interface is used for reading and writing back vector data. When a memory block conflict occurs, the vector input / output interface generates a stall signal to the processor control unit, and the processor control unit stops issuing the next instruction until all data has been successfully gathered or dispersed.

[0013] This invention also discloses a subsystem that works with DMA to accelerate computational tasks and reduce the load on the main CPU. The subsystem includes a RISC-V processor for accelerating sparse left-look LU decomposition, and also includes a subsystem register, a memory controller, and a direct memory access DMA. The subsystem register, the RISC-V processor for accelerating sparse left-look LU decomposition, the memory controller, and the direct memory access DMA are mounted under the main CPU via an AHB Lite bus matrix. When encountering data-intensive and computationally intensive tasks, the main CPU selects to assign the computational task to this subsystem for execution.

[0014] Furthermore, the process of the subsystem executing the computational task allocated by the CPU is as follows: the main CPU configures the computational task type, input data, and output data address information into the subsystem register. After the RISC-V processor core that accelerates sparse left-look LU decomposition reads the subsystem register, it configures DMA to move data from main memory to SRAM connected to the memory controller. After receiving the notification signal that the DMA transfer is complete, the processor core starts reading, calculating, and writing the data back to SRAM. After the processor core completes the computational task, it configures DMA again. The DMA moves the calculated data from SRAM back to main memory. After receiving the signal that the DMA transfer is complete, the processor core sends an interrupt to the main CPU, indicating that the entire computational task has been completed.

[0015] This invention also discloses a vectorized sparse left-look LU decomposition method using the custom instruction GmacS of a RISC-V processor to accelerate sparse left-look LU decomposition. This method converts the large number of cyclic scalar operations in the original sparse left-look LU decomposition algorithm into a small number of vector operations, and uses GmacS to implement the vector aggregation loading, scalar-vector multiplication accumulation operation, and vector scatter storage operation.

[0016] The RISC-V processor, subsystem, and method for accelerating sparse left-look LU decomposition of the present invention have the following advantages: Highly efficient acceleration of sparse left-view LU decomposition By using the custom instruction GmacS, the vector aggregation and loading, scalar-vector multiplication and accumulation, and vector scattering operations, which originally required multiple instructions, are combined into a single instruction, significantly reducing the number of instructions and improving computational efficiency. Experimental data shows that the performance can be improved by up to 3.8 times compared to the original algorithm.

[0017] Optimized data flow design The GmacS instruction avoids temporary data storage in the register file by reusing the vector address generation logic, reducing data transfer overhead and memory access latency, thereby further improving the processor's throughput.

[0018] Supports access to non-contiguous addresses To address the challenge of accessing non-contiguous memory addresses in sparse matrix computation, the GmacS instruction dynamically generates addresses using a vector adder, efficiently supporting aggregated loading and distributed storage operations, thus solving a key performance bottleneck in sparse computation.

[0019] Reduce main CPU load By using a subsystem design that works in conjunction with DMA, the main CPU can offload data-intensive tasks (such as sparse left-look LU decomposition) to this processor for execution, reducing the load on the main CPU and improving the overall system energy efficiency.

[0020] Flexible vectorization support The vector processing unit supports 4-channel 128-bit vector operations, which can efficiently process irregular data distributions in sparse matrices. At the same time, it provides hardware-level optimization for specific computing tasks through custom instruction extensions.

[0021] Compatibility and scalability Based on the RISC-V instruction set architecture, the processor boasts excellent compatibility and scalability. The custom instruction GmacS uses standard custom-0 encoding, avoiding conflicts with existing instructions and facilitating integration into the existing ecosystem.

[0022] Applicable to practical application scenarios In scientific computing fields such as circuit simulation, sparse left-look LU decomposition is a core algorithm. The processor in this invention significantly improves the performance of such applications through hardware acceleration, providing an efficient solution for industry.

[0023] In summary, this invention effectively solves the performance bottleneck in sparse left-look LU decomposition through hardware instruction optimization and subsystem design, combining high efficiency, flexibility, and practicality. Attached Figure Description

[0024] Figure 1 Processor architecture block diagram for accelerating sparse left-look LU decomposition; Figure 2 A diagram illustrating the GmacS command format; Figure 3 This is a schematic diagram of the GmacS instruction execution flow; Figure 4 This is a block diagram of the subsystem structure. Figure 5 This is a schematic diagram of the original sparse left-look LU decomposition algorithm; Figure 6 This is a schematic diagram of the vectorized sparse left-look LU decomposition algorithm; Figure 7 A schematic diagram of key operations in the vectorized sparse left-look LU decomposition algorithm; Figure 8 This is a schematic diagram of the vectorized sparse left-look LU decomposition algorithm using GmacS. Detailed Implementation

[0025] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides an RISC-V processor, subsystem, and method for accelerating sparse left-look LU decomposition.

[0026] like Figure 1 As shown, this invention discloses a RISC-V processor for accelerating sparse left-look LU decomposition, comprising a processor control unit (PCU), a scalar core, a vector processing unit tightly coupled to the scalar core, and input / output interfaces. The PCU sends instructions to the scalar core. The scalar core employs the RV32IMF instruction set architecture, a three-stage pipelined architecture, and ZFINX extensions, and includes a scalar register file consisting of 32 integer / single-precision floating-point registers. The vector processing unit supports 128-bit vector operations with a 4-channel configuration, includes a vector register file consisting of eight 128-bit vector registers, a scalar-vector multiplier-adder, and a vector adder, and includes a data path supporting the custom instruction GmacS.

[0027] The semantics of GmacS are GmacS rs1, rs2, vs1, vs2, and its encoding format is as follows: Figure 2 As shown. GmacS is a 32-bit instruction set, with bits 30-31 and 12-14 unused. Bits 0-7 are the opcode, using the custom-0 value (0001011) from the RISC-V standard to avoid conflict with existing instructions. It contains four source operands: bits 15-19 represent the scalar register rs1, used to provide the base address for memory access; bits 25-29 represent the scalar register rs2, used to provide the scalar multiplier in multiply-accumulate operations; bits 8-10 represent the vector register vs1, used to provide the vector operand in multiply-accumulate operations; and bits 20-24 represent the vector register vs2, used to provide the vector index for memory access.

[0028] like Figure 3 As shown, the processor that accelerates LU decomposition of sparse matrices executes GmacS instructions through a GmacS-enabled data path in the vector processing unit. Its internal data flow is as follows: ① The vector adder in the vector processing unit adds the base address and the vector index to generate a set of vector addresses; ② The processor reads data from memory based on this address. This read data is not written to the vector register file but is directly fed as an operand into the single-precision floating-point scalar-vector multiplication accumulator; ③ The calculation result of the single-precision floating-point scalar-vector multiplication accumulator is also not written to the vector register file; ④ The processor writes this result back to the same set of memory addresses generated in ① as write data. In this way, GmacS eliminates the temporary storage of the target data (memory read data) of the vector aggregation loading operation and the source data (memory write data) of the vector scattering storage operation in the register file, while reusing the vector addresses for aggregation and scattering operations.

[0029] The input / output interface includes a 32-bit scalar input / output interface and a 128-bit vector input / output interface. The 32-bit scalar input / output interface is used for reading and writing back scalar data; the 128-bit vector input / output interface is used for reading and writing back vector data. Meanwhile, when gathering and distributing vectors from memory, memory block conflicts are unavoidable. When a memory block conflict occurs, the vector input / output interface generates a stall signal to the PCU, causing the PCU to stop issuing the next instruction until all data has been successfully gathered or distributed.

[0030] like Figure 4 As shown, a subsystem of the present invention, which works with DMA to accelerate computational tasks and reduce the load on the main CPU, includes a subsystem register, a RISC-V processor for accelerating sparse left-look LU decomposition, a memory controller, and direct memory access (DMA), which is mounted under the main CPU via an AHB Lite bus matrix. When encountering data-intensive and computationally-intensive tasks such as the sparse left-look LU decomposition algorithm, the main CPU can choose to assign the computational task to this subsystem for execution.

[0031] The process of this subsystem executing the CPU-assigned computation task is as follows: The main CPU configures information such as the computation task type, input data, and output data addresses into the subsystem register. After the RISC-V processor core, which accelerates sparse left-lookahead LU decomposition, reads the subsystem register, it configures DMA to move data from main memory to SRAM connected to the memory controller. After receiving the DMA transfer completion notification signal, the processor core begins reading, calculating, and writing the data back to SRAM. After the processor core completes the computation task, it reconfigures DMA, which moves the calculated data from SRAM back to main memory. After receiving the DMA transfer completion signal, the processor core sends an interrupt to the main CPU, indicating that the entire computation task has been completed. This method, in conjunction with DMA, can accelerate the computation task while reducing the load on the main CPU.

[0032] The original sparse left-look LU decomposition algorithm is as follows: Figure 5 As shown, the sparse matrices A, L, and U are stored in a compressed format, while the intermediate variable x, whose updates depend on the non-zero pattern of L, is stored in an uncompressed format. The numerical decomposition part (lines 5-7) of the original sparse left-look LU decomposition algorithm is essentially a cyclic scalar operation. To improve algorithm performance, this part of the operation can be vectorized, converting the large number of cyclic scalar operations into a small number of vector operations. The vectorized sparse left-look LU decomposition algorithm is shown below. Figure 6 As shown. For L in compressed storage, the scalar load operation traversal is transformed into a one-step vector load operation (line 5). For the intermediate variable x, the scalar load operation traversal is transformed into a two-step vector load operation (lines 6 and 7), namely, the index load of x and the data load of x, and finally, the corresponding vector storage operation is executed. Figure 6 The vectorized sparse left-look LU decomposition algorithm shown has two vector loading operations (lines 6 and 7). Due to the uncompressed storage of the intermediate variable x, these constitute typical vector aggregation loading operations. This also leads to the corresponding vector scattering storage operation (line 9), as follows: Figure 7 As shown. The address of the vector aggregation loading operation is the same as the address of the scatter storage operation, which is reusable. Therefore, GmacS can be used to perform this part of the operation.

[0033] The sparse left-look LU decomposition algorithm using GmacS is as follows: Figure 8 As shown. In line 7, the proposed new GmacS instruction replaces... Figure 6 The algorithm contains three instructions: vector aggregation and loading instruction, scalar-vector multiplication and accumulation instruction, and vector scatter storage instruction. Figure 2(Lines 7-9). The four variables addr_x, x(j), L(j+1:n,j) and v_idx(j) correspond to the operands rs1, rs2, vs1, and vs2 in GmacS, respectively. Addr_x represents the base address of the intermediate variable x in SRAM, and v_idx(j) represents the vector index of the address of the intermediate variable x. Since the vector aggregation loading and vector scatter storage operations only exist in the loop starting from line 4, the remaining part of applying GmacS's sparse left-look LU decomposition algorithm... Figure 2 The algorithm remains the same. Through instruction substitution, the operations in the for loop starting from line 4 can be executed with only three instructions: two vector loading instructions and the new instruction GmacS proposed in this invention, which also reduces the number of instructions.

[0034] To verify the application effect of this invention, the processor for accelerating sparse left-look LU decomposition proposed in this invention was modeled on a periodically accurate simulator, and experimental verification was performed on 12 sparse matrices in the field of circuit simulation in practical applications. Experimental results show that, compared with the original sparse left-look LU decomposition algorithm and the vectorized sparse left-look LU decomposition algorithm without GmacS, the vectorized sparse left-look LU decomposition algorithm using GmacS can achieve performance improvements of up to 3.8 times and 1.3 times, respectively.

[0035] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A RISC-V processor for accelerating sparse left-look LU decomposition, characterized in that, The system includes a processor control unit, a scalar core, a vector processing unit tightly coupled to the scalar core, and input / output interfaces. The processor control unit sends instructions to the scalar core. The scalar core adopts the RV32IMF instruction set architecture, a three-stage pipelined architecture, and ZFINX extensions, and includes a scalar register file consisting of 32 integer / single-precision floating-point registers. The vector processing unit supports 128-bit vector operations with a 4-channel configuration, includes a vector register file consisting of eight 128-bit vector registers, a scalar-vector multiplier-adder and a vector adder, and a data path supporting the custom instruction GmacS. The input / output interfaces are used for reading and writing back scalar and vector data. The semantics of GmacS are GmacS rs1, rs2, vs1, vs2. GmacS is a 32-bit instruction set, where bits 30-31 and 12-14 are unused, and bits 0-7 are the opcode, using the custom-0 value from the RISC-V standard to avoid conflict with existing instructions. GmacS contains four source operands: bits 15-19 represent the scalar register rs1, used to provide the base address for memory access; bits 25-29 represent the scalar register rs2, used to provide the scalar multiplier in multiply-accumulate operations; bits 8-10 represent the vector register vs1, used to provide the vector operand in multiply-accumulate operations; and bits 20-24 represent the vector register vs2, used to provide the vector index for memory access. The processor executes GmacS instructions through a GmacS-enabled data path in the vector processing unit. Its internal data flow is as follows: ① The vector adder in the vector processing unit adds the base address and the vector index to generate a set of vector addresses; ② The processor reads data from memory based on these addresses. This read data is not written to the vector register file but is directly fed as an operand into the single-precision floating-point scalar-vector multiply-accumulate unit; ③ The calculation result of the single-precision floating-point scalar-vector multiply-accumulate unit is also not written to the vector register file; ④ The processor writes this result back to the same set of memory addresses generated in ① as write data.

2. The RISC-V processor for accelerating sparse left-look LU decomposition according to claim 1, characterized in that, The input / output interface includes a 32-bit scalar input / output interface and a 128-bit vector input / output interface. The 32-bit scalar input / output interface is used for reading and writing back scalar data; the 128-bit vector input / output interface is used for reading and writing back vector data. When a memory block conflict occurs, the vector input / output interface generates a stall signal to the processor control unit, and the processor control unit stops issuing the next instruction until all data has been successfully gathered or dispersed.

3. A subsystem that works with DMA to accelerate computational tasks and reduce the load on the main CPU, comprising a RISC-V processor for accelerating sparse left-look LU decomposition as described in any one of claims 1-2, characterized in that, It also includes subsystem registers, memory controllers, and direct memory access DMA. The subsystem registers, the RISC-V processor for accelerating sparse left-look LU decomposition, the memory controller, and the direct memory access DMA are mounted under the main CPU via the AHB Lite bus matrix. When encountering data-intensive and computationally intensive tasks, the main CPU selects to assign the computational task to the subsystem for execution.

4. The subsystem for accelerating computing tasks and reducing the load on the main CPU in conjunction with DMA as described in claim 3, characterized in that, The process of the subsystem executing the computation task allocated by the CPU is as follows: The main CPU configures the computation task type, input data, and output data address information into the subsystem register. After the RISC-V processor core that accelerates sparse left-look LU decomposition reads the subsystem register, it configures DMA to move data from main memory to SRAM connected to the memory controller. After receiving the notification signal that the DMA transfer is complete, the processor core starts reading, calculating, and writing the data back to SRAM. After the processor core completes the computation task, it configures DMA again. The DMA moves the calculated data from SRAM back to main memory. After receiving the signal that the DMA transfer is complete, the processor core sends an interrupt to the main CPU, indicating that the entire computation task has been completed.

5. A vectorized sparse left-look LU decomposition method for a RISC-V processor using the custom instruction GmacS for accelerating sparse left-look LU decomposition as described in any one of claims 1-2, characterized in that, The large number of cyclic scalar operations in the original sparse left-look LU decomposition algorithm are converted into a small number of vector operations, and GmacS is used to implement the vector aggregation loading, scalar-vector multiplication accumulation operation and vector scatter storage operation.

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