Control method, display device, and storage medium

Abstract

A control method, a display device and a storage medium, the control method is applied to a driving circuit of the display device, the driving circuit comprises a timing control module, the timing control module is used for outputting a clock signal, the clock signal comprises at least one set of adjacent first sub-clock signal and second sub-clock signal, and the method comprises the following steps: obtaining a waveform of the first sub-clock signal and a waveform of the second sub-clock signal; determining a first value based on the waveform of the first sub-clock signal and the waveform of the second sub-clock signal; determining a first preset value based on a first vertical resolution of the display device; determining an overload current based on the first value, the first preset value and the period length of one of the second sub-clock signals; and disconnecting the driving circuit when the signal current of the driving circuit is greater than or equal to the overload current, thereby improving the overcurrent protection degree of the display device with different refresh rates.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a control method, a display device, and a storage medium. Background Technology

[0002] Currently, monitors are widely popular among users. However, during use, if the current exceeds the monitor's capacity, it can lead to short circuits and burnout. Overcurrent protection measures can help protect monitors from damage caused by excessive current. In existing technology, overcurrent settings can only be configured with a single set of parameters for a single monitor, and cannot protect monitors with multiple refresh rates. Summary of the Invention

[0003] The purpose of this invention is to provide a control method, display device, and storage medium that improve the overcurrent protection for display devices with different refresh rates.

[0004] To achieve the objectives of this invention, the following technical solution is provided:

[0005] In a first aspect, the present invention provides a control method applied to a driving circuit of a display device. The driving circuit includes a timing control module for outputting a clock signal. The clock signal includes at least one set of adjacent first sub-clock signals and second sub-clock signals. The method includes: acquiring waveforms of the first sub-clock signal and the second sub-clock signal; determining a first value based on the waveforms of the first and second sub-clock signals; determining a first preset value based on a first vertical resolution of the display device; determining an overload current based on the first value, the first preset value, and the period length of one of the second sub-clock signals; and disconnecting the driving circuit when the signal current of the driving circuit is greater than or equal to the overload current.

[0006] It can be understood that the waveforms of the first sub-clock signal and the second sub-clock signal are acquired; a first value is determined based on the waveforms of the first and second sub-clock signals; a first preset value is determined based on the first vertical resolution of the display device; an overload current is determined based on the first value, the first preset value, and the period length of one of the second sub-clock signals; when the signal current of the driving circuit is greater than or equal to the overload current, the driving circuit is disconnected; the corresponding first vertical resolution is determined according to the display device with different refresh rates; the first preset value is determined based on the first vertical resolution of the display device; when the first value is equal to the first preset value, the overload current is determined based on the period length of the second sub-clock signal, thereby enabling overcurrent protection for display devices with different refresh rates.

[0007] In one possible example, determining the first value based on the waveforms of the first sub-clock signal and the second sub-clock signal includes: determining the degree of similarity between the waveforms of the first sub-clock signal and the second sub-clock signal; and determining the first value based on the degree of similarity.

[0008] It is understandable that the degree of similarity between the waveforms of the first sub-clock signal and the second sub-clock signal is determined; based on the degree of similarity, a first value is determined, which can detect the slight differences between the waveforms of the first sub-clock signal and the second sub-clock signal, thus improving the quantization accuracy.

[0009] In one possible example, determining the similarity between the waveforms of the first sub-clock signal and the second sub-clock signal includes: performing analog-to-digital conversion on the first sub-clock signal to obtain a first sequence; performing analog-to-digital conversion on the second sub-clock signal to obtain a second sequence; performing a Fast Fourier Transform on the first sequence and the second sequence with a preset number of points per frame; calculating the root mean square (RMS) value of the difference in spectral amplitude between the two frames of the transformed first sequence and the transformed second sequence; when the RMS value is less than a preset limit, the waveforms of the first sub-clock signal and the second sub-clock signal are the same; when the RMS value is greater than or equal to the preset limit, the waveforms of the first sub-clock signal and the second sub-clock signal are different.

[0010] The process involves: performing an analog-to-digital conversion on the first sub-clock signal to obtain the first sequence; performing an analog-to-digital conversion on the second sub-clock signal to obtain the second sequence; performing a Fast Fourier Transform (FFT) on the first and second sequences with a preset number of points per frame; calculating the root mean square (RMS) value of the difference in spectral amplitude between the two frames of the transformed first and second sequences; when the RMS value is less than a preset limit, the waveforms of the first and second sub-clock signals are the same; when the RMS value is greater than or equal to the preset limit, the waveforms of the first and second sub-clock signals are different. This comparison method is more robust to noise and jitter, reducing the false detection rate. Furthermore, the preset limit can be set according to requirements, facilitating adaptive adjustment for different panels or cables and improving versatility.

[0011] In one possible example, determining the first value based on the degree of similarity includes: when the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal, adding 1 to the first value, with the first value starting from 0; when the waveform of the first sub-clock signal is not the same as the waveform of the second sub-clock signal, clearing the first value to zero.

[0012] It is understandable that when the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal, the first value is incremented by 1, and the first value starts counting from 0; when the waveform of the first sub-clock signal is different from the waveform of the second sub-clock signal, the first value is cleared to zero. This method quantifies the number of consecutive identical waveforms. Once a waveform is different, it is immediately cleared to zero, which can prevent historical accumulation errors, ensure accurate counting, and improve the accuracy of calculating the first value.

[0013] In one possible example, determining the overload current based on the first value, the first preset value, and the period length of one of the second sub-clock signals includes: determining whether the first value is equal to the first preset value; when the timing control module outputs one of the second sub-clock signals, making the first value equal to the first preset value, stopping the counting of the first value and determining the overload current based on the period length of the one of the second sub-clock signals; and continuing to count the first value when the first value is less than the first preset value.

[0014] It is understandable that a precise start threshold is set for determining the overload current. When the first value does not reach the preset value, the counting continues to ensure the integrity of data acquisition and avoid detection deviations caused by insufficient data. Only when the first value meets the preset conditions is the overload current calculated based on the period length of one of the second sub-clock signals. This effectively eliminates interference factors in non-overload scenarios, significantly reduces the probability of misjudgment or missed judgment, ensures the reliability of current detection results, and improves the accuracy of determining the overload current.

[0015] In one possible example, stopping the counting of the first value and determining the overload current based on the period length of one of the second sub-clock signals includes: determining the overload current based on the period length of one of the second sub-clock signals and a preset relationship, wherein the preset relationship includes the period length of at least one second sub-clock signal and at least one overload current, and the period length of each second sub-clock signal corresponds one overload current.

[0016] It is understandable that the overload current is determined based on the period length of one of the second sub-clock signals and a preset relationship. The preset relationship includes the period length of at least one second sub-clock signal and at least one overload current. The period length of each second sub-clock signal corresponds one-to-one with an overload current, so that the period length is linked to the refresh rate. Using the period length as an index, the overload current can be quickly and accurately mapped, avoiding complex calculations and improving the accuracy and efficiency of determining the overload current.

[0017] In one possible example, determining the overload current based on the period length of one of the second sub-clock signals and a preset relationship includes: determining a first refresh rate based on the period length of one of the second sub-clock signals; the preset relationship includes a first sub-preset relationship, the first sub-preset relationship including at least one first refresh rate and at least one overload current, each first refresh rate being matched with one overload current; and determining the overload current based on the first refresh rate and the first sub-preset relationship.

[0018] It is understandable that the first refresh rate is determined based on the period length of one of the second sub-clock signals; the preset relationship includes a first sub-preset relationship, which includes at least one first refresh rate and at least one overload current, with each first refresh rate matched with an overload current; the overload current is determined based on the first refresh rate and the first sub-preset relationship, making the matching relationship between the first refresh rate and the overload current more intuitive, facilitating engineer debugging, and improving the accuracy and efficiency of determining the overload current.

[0019] In one possible example, determining the overload current based on the period length of one of the second sub-clock signals and a preset relationship further includes: generating the first sub-preset relationship in advance based on the overload current matching all the first refresh rates; and pre-storing the first sub-preset relationship.

[0020] It is understandable that the first sub-preset relationship is generated in advance based on the overload current matched by all first refresh rates; the first sub-preset relationship is stored in advance, and the pre-storage method ensures that the display device can call it when it is powered on, without the need for calibration every time. Moreover, the first sub-preset relationship between the first refresh rate and the overload current obtained by the actual measurement of the whole machine is more in line with the characteristics of the actual display device, and improves the accuracy of overcurrent protection.

[0021] In a second aspect, embodiments of this application provide a display device, including a memory and a processor, wherein the memory is used to store computer instructions, and the processor is used to invoke the computer instructions to perform a method as provided in the first aspect or any embodiment of the first aspect.

[0022] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program that causes a computer to execute the method provided in the first aspect or any embodiment of the first aspect. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram illustrating an application scenario of a control method according to one embodiment.

[0025] Figure 2 This is a flowchart illustrating a control method according to one embodiment;

[0026] Figure 3 This is a schematic diagram of the structure of a display device according to one embodiment;

[0027] Figure 4 This is a schematic diagram of a structure for processing a first preset relationship according to one embodiment;

[0028] Figure 5 This is a schematic diagram of the structure of the first sub-preset lookup table in one embodiment;

[0029] Figure 6 This is a schematic diagram of the structure of a display device according to one embodiment.

[0030] Explanation of reference numerals in the attached figures:

[0031] 101-User, 102-Display device, 103-Server, 300-Display device, 301-Acquisition module, 302-Processing module, 401-Flash memory module, 402-Timing control module, 403-Level conversion module, 601-Processor, 602-Memory. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] It should be noted that when a component is said to be "fixed" to another component, it can be directly on the other component or it can be in a middle component. When a component is said to be "connected" to another component, it can be directly connected to the other component or it may be in a middle component.

[0034] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used in this invention includes any and all combinations of one or more of the associated listed items.

[0035] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0036] Please see Figure 1 , Figure 1 This is a schematic diagram illustrating an application scenario of a control method according to one embodiment. For example... Figure 1 As shown in the diagram, this application scenario includes a user 101, a display device 102, and a server 103. Optionally, the display device 102 may be a thin-film transistor liquid crystal display (TFT-LCD), and this application does not limit the structure of the display device 102. Optionally, a user 101 may use multiple display devices 102. Optionally, multiple display devices 102 may transmit data with a single server 103.

[0037] Optionally, server 103 can be a standalone server or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms. Server 103 can also be implemented through a server cluster composed of multiple sub-servers.

[0038] It should be noted that, Figure 1 The number and form of each device in the system shown, as well as the number of users 101, are for illustrative purposes only and do not constitute a limitation on the embodiments of this application.

[0039] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating a control method according to one embodiment. The control method is applied to the driving circuit of a display device. The driving circuit includes a timing control module, which outputs a clock signal. The clock signal includes at least one set of adjacent first sub-clock signals and second sub-clock signals. The method includes the following steps S201-S205, wherein...

[0040] S201: Obtain the waveforms of the first sub-clock signal and the second sub-clock signal.

[0041] S202: Determine the first value based on the waveform of the first sub-clock signal and the waveform of the second sub-clock signal.

[0042] Determining a first value based on the waveforms of the first sub-clock signal and the second sub-clock signal includes: determining the degree of similarity between the waveforms of the first sub-clock signal and the second sub-clock signal; and determining the first value based on the degree of similarity.

[0043] Optionally, at least one set of adjacent first sub-clock signals and second sub-clock signals includes a first set of adjacent first sub-clock signals and second sub-clock signals, a second set of adjacent third sub-clock signals and fourth sub-clock signals, and a third set of adjacent fifth sub-clock signals and sixth sub-clock signals, wherein the second sub-clock signal is also adjacent to the third sub-clock signal, and the fourth sub-clock signal is also adjacent to the fifth sub-clock signal. The above is an example and should not be construed as a limitation.

[0044] Optionally, a first analog-to-digital converter and a second analog-to-digital converter are set inside the timing control module to synchronously sample the first sub-clock signal and the second sub-clock signal, respectively. Synchronous sampling eliminates the comparison error caused by clock offset.

[0045] Optionally, the rising edge time difference Δt1 of the first sub-clock signal and the second sub-clock signal is calculated, the falling edge time difference Δt2 of the first sub-clock signal and the second sub-clock signal is calculated, and the duty cycle difference ΔD of the first sub-clock signal and the second sub-clock signal is calculated. When Δt1 is less than a preset first limit value, Δt2 is less than a preset second limit value, and ΔD is less than a preset third limit value, it is determined that the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal; otherwise, the waveform of the first sub-clock signal is different from the waveform of the second sub-clock signal.

[0046] It is understandable that the degree of similarity between the waveforms of the first sub-clock signal and the second sub-clock signal is determined; based on the degree of similarity, a first value is determined, which can detect the slight differences between the waveforms of the first sub-clock signal and the second sub-clock signal, thus improving the quantization accuracy.

[0047] Determining the similarity between the waveforms of the first sub-clock signal and the second sub-clock signal includes: performing analog-to-digital conversion on the first sub-clock signal to obtain a first sequence; performing analog-to-digital conversion on the second sub-clock signal to obtain a second sequence; performing a Fast Fourier Transform on the first and second sequences with a preset number of points per frame; calculating the root mean square (RMS) value of the difference in spectral amplitude between the two frames of the transformed first and second sequences; when the RMS value is less than a preset limit, the waveforms of the first and second sub-clock signals are the same; when the RMS value is greater than or equal to the preset limit, the waveforms of the first and second sub-clock signals are different.

[0048] Optionally, the driving circuit includes a Fast Fourier Transform (FFT) processor. A first analog-to-digital converter samples the first sub-clock signal to generate a first digital sequence, and a second analog-to-digital converter samples the second sub-clock signal to generate a second digital sequence. The first and second digital sequences are divided into frames according to a preset number of points (e.g., 1024 points per frame) and sent to the FFT processor. A FFT is performed on each frame of data. Then, the root mean square value of the spectral amplitude difference between corresponding frames of the two signals is calculated.

[0049] The process involves: performing an analog-to-digital conversion on the first sub-clock signal to obtain the first sequence; performing an analog-to-digital conversion on the second sub-clock signal to obtain the second sequence; performing a Fast Fourier Transform (FFT) on the first and second sequences with a preset number of points per frame; calculating the root mean square (RMS) value of the difference in spectral amplitude between the two frames of the transformed first and second sequences; when the RMS value is less than a preset limit, the waveforms of the first and second sub-clock signals are the same; when the RMS value is greater than or equal to the preset limit, the waveforms of the first and second sub-clock signals are different. This comparison method is more robust to noise and jitter, reducing the false detection rate. Furthermore, the preset limit can be set according to requirements, facilitating adaptive adjustment for different panels or cables and improving versatility.

[0050] The first value is determined based on the degree of similarity, including: when the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal, the first value is incremented by 1, and the first value starts counting from 0; when the waveform of the first sub-clock signal is different from the waveform of the second sub-clock signal, the first value is cleared to zero.

[0051] Optionally, the driving circuit includes a counter. First, the counter is initialized: when it starts, the first value N = 0. When the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal, N = N + 1 is executed; when the waveform of the first sub-clock signal is different from the waveform of the second sub-clock signal, N = 0.

[0052] It is understandable that when the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal, the first value is incremented by 1, and the first value starts counting from 0; when the waveform of the first sub-clock signal is different from the waveform of the second sub-clock signal, the first value is cleared to zero. This method quantifies the number of consecutive identical waveforms. Once a waveform is different, it is immediately cleared to zero, which can prevent historical accumulation errors, ensure accurate counting, and improve the accuracy of calculating the first value.

[0053] S203: Determine a first preset value based on the first vertical resolution of the display device.

[0054] S204: Determine the overload current based on the first value, the first preset value, and the period length of one of the second sub-clock signals.

[0055] In one possible example, determining the overload current based on a first value, a first preset value, and the period length of one of the second sub-clock signals includes: determining whether the first value is equal to the first preset value; when the timing control module outputs one of the second sub-clock signals, making the first value equal to the first preset value, stopping the counting of the first value and determining the overload current based on the period length of one of the second sub-clock signals; and continuing to count the first value when the first value is less than the first preset value.

[0056] Optionally, the clock signal includes a first sub-clock signal, a second sub-clock signal, and a third sub-clock signal that are sequentially adjacent. When the timing control module outputs the third sub-clock signal so that the first value is equal to the first preset value, the third sub-clock signal is regarded as one of the second sub-clock signals, the counting of the first value is stopped, and the overload current is determined based on the period length of the third sub-clock signal.

[0057] Optionally, the first sub-clock signal can be regarded as the nth sub-clock signal, and the second sub-clock signal can be regarded as the (n+1)th sub-clock signal, where the value of n is from 1 to any positive integer.

[0058] It is understandable that a precise start threshold is set for determining the overload current. When the first value does not reach the preset value, counting continues to ensure the integrity of data acquisition and avoid detection deviations caused by insufficient data. Only when the first value meets the preset conditions is the overload current calculated based on the period length of one of the second sub-clock signals when the first value reaches the preset value. This effectively eliminates interference factors in non-overload scenarios, significantly reduces the probability of misjudgment or missed judgment, ensures the reliability of current detection results, and improves the accuracy of determining the overload current.

[0059] Stopping the counting of the first value and determining the overload current based on the period length of the second sub-clock signal includes: determining the overload current based on the period length of the second sub-clock signal and a preset relationship, wherein the preset relationship includes the period length of at least one second sub-clock signal and at least one overload current, and the period length of each second sub-clock signal corresponds one-to-one with an overload current.

[0060] Optionally, when the first value is equal to the first preset value, the period length of the second sub-clock signal under this condition is obtained, and based on the period length of the second sub-clock signal under this condition, the overload current of the period length of the second sub-clock signal is adjusted to generate a preset relationship.

[0061] Optionally, at least one set of adjacent first sub-clock signals and second sub-clock signals includes a first set of adjacent first sub-clock signals and second sub-clock signals, a second set of adjacent third sub-clock signals and fourth sub-clock signals, and a third set of adjacent fifth sub-clock signals and sixth sub-clock signals. The second sub-clock signal is also adjacent to the third sub-clock signal, and the fourth sub-clock signal is also adjacent to the fifth sub-clock signal. When the sixth sub-clock signal is output and the first value is equal to the first preset value, the period length of the sixth sub-clock signal is taken as the period length of the second sub-clock signal as defined above. The overload current is then determined based on the period length of the sixth sub-clock signal and the preset relationship.

[0062] Optionally, when the first value is equal to the first preset value, the period length, total horizontal pixels, and total vertical pixels of the second sub-clock signal are obtained, and the first refresh rate is determined based on the period length, total horizontal pixels, and total vertical pixels of the second sub-clock signal. Each first refresh rate corresponds to a unique overload current, thus forming a mapping relationship between the period length of the second sub-clock signal and the overload current.

[0063] It is understandable that determining the overload current based on the period length of the second sub-clock signal includes: determining the overload current based on the period length of the second sub-clock signal and a preset relationship. The preset relationship includes the period length of at least one second sub-clock signal and at least one overload current. The period length of each second sub-clock signal corresponds one-to-one with an overload current, so that the period length is linked to the refresh rate. Using the period length as an index, the overload current can be quickly and accurately mapped, avoiding complex calculations and improving the accuracy and efficiency of determining the overload current.

[0064] Stopping the counting of a first value and determining an overload current based on the period length of one of the second sub-clock signals includes: determining a first refresh rate based on the period length of one of the second sub-clock signals; a preset relationship including a first sub-preset relationship, the first sub-preset relationship including at least one first refresh rate and at least one overload current, each first refresh rate being matched with an overload current; and determining the overload current based on the first refresh rate and the first sub-preset relationship.

[0065] It should be noted that when the timing control module detects and calculates the CLK period and sets parameters corresponding to multiple refresh rate ranges (refresh rate corresponds one-to-one with refresh rate range parameters, and refresh rate range parameters correspond one-to-one with overload current), the CLK integrated on the array substrate's gate driver is output through a level converter. The level converter receives the CLK from the timing control module and then generates CLK1, CLK2, CLK3, etc. The CLK period inside the timing control module corresponds to the time of each H (the falling edge of the Tp signal corresponds to the current row source output, so the time from the falling edge of Tp to the next falling edge of Tp, which is one cycle of the Tp signal, also corresponds to one H time. The refresh rate can also be determined by detecting the Tp period), which is the phase difference between CLK1 and CLK2. Taking a conventional 60Hz display as an example, its H*V=4400*2250, so the time of one H is H=1 / 60 / 2250, where 60 is the refresh rate, and the width of H corresponds to the refresh rate. Then, the corresponding refresh rate range parameter is queried.

[0066] Based on the above scheme, the refresh rate can be determined by detecting different signals, and then the corresponding parameters for the refresh rate range can be set. However, in practical applications, taking a 50-inch 1G1 D UD product as an example, the current in-plane design is 10CLK, our typ is 144Hz, and HSR is 288Hz. HSR is under the condition that the data volume remains unchanged (transmission rate = 4400*2250*144*3*8*1.03 / 12). Since the scanning signal is output through a level converter chip, and the level converter only supports 4 / 6 / 8 channel output, while the requirement is 10CLK, a cascaded scheme of two level converter chips (first level converter chip and second level converter chip) is adopted and set to 6 channels. Depending on the situation, a cascaded scheme of multiple level converter chips can be used. The first level converter chip outputs channels 1, 3, 5, 7, 9, and 11, and the second level converter chip outputs channels 2, 4, 6, 8, 10, and 12. This scheme has a total of 12 CLKs, cycling through each other. However, the 11th and 12th CLKs are redundant and not actually used. This prevents the 10th CLK and the 1st CLK of the next cycle from forming a continuous waveform, failing to meet the charging requirements; the 10th and 1st CLKs are invalid. Therefore, the CLKs corresponding to the 11th and 12th CLKs can be edited individually. For a single level converter chip, this means hiding the 6th or multiples of 6 CLK_IN waveforms (the input signal output from the timing control module to the LS IC) between the 5th CLK_IN and the next 1st CLK_IN. Only 10 of the 12 CLKs are valid, and the CLK periods are not uniform. Therefore, judging solely by the CLK period cannot guarantee absolutely accurate detection.

[0067] Optionally, the first sub-preset relationship can be a first sub-preset lookup table, which displays the matching relationship between the first refresh rate and the overload current.

[0068] It is understandable that the first refresh rate is determined based on the period length of the second sub-clock signal; the preset relationship includes a first sub-preset relationship, which includes at least one first refresh rate and at least one overload current, with each first refresh rate matched with an overload current; the overload current is determined based on the first refresh rate and the first sub-preset relationship, making the matching relationship between the first refresh rate and the overload current more intuitive, facilitating engineer debugging, and improving the accuracy and efficiency of determining the overload current.

[0069] The overload current is determined based on the period length of one of the second sub-clock signals and a preset relationship, and the method further includes: pre-tuning the overload current to match all first refresh rates, generating a first sub-preset relationship; and pre-storing the first sub-preset relationship.

[0070] Optionally, when the first value is equal to the first preset value, the period length of the second sub-clock signal under this condition is obtained, the first refresh rate is calculated based on the period length of the second sub-clock signal under this condition, the overload current under the first refresh rate is adjusted, all overload currents of the display panel are tested under different first refresh rates, the first sub-preset relationship is generated and stored in the display device.

[0071] Optionally, the display device can be pre-calibrated using a programmable power supply and an oscilloscope, setting different first refresh rates, for example, traversing from 24Hz to 240Hz, and measuring the overload current corresponding to the changed first refresh rate in 5Hz increments.

[0072] Optionally, the overcurrent protection detection of the display device includes a rest time and a detection time. When the signal current reaches the overload current we set, and the time is greater than or equal to the detection time, we will count once. When the count reaches our detection count, overcurrent protection will be activated.

[0073] Optionally, taking a 120Hz display device as an example, the common 1920H×1200V (H×V represents the number of horizontal and vertical pixels of the resolution, i.e., horizontal resolution × vertical resolution) means that the display has 1920 horizontal pixels and 1200 vertical pixels. Our H*V total is 4400*2250, so our time T1 for one row is: T1=1 / 120 / 2250=3.7us. The sum of the rest time and the detection time cannot exceed 3.7us.

[0074] It is understandable that the first sub-preset relationship is generated in advance based on the overload current matched by all first refresh rates; the first sub-preset relationship is stored in advance, and the pre-storage method ensures that the display device can call it when it is powered on, without the need for calibration every time. Moreover, the first sub-preset relationship between the first refresh rate and the overload current obtained by the actual measurement of the whole machine is more in line with the characteristics of the actual display device, and improves the accuracy of overcurrent protection.

[0075] Optionally, determining a first preset value based on the first vertical resolution of the display device includes:

[0076] When the first vertical resolution switches to the second vertical resolution within a preset time period, the first preset value is determined based on the second vertical resolution.

[0077] When the first vertical resolution switches to the second vertical resolution outside the preset time period, the first preset value is determined based on the first vertical resolution.

[0078] It is understandable that introducing a preset duration avoids erroneous switching caused by transient jitter and improves the accuracy and stability of determining the first preset value.

[0079] S205: When the signal current of the drive circuit is greater than or equal to the overload current, disconnect the drive circuit.

[0080] Optionally, when the signal current of the drive circuit is greater than or equal to the overload current, a disconnect signal is sent to the timing control module to immediately freeze the frame buffer data. Then, the black screen protection mode is activated (all pixels are reset to zero) and an error code is displayed to prevent screen distortion or ghosting when the drive circuit is disconnected, thereby reducing power consumption. The error code improves user operability.

[0081] It can be understood that the waveforms of the first sub-clock signal and the second sub-clock signal are acquired; a first value is determined based on the waveforms of the first and second sub-clock signals; a first preset value is determined based on the first vertical resolution of the display device; when the first value equals the first preset value, the overload current is determined based on the period length of the second sub-clock signal; when the signal current of the driving circuit is greater than or equal to the overload current, the driving circuit is disconnected; the corresponding first vertical resolution is determined according to the display device with different refresh rates; the first preset value is determined based on the first vertical resolution of the display device; when the first value equals the first preset value, the overload current is determined based on the period length of the second sub-clock signal, thereby enabling overcurrent protection for display devices with different refresh rates.

[0082] It should be noted that overcurrent protection measures prevent drive circuits or display devices from being damaged by excessive current. When the signal current of the drive circuit is greater than or equal to the overload current, exceeding the withstand capacity of the drive circuit or display device, it may cause safety problems such as arcing, overheating, and fire. Overcurrent protection promptly cuts off the excessive current to prevent potential dangers. When excessive current occurs in the drive circuit, it may cause a drop in power supply voltage, thereby affecting the normal operation of the entire power system. Overcurrent protection can quickly cut off the excessive current, maintain stable circuit operation, and ensure an interference-free power supply.

[0083] Please see Figure 3 , Figure 3 This is a schematic diagram of a display device according to one embodiment. Based on the above system architecture, the display device 300 can be a server or a device, or a module within a server. The display device 300 includes at least: an acquisition module 301 and a processing module 302, wherein...

[0084] The acquisition module 301 is used to acquire the waveforms of the first sub-clock signal and the second sub-clock signal.

[0085] Processing module 302 is used to determine a first value based on the waveform of the first sub-clock signal and the waveform of the second sub-clock signal; processing module 302 is used to determine a first preset value based on the first vertical resolution of the display device; processing module 302 is used to determine the overload current based on the first value, the first preset value, and the period length of one of the second sub-clock signals; when the signal current of the drive circuit is greater than or equal to the overload current, processing module 302 is used to disconnect the drive circuit.

[0086] In one possible example, processing module 302 is used to process the following steps:

[0087] Determine the degree of similarity between the waveforms of the first sub-clock signal and the waveforms of the second sub-clock signal;

[0088] The first value is determined based on the degree of similarity.

[0089] In one possible example, processing module 302 is used to process the following steps:

[0090] The first sub-clock signal is converted from analog to digital to obtain the first sequence;

[0091] The second sub-clock signal is converted from analog to digital to obtain the second sequence;

[0092] Perform a Fast Fourier Transform on the first and second sequences, with a preset number of points per frame;

[0093] Calculate the root mean square value of the spectral amplitude difference between the two frames of the transformed first sequence and the transformed second sequence;

[0094] When the root mean square value is less than a preset limit, the waveforms of the first sub-clock signal and the second sub-clock signal are the same; when the root mean square value is greater than or equal to the preset limit, the waveforms of the first sub-clock signal and the second sub-clock signal are different.

[0095] In one possible example, processing module 302 is used to process the following steps:

[0096] When the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal, the first value is incremented by 1, and the first value starts counting from 0.

[0097] When the waveform of the first sub-clock signal is different from that of the second sub-clock signal, the first value is cleared to zero.

[0098] In one possible example, processing module 302 is used to process the following steps:

[0099] Determine whether the first value is equal to the first preset value;

[0100] When the timing control module outputs one of the second sub-clock signals, making the first value equal to the first preset value, it stops counting the first value and determines the overload current based on the period length of one of the second sub-clock signals;

[0101] When the first value is less than the first preset value, the counting of the first value continues.

[0102] In one possible example, processing module 302 is used to process the following steps:

[0103] The overload current is determined based on the period length of one of the second sub-clock signals and a preset relationship. The preset relationship includes the period length of at least one second sub-clock signal and at least one overload current, with each period length of the second sub-clock signal corresponding to an overload current.

[0104] In one possible example, processing module 302 is used to process the following steps:

[0105] The first refresh rate is determined based on the period length of one of the second sub-clock signals;

[0106] The preset relationship includes a first sub-preset relationship, which includes at least one first refresh rate and at least one overload current, with each first refresh rate matched with an overload current.

[0107] The overload current is determined based on the first refresh rate and the first sub-preset relationship.

[0108] In one possible example, processing module 302 is used to process the following steps:

[0109] The first sub-preset relationship is generated by pre-tuning the overload current to match all first refresh rates;

[0110] The first child preset relationship is stored in advance.

[0111] Please see Figure 4 , Figure 4 This is a schematic diagram illustrating the structure for processing a first preset relationship according to one embodiment. For example... Figure 4 As shown, the display device 300 includes a flash memory module 401, a timing control module 402, and a level conversion module 403. The flash memory module 401 is electrically connected to the timing control module 402, and the level conversion module 403 is electrically connected to the timing control module 402. The timing control module 402 searches for a first preset relationship in the flash memory module 401, the flash memory module 401 loads the first preset relationship into the timing control module 402, and the timing control module 402 burns the first preset relationship into the level conversion module 403.

[0112] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of the first sub-preset lookup table in one embodiment. For example... Figure 5 As shown, the first sub-preset lookup table displays the matching relationship between the first refresh rate and the overload current. The first refresh rate corresponds one-to-one with the parameters of the refresh rate range, and the parameters of the refresh rate range correspond one-to-one with the overload current. This allows us to obtain the matching relationship between the first refresh rate and the overload current. For example, the first refresh rate can be 40Hz, 50Hz, and 60Hz, etc., and the overload current can be C1, C2, and C3, etc. 40Hz to 50Hz corresponds to C1, 50Hz to 60Hz corresponds to C2, 60Hz to 70Hz corresponds to C3, 70Hz to 80Hz corresponds to C4, and 80Hz to 90Hz corresponds to C5.

[0113] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a display device according to one embodiment. Figure 6 As shown, the display device 102 includes a processor 601 and a memory 602. The memory 602 is used to store computer instructions, and the processor 601 is used to invoke the computer instructions to execute the following steps:

[0114] Obtain the waveforms of the first sub-clock signal and the second sub-clock signal;

[0115] The first value is determined based on the waveforms of the first sub-clock signal and the second sub-clock signal;

[0116] A first preset value is determined based on the first vertical resolution of the display device;

[0117] The overload current is determined based on a first value, a first preset value, and the period length of one of the second sub-clock signals;

[0118] When the signal current of the drive circuit is greater than or equal to the overload current, the drive circuit will be disconnected.

[0119] In one possible example, processor 601 is specifically used to execute the following instructions:

[0120] Determine the degree of similarity between the waveforms of the first sub-clock signal and the waveforms of the second sub-clock signal;

[0121] The first value is determined based on the degree of similarity.

[0122] In one possible example, processor 601 is specifically used to execute the following instructions:

[0123] The first sub-clock signal is converted from analog to digital to obtain the first sequence;

[0124] The second sub-clock signal is converted from analog to digital to obtain the second sequence;

[0125] Perform a Fast Fourier Transform on the first and second sequences, with a preset number of points per frame;

[0126] Calculate the root mean square value of the spectral amplitude difference between the two frames of the transformed first sequence and the transformed second sequence;

[0127] When the root mean square value is less than a preset limit, the waveforms of the first sub-clock signal and the second sub-clock signal are the same; when the root mean square value is greater than or equal to the preset limit, the waveforms of the first sub-clock signal and the second sub-clock signal are different.

[0128] In one possible example, processor 601 is specifically used to execute the following instructions:

[0129] When the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal, the first value is incremented by 1, and the first value starts counting from 0.

[0130] When the waveform of the first sub-clock signal is different from that of the second sub-clock signal, the first value is cleared to zero.

[0131] In one possible example, processor 601 is specifically used to execute the following instructions:

[0132] Determine whether the first value is equal to the first preset value;

[0133] When the timing control module outputs one of the second sub-clock signals, making the first value equal to the first preset value, it stops counting the first value and determines the overload current based on the period length of one of the second sub-clock signals;

[0134] When the first value is less than the first preset value, the counting of the first value continues.

[0135] In one possible example, processor 601 is specifically used to execute the following instructions:

[0136] The overload current is determined based on the period length of one of the second sub-clock signals and a preset relationship. The preset relationship includes the period length of at least one second sub-clock signal and at least one overload current, with each period length of the second sub-clock signal corresponding to an overload current.

[0137] In one possible example, processor 601 is specifically used to execute the following instructions:

[0138] The first refresh rate is determined based on the period length of one of the second sub-clock signals;

[0139] The preset relationship includes a first sub-preset relationship, which includes at least one first refresh rate and at least one overload current, with each first refresh rate matched with an overload current.

[0140] The overload current is determined based on the first refresh rate and the first sub-preset relationship.

[0141] In one possible example, processor 601 is specifically used to execute the following instructions:

[0142] The first sub-preset relationship is generated by pre-tuning the overload current to match all first refresh rates;

[0143] The first child preset relationship is stored in advance.

[0144] Those skilled in the art will understand that, for ease of explanation, Figure 6 Only one memory 602 and processor 601 are shown in the illustration. In a real terminal or server, multiple processors 601 and memory 602 may exist. The memory 602 may also be referred to as a storage medium or storage device, etc., and this application embodiment does not impose any limitations on this.

[0145] It should be understood that in this application, the processor 601 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 601 may also employ a general-purpose microprocessor, graphics processing unit (GPU), or one or more integrated circuits to execute relevant programs to achieve the functions required by the embodiments of this application.

[0146] Processor 601 can also be an integrated circuit chip with signal processing capabilities. In implementation, each step of this application can be completed by the integrated logic circuitry in the hardware of processor 601 or by instructions in software form. The processor 601 described above can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The steps of the methods disclosed in the embodiments of this application can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory 602. Processor 601 reads the information in memory 602 and, in conjunction with its hardware, completes the functions required by the units included in the methods, apparatus, and storage media of the embodiments of this application.

[0147] It should also be understood that the memory 602 mentioned in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). The memory can also be, but is not limited to, Compact Disc Read-Only Memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, digital universal discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer. The memory can be independent and connected to the processor via a bus. The memory 602 can also be integrated with the processor 601. The memory 602 can store programs. When the program stored in the memory is executed by the processor 601, the processor 601 is used to execute the various steps of the determination method in the above embodiments of this application.

[0148] It should be noted that when the processor 601 is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory 602 (memory module) is integrated into the processor. It should be noted that the memory 602 described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0149] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0150] In implementation, each step of the above method can be completed by the integrated logic circuitry of the hardware in processor 601 or by instructions in software form. The steps of the method disclosed in the embodiments of this application can be directly implemented by the hardware processor, or by a combination of hardware and software modules in processor 601. The software modules can be located in mature storage media in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 602. The processor reads the information in memory 602 and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, these will not be described in detail here.

[0151] Those skilled in the art will recognize that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0152] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer-programmed program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on processor 601, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic) or wireless (e.g., infrared, wireless, microwave, etc.) means, or from one website, computer, server, or data center to a mobile phone processor via a wired means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0153] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A control method, characterized in that, The control method is applied to a driving circuit of a display device. The driving circuit includes a timing control module, which outputs a clock signal. The clock signal includes at least one set of adjacent first sub-clock signals and second sub-clock signals. The method includes: Obtain the waveforms of the first sub-clock signal and the second sub-clock signal; The first value is determined based on the waveforms of the first sub-clock signal and the second sub-clock signal; A first preset value is determined based on the first vertical resolution of the display device; The overload current is determined based on the first value, the first preset value, and the period length of one of the second sub-clock signals; When the signal current of the drive circuit is greater than or equal to the overload current, the drive circuit is disconnected.

2. The control method according to claim 1, characterized in that, Determining the first value based on the waveforms of the first sub-clock signal and the second sub-clock signal includes: Determine the degree of similarity between the waveform of the first sub-clock signal and the waveform of the second sub-clock signal; The first value is determined based on the degree of similarity.

3. The control method according to claim 2, characterized in that, The determination of the similarity between the waveform of the first sub-clock signal and the waveform of the second sub-clock signal includes: The first sub-clock signal is converted from analog to digital to obtain the first sequence; The second sub-clock signal is converted from analog to digital to obtain the second sequence; Perform a Fast Fourier Transform on the first sequence and the second sequence, with a preset number of points per frame; Calculate the root mean square value of the spectral amplitude difference between the two frames of the transformed first sequence and the transformed second sequence; When the root mean square value is less than a preset limit, the waveforms of the first sub-clock signal and the second sub-clock signal are the same; when the root mean square value is greater than or equal to the preset limit, the waveforms of the first sub-clock signal and the second sub-clock signal are different.

4. The control method according to claim 2, characterized in that, Determining the first value based on the degree of similarity includes: When the waveform of the first sub-clock signal is the same as the waveform of the second sub-clock signal, the first value is incremented by 1, and the first value starts counting from 0. When the waveform of the first sub-clock signal is different from the waveform of the second sub-clock signal, the first value is cleared to zero.

5. The control method according to claim 4, characterized in that, The determination of overload current based on the first value, the first preset value, and the period length of one of the second sub-clock signals includes: Determine whether the first value is equal to the first preset value; When the timing control module outputs one of the second sub-clock signals, making the first value equal to the first preset value, it stops counting the first value and determines the overload current based on the period length of one of the second sub-clock signals. When the first value is less than the first preset value, the counting of the first value continues.

6. The control method according to claim 5, characterized in that, The step of stopping the counting of the first value and determining the overload current based on the period length of one of the second sub-clock signals includes: The overload current is determined based on the period length of one of the second sub-clock signals and a preset relationship, wherein the preset relationship includes the period length of at least one second sub-clock signal and at least one overload current, and the period length of each second sub-clock signal corresponds one overload current.

7. The control method according to claim 6, characterized in that, The determination of overload current based on the period length of one of the second sub-clock signals and a preset relationship includes: The first refresh rate is determined based on the period length of one of the second sub-clock signals; The preset relationship includes a first sub-preset relationship, which includes at least one first refresh rate and at least one overload current, with each first refresh rate matched with one overload current. The overload current is determined based on the first refresh rate and the first sub-preset relationship.

8. The control method according to claim 7, characterized in that, The determination of overload current based on the period length of one of the second sub-clock signals and a preset relationship further includes: The first sub-preset relationship is generated in advance based on the overload current that matches all the first refresh rates; The first sub-preset relationship is stored in advance.

9. A display device, characterized in that, It includes a memory and a processor, wherein the memory is used to store computer instructions, and the processor is used to invoke the computer instructions to perform the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that causes a computer to perform the method according to any one of claims 1 to 7.

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