Voltage regulating device and driving device

Abstract

The application discloses a voltage regulating device and driving device, which determines OLED pixel area power supply voltage, power supply voltage reference value, first reference voltage and second reference voltage through an input unit; determines voltage variation through a calculation unit; sets threshold voltage range through a detection unit, when the voltage variation is within the threshold voltage range, the output first reference voltage and second reference voltage are unregulated voltage, when the voltage variation is not within the threshold voltage range, the output first target reference voltage and second target reference voltage are regulated voltage through the voltage variation. The application can reduce the frequency of the first reference voltage and the second reference voltage changing with the fluctuation of the OLED pixel area power supply voltage, thereby reducing the frequency of the difference between the OLED pixel area power supply voltage and the data voltage changing, further reducing the frequency of the pixel current changing with the fluctuation of the OLED pixel area power supply voltage, reducing screen flicker and improving display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a voltage regulation device and a driving device. Background Technology

[0002] OLED (Organic Light Emitting Diode) is a current-injection type device whose luminous intensity is directly proportional to the pixel current, and it is widely used in the display technology field. Specifically, the difference between the power supply voltage and the data voltage in the OLED pixel area determines the pixel current, and the data voltage is related to the magnitudes of a first reference voltage and a second reference voltage.

[0003] The relevant technologies only perform simple detection of the change in the power supply voltage of the OLED pixel area. When the power supply voltage of the OLED pixel area changes frequently, the first reference voltage and the second reference voltage also change frequently with the power supply voltage of the OLED pixel area, causing the difference between the power supply voltage and the data voltage of the OLED pixel area to change frequently. In turn, the pixel current changes frequently with the fluctuation of the power supply voltage of the OLED pixel area, causing screen flicker and affecting the display effect. Summary of the Invention

[0004] This invention provides a voltage regulation device and a driving device to solve the problem in the prior art that when the power supply voltage of the OLED pixel area changes frequently, it causes screen flickering and affects the display effect.

[0005] In a first aspect, embodiments of the present invention provide a voltage regulation device, comprising: an input unit, a calculation unit, a detection unit, and an output unit;

[0006] The input unit, the calculation unit, and the output unit are connected in sequence. The input unit is also connected to the output unit, and the detection unit is also connected to both the calculation unit and the output unit.

[0007] The input unit is used to acquire the power supply voltage of the OLED pixel area in real time, and to amplify the received initial reference voltage to obtain the power supply voltage reference value, the first reference voltage, and the second reference voltage.

[0008] The calculation unit is used to determine the voltage change based on the power supply voltage reference value and the power supply voltage of the OLED pixel area.

[0009] The detection unit is used to output a first control signal and a second control signal based on whether the voltage change is within the threshold voltage range.

[0010] The output unit is configured to adjust the first reference voltage and the second reference voltage according to the voltage change to obtain a first target reference voltage and a second target reference voltage; and under the control of the first control signal and the second control signal, output the first reference voltage and the second reference voltage, or output the first target reference voltage and the second target reference voltage.

[0011] In one optional embodiment, the input unit includes a data acquisition module, a first reference voltage generation module, a second reference voltage generation module, and a power supply voltage reference value generation module;

[0012] The acquisition module is used to acquire the power supply voltage of the OLED pixel area in real time;

[0013] The first reference voltage generation module is used to amplify the initial reference voltage based on a first amplification factor and then perform buffering to obtain the first reference voltage.

[0014] The second reference voltage generation module is used to amplify the initial reference voltage based on the second amplification factor, and then perform voltage division and buffering to obtain the second reference voltage.

[0015] The power supply voltage reference value generation module is used to amplify the initial reference voltage based on the third amplification factor and then perform buffering to obtain the power supply voltage reference value.

[0016] In one optional embodiment, the acquisition module includes a first unity-gain buffer;

[0017] The non-inverting input of the first unity-gain buffer is electrically connected to the voltage sampling terminal of the OLED, and the inverting input of the first unity-gain buffer is electrically connected to the output terminal of the first unity-gain buffer, for outputting the power supply voltage of the OLED pixel area;

[0018] The first reference voltage generation module includes a first operational amplifier, a second unity-gain buffer, a first resistor, and a second resistor;

[0019] The non-inverting input terminal of the first operational amplifier is used to input the initial reference voltage, the inverting input terminal of the first operational amplifier is electrically connected to the second terminal of the first resistor and the first terminal of the second resistor, and the output terminal of the first operational amplifier is electrically connected to the first terminal of the first resistor and the non-inverting input terminal of the second unity-gain buffer.

[0020] The second terminal of the second resistor is grounded;

[0021] The inverting input terminal and the output terminal of the second unity-gain buffer are electrically connected to output the first reference voltage;

[0022] The second reference voltage generation module includes a second operational amplifier, a third unity-gain buffer, a third resistor, a fourth resistor, and a first variable resistor;

[0023] The non-inverting input terminal of the second operational amplifier is used to input the initial reference voltage, the inverting input terminal of the second operational amplifier is electrically connected to the second terminal of the third resistor and the first terminal of the fourth resistor, and the output terminal of the second operational amplifier is electrically connected to the first terminal of the third resistor and the first terminal of the first variable resistor.

[0024] The second terminal of the fourth resistor is grounded;

[0025] The second terminal of the first rheostat is grounded;

[0026] The non-inverting input terminal of the third unity-gain buffer is electrically connected to the third terminal of the first variable resistor, and the inverting input terminal of the third unity-gain buffer is electrically connected to the output terminal of the third unity-gain buffer, for outputting the second reference voltage;

[0027] The power supply voltage reference value generation module includes a third operational amplifier, a fourth unity-gain buffer, a fifth resistor, and a sixth resistor;

[0028] The non-inverting input terminal of the third operational amplifier is used to input the initial reference voltage. The inverting input terminal of the third operational amplifier is electrically connected to the second terminal of the fifth resistor and the first terminal of the sixth resistor. The output terminal of the third operational amplifier is electrically connected to the first terminal of the fifth resistor and the non-inverting input terminal of the fourth unity-gain buffer.

[0029] The second terminal of the sixth resistor is grounded;

[0030] The inverting input terminal of the fourth unity-gain buffer and the output terminal of the fourth gain buffer are electrically connected to output the power supply voltage reference value.

[0031] In one optional embodiment, the first reference voltage generation module further includes a second rheostat;

[0032] The first end of the second rheostat is electrically connected to the second end of the first resistor, the second end of the second rheostat is electrically connected to the first end of the second resistor, and the third end of the second rheostat is electrically connected to the inverting input terminal of the first operational amplifier.

[0033] The second reference voltage generation module also includes a third rheostat;

[0034] The first terminal of the third rheostat is electrically connected to the second terminal of the third resistor, the second terminal of the third rheostat is electrically connected to the first terminal of the fourth resistor, and the third terminal of the third rheostat is electrically connected to the inverting input terminal of the second operational amplifier.

[0035] The power supply voltage reference value generation module also includes a fourth rheostat;

[0036] The first terminal of the fourth rheostat is electrically connected to the second terminal of the fifth resistor, the second terminal of the fourth rheostat is electrically connected to the first terminal of the sixth resistor, and the third terminal of the fourth rheostat is electrically connected to the inverting input terminal of the third operational amplifier.

[0037] In one alternative embodiment, the computing unit includes a fifth operational amplifier, a seventh resistor, and an eighth resistor;

[0038] The inverting input of the fifth operational amplifier is electrically connected to the seventh resistor and is used to input the power supply voltage of the OLED pixel area. The non-inverting input of the fifth operational amplifier is electrically connected to the eighth resistor and is used to input the power supply voltage reference value. The output of the fifth operational amplifier is used to output the voltage change.

[0039] In one optional embodiment, the detection unit includes a first comparator, a second comparator, an OR gate, and a NOT gate;

[0040] The non-inverting input of the first comparator is used to input the voltage change, the inverting input of the first comparator is electrically connected to the fourth terminal of the first rheostat, and the output of the first comparator is electrically connected to the first receiving terminal of the OR gate.

[0041] The inverting input of the second comparator is used to input the voltage change, the non-inverting input of the second comparator is electrically connected to the fifth terminal of the first rheostat, and the output of the second comparator is electrically connected to the second receiving terminal of the OR gate.

[0042] The output of the OR gate is electrically connected to the input of the NOT gate, and is used to output a first control signal. The NOT gate is used to output a second control signal.

[0043] In one optional embodiment, the output unit includes a sixth operational amplifier, a seventh operational amplifier, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a first transmission gate, a second transmission gate, a third transmission gate, and a fourth transmission gate.

[0044] The inverting input terminal of the sixth operational amplifier is electrically connected to the eighth resistor to input the voltage change; the non-inverting input terminal of the sixth operational amplifier is electrically connected to the ninth resistor to input the first reference voltage; and the output terminal of the sixth operational amplifier is electrically connected to the first transmission gate to output the first target reference voltage.

[0045] The second transmission gate is used to output the first reference voltage;

[0046] The inverting input terminal of the seventh operational amplifier is electrically connected to the tenth resistor to input the voltage change; the non-inverting input terminal of the seventh operational amplifier is electrically connected to the eleventh resistor to input the second reference voltage; and the output terminal of the seventh operational amplifier is electrically connected to the third transmission gate to output the second target reference voltage.

[0047] The fourth transmission gate is used to output the second reference voltage.

[0048] In one alternative embodiment, the device further includes a base voltage generating unit;

[0049] The base voltage generating unit is used to perform voltage division processing on the received initial second reference voltage to obtain the base voltage;

[0050] The calculation unit is used to determine the voltage change based on the substrate voltage, the power supply voltage reference value, and the power supply voltage of the OLED pixel area.

[0051] The output unit is configured to adjust the first reference voltage and the second reference voltage according to the base voltage and the voltage change to obtain a first target reference voltage and a second target reference voltage; and under the control of the first control signal and the second control signal, output the first reference voltage and the second reference voltage, or output the first target reference voltage and the second target reference voltage.

[0052] In one alternative embodiment, it further includes a first trimming resistor, a second trimming resistor, and a third trimming resistor;

[0053] The first end of the first adjustment resistor is electrically connected to the inverting input terminal of the fifth operational amplifier, and the second end of the first adjustment resistor is electrically connected to the output terminal of the fifth operational amplifier.

[0054] The first end of the second adjustment resistor is electrically connected to the inverting input terminal of the sixth operational amplifier, and the second end of the second adjustment resistor is electrically connected to the output terminal of the sixth operational amplifier.

[0055] The first end of the third adjustment resistor is electrically connected to the inverting input terminal of the seventh operational amplifier, and the second end of the third adjustment resistor is electrically connected to the output terminal of the seventh operational amplifier.

[0056] In a second aspect, embodiments of this application provide a driving device, including a low dropout linear stabilizer (LDO), a GAMMA circuit, and a voltage regulation device as described in any of the first aspects;

[0057] The output terminal of the LDO is electrically connected to the input terminal of the voltage regulation device. The LDO is used to provide an initial reference voltage to the voltage regulation device and to provide a power supply voltage to the OLED.

[0058] The first input terminal of the GAMMA circuit is electrically connected to the first output terminal of the voltage regulation device, and the second input terminal of the GAMMA circuit is electrically connected to the second output terminal of the voltage regulation device. The GAMMA circuit is used to provide data voltage to the OLED according to the first reference voltage and the second reference voltage, or the first target reference voltage and the second target reference voltage, output by the voltage regulation device.

[0059] The beneficial effects of this invention are as follows:

[0060] This application provides a voltage regulation device and a driving device. The voltage regulation device determines the power supply voltage of the OLED pixel area, the power supply voltage reference value, the first reference voltage, and the second reference voltage through an input unit; determines the voltage change through a calculation unit; and sets a threshold voltage range through a detection unit. When the voltage change is within the threshold voltage range, the output first reference voltage and second reference voltage are unregulated voltages. When the voltage change is not within the threshold voltage range, the output first target reference voltage and second target reference voltage are voltages regulated by the voltage change.

[0061] This application can reduce the frequency at which the first reference voltage and the second reference voltage change with the fluctuation of the OLED pixel area power supply voltage, thereby reducing the frequency of the change in the difference between the OLED pixel area power supply voltage and the data voltage, and further reducing the frequency of the change in the pixel current with the fluctuation of the OLED pixel area power supply voltage, reducing screen flicker and improving display effect. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0063] Figure 1This is a schematic diagram of a driving device provided in related technologies;

[0064] Figure 2 This is a schematic diagram of another driving device provided in the related technology;

[0065] Figure 3 This is a schematic diagram of a voltage regulation device provided in related technologies;

[0066] Figure 4 This is a schematic diagram of the structure of a voltage regulation device provided in an embodiment of this application;

[0067] Figure 5 This is a schematic diagram of another voltage regulation device provided in an embodiment of this application;

[0068] Figure 6 A circuit diagram of a voltage regulation device provided in an embodiment of this application;

[0069] Figure 7 A circuit diagram of another voltage regulation device provided in the embodiments of this application;

[0070] Figure 8 A circuit diagram of another voltage regulation device provided in the embodiments of this application;

[0071] Figure 9 A circuit diagram of another voltage regulation device provided in the embodiments of this application;

[0072] Figure 10 A circuit diagram of another voltage regulation device provided in the embodiments of this application;

[0073] Figure 11 A circuit diagram of another voltage regulation device provided in the embodiments of this application;

[0074] Figure 12 A circuit diagram of another voltage regulation device provided in the embodiments of this application;

[0075] Figure 13 This is a schematic diagram of a driving device provided in an embodiment of this application. Detailed Implementation

[0076] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0077] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0078] The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0079] OLEDs are current-injection type devices, and their luminous intensity is directly proportional to the pixel current. They are widely used in the display technology field. For example... Figure 1 The diagram shown is a structural schematic of a driving device provided by related technologies.

[0080] Figure 1 In this circuit, the LDO (Low Dropout Regulator) provides the power supply voltage ELVDD to the OLED, and the GAMMA circuit 101 provides the data voltage VDATA to the OLED.

[0081] Since the difference between the power supply voltage ELVDD_IN and the data voltage VDATA in the OLED pixel area determines the pixel current, fluctuations in the power supply voltage ELVDD_IN in the OLED pixel area will affect the pixel current and thus the OLED display effect.

[0082] The magnitude of the data voltage VDATA is determined by the first reference voltage VGMP and the second reference voltage VGSP. Specifically, R i This refers to the resistors that make up the resistor string in a GAMMA circuit.

[0083] like Figure 2 The diagram shows another driving device provided in the related art, including a voltage adjustment device 201. The voltage adjustment device 201 collects the power supply voltage ELVDD_IN of the OLED pixel area in real time, calculates the voltage change ΔELVDD, and adjusts the first reference voltage VGMP and the second reference voltage VGSP based on the voltage change ΔELVDD to obtain the first target reference voltage VGMP-ΔELVDD and the second target reference voltage VGSP-ΔELVDD.

[0084] Specifically, such as Figure 3The diagram shown is a structural schematic of a voltage regulation device provided in the related art. The device includes an input unit 301, a calculation unit 302, and an output unit 303.

[0085] The input unit 301 is used to amplify the received initial reference voltage Vref to obtain the power supply voltage reference value ELVDD_TAR, and to acquire the power supply voltage ELVDD_IN of the OLED pixel area in real time.

[0086] Calculation unit 302 is used to determine the voltage change ΔELVDD based on the power supply voltage reference value ELVDD_TAR and the OLED pixel area power supply voltage ELVDD_IN;

[0087] The output unit 303 is used to adjust the received first reference voltage VGMP and second reference voltage VGSP according to the voltage change ΔELVDD, and output the adjusted first target reference voltage VGMP-ΔELVDD and second target reference voltage VGSP-ΔELVDD.

[0088] Because existing technologies simply detect the change in the OLED pixel area power supply voltage ELVDD_IN, ΔELVDD, when the OLED pixel area power supply voltage ELVDD_IN changes frequently, the first reference voltage VGMP and the second reference voltage VGSP also change frequently along with ELVDD_IN. This causes the difference between the OLED pixel area power supply voltage ELVDD_IN and the data voltage VDATA to change frequently, which in turn causes the pixel current to change frequently with the fluctuation of the OLED pixel area power supply voltage, resulting in screen flicker and affecting the display effect.

[0089] In addition, such as Figure 1 and Figure 2 The drive unit shown also includes a buffer 102 for enhancing drive capability.

[0090] Based on the above problems, embodiments of this application provide a voltage regulation device, such as... Figure 4 As shown, it includes an input unit 401, a calculation unit 402, a detection unit 403, and an output unit 404;

[0091] The input unit 401, the calculation unit 402, and the output unit 404 are connected in sequence. The input unit 401 is also connected to the output unit 404, and the detection unit 403 is also connected to the calculation unit 402 and the output unit 404.

[0092] The input unit 401 is used to acquire the power supply voltage ELVDD_IN of the OLED pixel area in real time, and to amplify the received initial reference voltage Vref to obtain the power supply voltage reference value ELVDD_TAR, the first reference voltage VGMP, and the second reference voltage VGSP.

[0093] Calculation unit 402 is used to determine the voltage change ΔELVDD based on the power supply voltage reference value ELVDD_TAR and the OLED pixel area power supply voltage ELVDD_IN;

[0094] The detection unit 403 is used to output a first control signal DEL_EN and a second control signal DEL_ENB based on whether the voltage change ΔELVDD is within the threshold voltage range.

[0095] The output unit 404 is used to adjust the first reference voltage VGMP and the second reference voltage VGSP according to the voltage change ΔELVDD to obtain the first target reference voltage VGMP-ΔELVDD and the second target reference voltage VGSP-ΔELVDD; under the control of the first control signal DEL_EN and the second control signal DEL_ENB, it outputs the first reference voltage VGMP and the second reference voltage VGSP, or outputs the first target reference voltage VGMP-ΔELVDD and the second target reference voltage VGSP-ΔELVDD.

[0096] This application provides a voltage regulation device. The voltage regulation device sets a threshold voltage range through a detection unit. When the voltage change ΔELVDD is within the threshold voltage range, the first reference voltage VGMP and the second reference voltage VGSP output by the output unit are unregulated voltages. When the voltage change is not within the threshold voltage range, the first target reference voltage VGMP-ΔELVDD and the second target reference voltage VGSP-ΔELVDD output by the output unit are both voltages regulated by the voltage change ΔELVDD.

[0097] This application can reduce the frequency at which the first reference voltage VGMP and the second reference voltage VGSP change with the fluctuation of the OLED pixel area power supply voltage, thereby reducing the frequency at which the difference between the OLED pixel area power supply voltage ELVDD_IN and the data voltage VDATA changes, and further reducing the frequency at which the pixel current changes with the fluctuation of the OLED pixel area power supply voltage ELVDD_IN, reducing screen flicker and improving display effect.

[0098] It should be noted that OLED can be AMOLED (Active Matrix Organic Light Emitting Diode).

[0099] In one embodiment, such as Figure 5 As shown, the input unit includes a data acquisition module 501, a first reference voltage generation module 502, a second reference voltage generation module 503, and a power supply voltage reference value generation module 504.

[0100] Acquisition module 501 is used to acquire the power supply voltage ELVDD_IN of the OLED pixel area in real time;

[0101] Specifically, such as Figure 6 As shown, the acquisition module 501 includes a first unity-gain buffer 601;

[0102] The non-inverting input terminal of the first unity gain buffer 601 is electrically connected to the voltage sampling terminal of the OLED, and the inverting input terminal of the first unity gain buffer 601 is electrically connected to the output terminal of the first unity gain buffer 601, which is used to output the power supply voltage ELVDD_IN of the OLED pixel area.

[0103] In a specific embodiment, the first unity-gain buffer 601 is used to acquire the real-time power supply voltage ELVDD_IN of the OLED pixel area, perform buffering processing, and enhance the driving capability of the output OLED pixel area power supply voltage ELVDD_IN.

[0104] The first reference voltage generation module 502 is used to amplify the initial reference voltage Vref based on the first amplification factor and then perform buffering to obtain the first reference voltage VGMP.

[0105] Specifically, the first reference voltage generation module 502 includes a first operational amplifier 602, a second unity-gain buffer 603, a first resistor R1, and a second resistor R2;

[0106] The non-inverting input terminal of the first operational amplifier 602 is used to input the reference voltage Vref. The inverting input terminal of the first operational amplifier 602 is electrically connected to the second terminal of the first resistor R1 and the first terminal of the second resistor R2. The output terminal of the first operational amplifier 602 is electrically connected to the first terminal of the first resistor R1 and the non-inverting input terminal of the second unity-gain buffer 603.

[0107] The second terminal of the second resistor R2 is grounded;

[0108] The inverting input terminal of the second unity-gain buffer 603 and the output terminal of the second unity-gain buffer 603 are electrically connected to output the first reference voltage VGMP.

[0109] In a specific embodiment, the first operational amplifier 602 is used to input the initial reference voltage Vref, amplify the initial reference voltage Vref based on the first amplification factor to obtain the first reference voltage VGMP, and send the first reference voltage VGMP to the second gain buffer 603. The first amplification factor is related to the resistance values ​​of the first resistor R1 and the second resistor R2.

[0110] The second unity-gain buffer 603 is used to buffer the received first reference voltage VGMP and enhance the driving capability of the output first reference voltage VGMP.

[0111] The second reference voltage generation module 503 is used to amplify the initial reference voltage Vref based on the second amplification factor, and then perform voltage division and buffering to obtain the second reference voltage VGSP.

[0112] Specifically, the second reference voltage generation module 503 includes a second operational amplifier 604, a third unity-gain buffer 605, a third resistor R3, a fourth resistor R4, and a first variable resistor RP1;

[0113] The non-inverting input terminal of the second operational amplifier 604 is used to input the initial reference voltage Vref. The inverting input terminal of the second operational amplifier 604 is electrically connected to the second terminal of the third resistor R3 and the first terminal of the fourth resistor R4. The output terminal of the second operational amplifier 604 is electrically connected to the first terminal of the third resistor R3 and the first terminal of the first variable resistor RP1.

[0114] The second terminal of the fourth resistor R4 is grounded;

[0115] The second terminal of the first variable resistor RP1 is grounded;

[0116] The non-inverting input terminal of the third unity gain buffer 605 is electrically connected to the third terminal of the first variable resistor RP1, and the inverting input terminal of the third unity gain buffer 605 is electrically connected to the output terminal of the third unity gain buffer 605, for outputting the second reference voltage VGSP.

[0117] In a specific embodiment, the second operational amplifier 604 is used to input the initial reference voltage Vref, amplify the initial reference voltage Vref based on the second amplification factor to obtain the initial second reference voltage VGSP_IN, and divide the initial second reference voltage VGSP_IN through the first variable resistor RP1 to obtain the second reference voltage VGSP. The second amplification factor is related to the resistance values ​​of the third resistor R3 and the fourth resistor R4.

[0118] It should be noted that the magnitude of the second reference voltage VGSP is related to the position of the third terminal of the first variable resistor RP1.

[0119] The third unity-gain buffer 605 is used to buffer the received second reference voltage VGSP and enhance the driving capability of the output second reference voltage VGSP.

[0120] The power supply voltage reference value generation module 504 is used to amplify the initial reference voltage Vref based on the third amplification factor and then perform buffering to obtain the power supply voltage reference value ELVDD_TAR.

[0121] Specifically, the power supply voltage reference value generation module 504 includes a third operational amplifier 606, a fourth unity-gain buffer 607, a fifth resistor R5, and a sixth resistor R6.

[0122] The non-inverting input of the third operational amplifier 606 is used to input the initial reference voltage Vref. The inverting input of the third operational amplifier 606 is electrically connected to the second terminal of the fifth resistor R5 and the first terminal of the sixth resistor R6. The output of the third operational amplifier 606 is electrically connected to the first terminal of the fifth resistor R5 and the non-inverting input of the fourth unity-gain buffer 607.

[0123] The second terminal of the sixth resistor R6 is grounded;

[0124] The inverting input and output of the fourth unity gain buffer 607 are electrically connected to output the power supply voltage reference value ELVDD_TAR.

[0125] In a specific embodiment, the third operational amplifier 606 is used to input the initial reference voltage Vref, amplify the initial reference voltage Vref based on the third amplification factor to obtain the power supply voltage reference value ELVDD_TAR, and send the power supply voltage reference value ELVDD_TAR to the fourth unity gain buffer 607. The third amplification factor is related to the resistance values ​​of the fifth resistor R5 and the sixth resistor R6.

[0126] The fourth unity-gain buffer 607 is used to buffer the received power supply voltage reference value ELVDD_TAR and enhance the driving capability of the output power supply voltage reference value ELVDD_TAR.

[0127] In one embodiment, such as Figure 7 As shown, the first reference voltage generation module 502 also includes a second rheostat RP2;

[0128] The first terminal of the second rheostat RP2 is electrically connected to the second terminal of the first resistor R1, the second terminal of the second rheostat RP2 is electrically connected to the first terminal of the second resistor R2, and the third terminal of the second rheostat RP2 is electrically connected to the inverting input terminal of the first operational amplifier 602.

[0129] Specifically, the first operational amplifier 602 is used to input the initial reference voltage Vref and amplify the initial reference voltage Vref based on the first amplification factor to obtain the first reference voltage VGMP. The magnitude of the first amplification factor is related to the resistance values ​​of the first resistor R1, the second resistor R2, and the position of the third terminal of the second variable resistor RP2. In a specific implementation, the magnitude of the first amplification factor is adjusted by adjusting the position of the third terminal of the second variable resistor RP2.

[0130] The second reference voltage generation module 503 also includes a third variable resistor RP3;

[0131] The first terminal of the third rheostat RP3 is electrically connected to the second terminal of the third resistor R3, the second terminal of the third rheostat RP3 is electrically connected to the first terminal of the fourth resistor R4, and the third terminal of the third rheostat RP3 is electrically connected to the inverting input terminal of the second operational amplifier 604.

[0132] Specifically, the second operational amplifier 604 is used to input the initial reference voltage Vref and amplify the initial reference voltage Vref based on the second amplification factor to obtain the initial second reference voltage VGSP_IN. The second amplification factor is related to the resistance value of the third resistor R3, the resistance value of the fourth resistor R4, and the position of the third terminal of the third variable resistor RP3. In specific implementation, the magnitude of the second amplification factor is adjusted by adjusting the position of the third terminal of the third variable resistor RP3.

[0133] The power supply voltage reference value generation module 504 also includes a fourth rheostat RP4;

[0134] The first terminal of the fourth rheostat RP4 is electrically connected to the second terminal of the fifth resistor R5, the second terminal of the fourth rheostat RP4 is electrically connected to the first terminal of the sixth resistor R6, and the third terminal of the fourth rheostat RP4 is electrically connected to the inverting input terminal of the third operational amplifier 604.

[0135] Specifically, the third operational amplifier 606 is used to input the initial reference voltage Vref. Based on the third amplification factor, the initial reference voltage Vref is amplified to obtain the power supply voltage reference value ELVDD_TAR. The third amplification factor is related to the resistance value of the fifth resistor R5, the resistance value of the sixth resistor R6, and the position of the third terminal of the fourth variable resistor RP4. In specific implementation, the magnitude of the third amplification factor is adjusted by adjusting the position of the third terminal of the fourth variable resistor RP4.

[0136] In one embodiment, such as Figure 8 As shown, the computing unit 402 includes a fifth operational amplifier 801, a seventh resistor R7, and an eighth resistor R8;

[0137] The inverting input of the fifth operational amplifier 801 is electrically connected to the seventh resistor R7 and is used to input the OLED pixel area power supply voltage ELVDD_IN. The non-inverting input of the fifth operational amplifier 801 is electrically connected to the eighth resistor R8 and is used to input the power supply voltage reference value ELVDD_TAR. The output of the fifth operational amplifier 801 is used to output the voltage change ΔELVDD.

[0138] Specifically, the calculation unit 402 is a subtractor composed of the fifth operational amplifier 801, the seventh resistor R7, and the eighth resistor R8. The calculation unit 402 receives the power supply voltage reference value ELVDD_TAR determined by the power supply voltage generation module 502 and the OLED pixel area power supply voltage ELVDD_IN collected in real time by the acquisition module 501. The difference between the power supply voltage reference value ELVDD_TAR and the OLED pixel area power supply voltage ELVDD_IN is used as the voltage change ΔELVDD, that is, the voltage change ΔELVDD = ELVDD_TAR - ELVDD_IN.

[0139] In one embodiment, such as Figure 9 As shown, the detection unit 403 includes a first comparator CMP1, a second comparator CMP2, an OR gate 901, and a NOT gate 902;

[0140] The non-inverting input of the first comparator CMP1 is used to input the voltage change ΔELVDD. The inverting input of the first comparator CMP1 is electrically connected to the fourth terminal of the first rheostat RP1. The output of the first comparator CMP1 is electrically connected to the first receiving terminal of the OR gate 901.

[0141] The inverting input of the second comparator CMP2 is used to input the voltage change ΔELVDD. The non-inverting input of the second comparator CMP2 is electrically connected to the fifth terminal of the first rheostat RP1. The output of the second comparator CMP2 is electrically connected to the second receiving terminal of the OR gate 901.

[0142] The output of OR gate 901 is electrically connected to the input of NOT gate 902 to output the first control signal DEL_EN, and NOT gate 902 is used to output the second control signal DEL_ENB.

[0143] In a specific embodiment, the threshold voltage range is related to the position of the fourth terminal of the first variable resistor RP1 and the fifth terminal of the first variable resistor RP2. The first threshold voltage is determined by the position of the fourth terminal of the first variable resistor RP1, and the second threshold voltage is determined by the position of the fifth terminal of the first variable resistor RP2. The first threshold voltage is greater than the second threshold voltage.

[0144] When the voltage change ΔELVDD is less than the first threshold voltage but greater than the second threshold voltage, the voltage change ΔELVDD is determined to be within the threshold voltage range; when the voltage change ΔELVDD is greater than the first threshold voltage or less than the second threshold voltage, the voltage change ΔELVDD is determined to be outside the threshold voltage range.

[0145] The first comparator CMP1 is used to determine whether the voltage change ΔELVDD is less than the first threshold voltage. When it is determined that the voltage change ΔELVDD is less than the first threshold voltage, the first comparator CMP1 sends a first low-level signal to the first receiving end of the OR gate. When it is determined that the voltage change ΔELVDD is greater than the first threshold voltage, the first comparator CMP1 sends a first high-level signal to the first receiving end of the OR gate.

[0146] The first low-level signal can be 0, and the first high-level signal can be 1.

[0147] The second comparator CMP2 is used to determine whether the voltage change ΔELVDD is greater than the second threshold voltage. When the voltage change ΔELVDD is greater than the second threshold voltage, the second comparator CMP2 sends a second low-level signal to the second receiver of the OR gate. When the voltage change ΔELVDD is less than the second threshold voltage, the second comparator CMP2 sends a second high-level signal to the second receiver of the OR gate.

[0148] The second low-level signal can be 0, and the second high-level signal can be 1.

[0149] For example, when the first threshold voltage is determined to be 0.5V by the position of the fourth terminal of the first variable resistor RP1, the second threshold voltage is determined to be 0.1V by the position of the fifth terminal of the first variable resistor RP2.

[0150] In one possible implementation, if the voltage change ΔELVDD received by the first comparator CMP1 is 0.4V, since 0.4V is less than the first threshold voltage of 0.5V and greater than the second threshold voltage of 0.1V, that is, the voltage change ΔELVDD is determined to be within the threshold voltage range, then the first comparator CMP1 sends a first low-level signal to the first receiving end of the OR gate, and the second comparator CMP2 sends a second low-level signal to the second receiving end of the OR gate.

[0151] In another possible implementation, if the voltage change ΔELVDD received by the first comparator CMP1 is 0.6V, since 0.6V is greater than the first threshold voltage of 0.5V and 0.6V is greater than the second threshold voltage of 0.1V, that is, it is determined that the voltage change ΔELVDD is not within the threshold voltage range, then the first comparator CMP1 sends a first high-level signal to the first receiving end of the OR gate, and the second comparator CMP2 sends a second low-level signal to the second receiving end of the OR gate.

[0152] In another possible implementation of the prevention, if the voltage change ΔELVDD received by the first comparator CMP1 is 0.05V, since 0.05V is less than the first threshold voltage of 0.5V and less than the second threshold voltage of 0.1V, that is, it is determined that the voltage change ΔELVDD is not within the threshold voltage range, then the first comparator CMP1 sends a first low-level signal to the first receiving end of the OR gate, and the second comparator CMP2 sends a second high-level signal to the second receiving end of the OR gate.

[0153] OR gate 901 is used to output a first control signal based on a first low-level signal or a first high-level signal received by the first receiving end and a second low-level signal or a second high-level signal received by the second receiving end.

[0154] For example, in one possible implementation, if the first receiving end of OR gate 901 receives a first low-level signal and the second receiving end of OR gate 901 receives a second low-level signal, that is, if the voltage change ΔELVDD is determined to be within the threshold voltage range, then the first control signal DEL_EN output by the output end of OR gate is low.

[0155] In another possible implementation, if the first receiving end of OR gate 901 receives a first high-level signal and the second receiving end of OR gate 901 receives a second low-level signal, that is, if it is determined that the voltage change ΔELVDD is not within the threshold voltage range, then the first control signal DEL_EN output by the OR gate output is high.

[0156] In another possible implementation, if the first receiving end of OR gate 901 receives a first low-level signal and the second receiving end of OR gate 901 receives a second high-level signal, that is, if it is determined that the voltage change ΔELVDD is not within the threshold voltage range, then the first control signal DEL_EN output by the OR gate output is high.

[0157] The NOT gate 902 is used to invert the received first control signal DEL_EN. That is, when the first control signal DEL_EN output by the OR gate 901 is low, the second control signal DEL_ENB output by the NOT gate 902 is high; when the first control signal DEL_EN output by the OR gate 901 is high, the second control signal DEL_ENB output by the NOT gate 902 is low.

[0158] In other words, when the voltage change ΔELVDD is within the threshold voltage range, the second control signal DEL_ENB output by the NOT gate 902 is at a high level; when the voltage change ΔELVDD is outside the threshold voltage range, the second control signal DEL_ENB output by the NOT gate 902 is at a low level.

[0159] In one embodiment, such as Figure 10 As shown, the output unit 404 includes a sixth operational amplifier 1001, a seventh operational amplifier 1002, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a first transmission gate 1003, a second transmission gate 1004, a third transmission gate 1005, and a fourth transmission gate 1006.

[0160] The inverting input terminal of the sixth operational amplifier 1001 is electrically connected to the eighth resistor R8 and is used to input the voltage change ΔELVDD. The non-inverting input terminal of the sixth operational amplifier 1001 is electrically connected to the ninth resistor R9 and is used to input the first reference voltage VGMP. The output terminal of the sixth operational amplifier 1001 is electrically connected to the first transmission gate 1003 and is used to output the first target reference voltage VGMP-ΔELVDD.

[0161] The second transmission gate 1004 is used to output the first reference voltage VGMP;

[0162] The inverting input of the seventh operational amplifier 1002 is electrically connected to the tenth resistor R10 to input the voltage change ΔELVDD. The non-inverting input of the seventh operational amplifier 1002 is electrically connected to the eleventh resistor R11 to input the second reference voltage VGSP. The output of the seventh operational amplifier 1002 is electrically connected to the third transmission gate 1004 to output the second target reference voltage VGSP-ΔELVDD.

[0163] The fourth transmission gate 1006 is used to output the second reference voltage VGSP.

[0164] Based on the subtractor composed of the sixth operational amplifier 1001, the eighth resistor R8 and the ninth resistor R9, the first target reference voltage is determined as VGMP-ΔELVDD by subtracting the first reference voltage VGMP input to the non-inverting input terminal and the voltage change ΔELVDD input to the inverting input terminal.

[0165] The subtractor, composed of the seventh operational amplifier 1002, the tenth resistor R10, and the eleventh resistor R11, determines the second target reference voltage as VGSP-ΔELVDD by subtracting the second reference voltage VGSP input to the non-inverting input terminal from the voltage change ΔELVDD input to the inverting input terminal.

[0166] In a specific embodiment, when the first control signal DEL_EN received by the first transmission gate, the second transmission gate, the third transmission gate, and the fourth transmission gate is at a low level and the second control signal DEL_ENB is at a high level, that is, when it is determined that the voltage change ΔELVDD is within the threshold voltage range, the second transmission gate is turned on to output the first reference voltage VGMP, and the fourth transmission gate is turned on to output the second reference voltage VGSP.

[0167] When the first control signal DEL_EN received by the first transmission gate, the second transmission gate, the third transmission gate, and the fourth transmission gate is at a high level, and the second control signal DEL_ENB is at a low level, that is, when it is determined that the voltage change ΔELVDD is not within the threshold voltage range, the second transmission gate is turned on to output the first target reference voltage VGMP-ΔELVDD, and the third transmission gate is turned on to output the second target reference voltage VGSP-ΔELVDD.

[0168] In other words, when the voltage change is within the threshold voltage range, the output voltage is an unregulated first reference voltage VGMP and a second reference voltage VGSP. This reduces the frequency at which VGMP and VGSP change with ELVDD fluctuations, thereby reducing screen flicker and improving display performance.

[0169] In one embodiment, such as Figure 11 As shown, it also includes a base voltage generation unit 1101;

[0170] The base voltage generation unit 1101 is used to perform voltage division processing on the received initial second reference voltage VGSP_IN to obtain the base voltage VBOT;

[0171] Calculation unit 402 is used to determine the voltage change ΔELVDD_1 based on the substrate voltage VBOT, the power supply voltage reference value ELVDD_TAR, and the OLED pixel area power supply voltage ELVDD_IN.

[0172] Output unit 404 is used to adjust the first reference voltage VGMP and the second reference voltage VGSP according to the base voltage VBOT and the voltage change ΔELVDD_1 to obtain the first target reference voltage VGMP-ΔELVDD and the second target reference voltage VGSP-ΔELVDD; under the control of the first control signal DEL_EN and the second control signal DEL_ENB, output the first reference voltage VGMP and the second reference voltage VGSP, or output a target reference voltage VGMP-ΔELVDD and the second target reference voltage VGSP-ΔELVDD.

[0173] Specifically, the base voltage generation unit 1101 includes a fifth unity-gain buffer 1102 and a fifth variable resistor RP5.

[0174] The first terminal of the fifth variable resistor RP5 is electrically connected to the output terminal of the second operational amplifier 604 and is used to input the initial second reference voltage VGSP_IN. The second terminal of the fifth variable resistor RP5 is grounded. The third terminal of the fifth variable resistor RP5 is electrically connected to the non-inverting input terminal of the fifth unity-gain buffer 1002 and is used to perform voltage division on the second reference voltage VGSP_IN to obtain the base voltage VBOT.

[0175] The inverting input of the fifth unity gain buffer 1102 is electrically connected to the output of the fifth unity gain buffer 1002, and is used to output the base voltage VBOT.

[0176] In addition, it should be noted that the output terminal of the fifth unity-gain buffer 1102 is electrically connected to the twelfth resistor R12 at the non-inverting input terminal of the fifth operational amplifier 801, the thirteenth resistor R13 at the non-inverting input terminal of the sixth operational amplifier 1001, and the fourteenth resistor R14 at the non-inverting input terminal of the seventh operational amplifier 1002.

[0177] In a specific embodiment, the calculation unit 402 is a subtractor composed of a fifth operational amplifier 801, a seventh resistor R7, an eighth resistor R8, and a twelfth resistor R12. The fifth operational amplifier 801 receives the power supply voltage reference value ELVDD_TAR and the substrate voltage VBOT through the non-inverting input terminal, and the OLED pixel area power supply voltage ELVDD_IN through the inverting input terminal. The difference between the sum of the power supply voltage reference value ELVDD_TAR and the substrate voltage VBOT and the OLED pixel area power supply voltage ELVDD_IN is taken as the voltage change ΔELVDD_1, that is, the voltage change ΔELVDD_1 = ELVDD_TAR + VBOT - ELVDD_IN = ΔELVDD + VBOT.

[0178] Based on the subtractor composed of the sixth operational amplifier 1001, the eighth resistor R8, the ninth resistor R9, and the thirteenth resistor R13, the sixth operational amplifier 1001 receives the first reference voltage VGMP and the base voltage VBOT through the non-inverting input terminal, and receives the voltage change ΔELVDD_1 through the inverting input terminal, and determines the first target reference voltage as VGMP+VBOT-ΔELVDD_1=VGMP+VBOT-(ΔELVDD+VBOT)=VGMP-ΔELVDD.

[0179] Based on the subtractor composed of the seventh operational amplifier 1002, the tenth resistor R10, the eleventh resistor R11, and the fourteenth resistor R14, the seventh operational amplifier 1002 inputs the second reference voltage VGSP and the base voltage VBOT through the non-inverting input terminal, and inputs the voltage change ΔELVDD_ through the inverting input terminal, and determines the second target reference voltage as VGSP+VBOT-ΔELVDD_1=VGSP+VBOT-(ΔELVDD+VBOT)=VGSP-ΔELVDD.

[0180] It should be noted that the substrate voltage generation unit 1101 generates a substrate voltage VBOT and sends it to the calculation unit 402 and the output unit 404, thereby increasing the calculation range of the calculation unit 402 to a higher voltage range. This avoids calculation errors caused by a negative difference between the power supply voltage reference value ELVDD_TAR and the OLED pixel area power supply voltage ELVDD_IN. At the same time, the substrate voltage VBOT is eliminated during the calculation process of the output unit 404, without affecting the final calculation result.

[0181] In one embodiment, such as Figure 12 As shown, it also includes a first adjustment resistor, a second adjustment resistor, and a third adjustment resistor;

[0182] The first end of the first trimming resistor RT1 is electrically connected to the inverting input terminal of the fifth operational amplifier 801, and the second end of the first trimming resistor RT1 is electrically connected to the output terminal of the fifth operational amplifier 801.

[0183] The first end of the second adjustment resistor RT2 is electrically connected to the inverting input terminal of the sixth operational amplifier 1001, and the second end of the second adjustment resistor RT2 is electrically connected to the output terminal of the sixth operational amplifier 1001.

[0184] The first end of the third adjustment resistor RT3 is electrically connected to the inverting input of the seventh operational amplifier 1002, and the second end of the third adjustment resistor RT3 is electrically connected to the output of the seventh operational amplifier 1002.

[0185] Specifically, the offset voltage output of the fifth operational amplifier 801 is eliminated by the first trimming resistor, the offset voltage output of the sixth operational amplifier 1001 is eliminated by the second trimming resistor, and the offset voltage output of the seventh operational amplifier 1002 is eliminated by the third trimming resistor.

[0186] Based on the same inventive concept, this application also provides a driving device, which is similar in principle to the voltage regulation device described above, and the repeated parts will not be described again.

[0187] like Figure 13 The diagram shown is a schematic of the structure of a driving device provided in an embodiment of this application, including a low dropout linear stabilizer (LDO), a GAMMA circuit 1301, and a voltage regulation device 1303 as described in any one of claims 1 to 8.

[0188] The output of the LDO is electrically connected to the input of the voltage regulator 1303. The LDO is used to provide the initial reference voltage Vref to the voltage regulator and the power supply voltage ELVDD to the OLED.

[0189] The first input terminal of the GAMMA circuit 1301 is electrically connected to the first output terminal of the voltage regulation device 1303, and the second input terminal of the GAMMA circuit 1301 is electrically connected to the second output terminal of the voltage regulation device 1303. The GAMMA circuit 1301 is used to provide the data voltage VADTA to the OLED according to the first reference voltage VGMP and the second reference voltage VGSP, or the first target reference voltage VGMP-ΔELVDD and the second target reference voltage VGSP-ΔELVDD, output by the voltage regulation device 1303.

[0190] This application provides a voltage regulation device and a driving device. The voltage regulation device sets a threshold voltage range through a detection unit. When the voltage change ΔELVDD is within the threshold voltage range, the first reference voltage VGMP and the second reference voltage VGSP output by the output unit are unregulated voltages. When the voltage change is not within the threshold voltage range, the first target reference voltage VGMP-ΔELVDD and the second target reference voltage VGSP-ΔELVDD output by the output unit are both voltages regulated by the voltage change ΔELVDD.

[0191] This application can reduce the frequency at which the first reference voltage VGMP and the second reference voltage VGSP change with the fluctuation of the OLED pixel area power supply voltage, thereby reducing the frequency at which the difference between the OLED pixel area power supply voltage ELVDD_IN and the data voltage VDATA changes, and further reducing the frequency at which the pixel current changes with the fluctuation of the OLED pixel area power supply voltage ELVDD_IN, reducing screen flicker and improving display effect.

[0192] The present application has been described above with reference to block diagrams and / or flowcharts illustrating methods, apparatus (systems), and / or computer program products according to embodiments of the present application. It should be understood that a block of a block diagram and / or flowchart, as well as combinations of blocks of block diagrams and / or flowcharts, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, and / or other programmable data processing means to produce a machine, such that the instructions, executable via the computer processor and / or other programmable data processing means, create methods for implementing the functions / actions specified in the blocks of the block diagrams and / or flowcharts.

[0193] Accordingly, this application can also be implemented using hardware and / or software (including firmware, resident software, microcode, etc.). Furthermore, this application can take the form of a computer program product on a computer-usable or computer-readable storage medium, having computer-usable or computer-readable program code implemented in the medium for use by or in conjunction with an instruction execution system. In the context of this application, a computer-usable or computer-readable medium can be any medium that can contain, store, communicate, transmit, or deliver a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0194] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A voltage regulating device, characterized in that, include: Input unit, calculation unit, detection unit, and output unit; The input unit, the calculation unit, and the output unit are connected in sequence. The input unit is also connected to the output unit, and the detection unit is also connected to both the calculation unit and the output unit. The input unit is used to acquire the power supply voltage of the OLED pixel area in real time, and to amplify the received initial reference voltage to obtain the power supply voltage reference value, the first reference voltage, and the second reference voltage. The calculation unit is used to determine the voltage change based on the power supply voltage reference value and the power supply voltage of the OLED pixel area. The detection unit is used to output a first control signal and a second control signal based on whether the voltage change is within the threshold voltage range. The output unit is used to adjust the first reference voltage and the second reference voltage according to the voltage change to obtain the first target reference voltage and the second target reference voltage; Under the control of the first control signal and the second control signal, when the voltage change is within the threshold voltage range, the first reference voltage and the second reference voltage are output; when the voltage change is not within the threshold voltage range, the first target reference voltage and the second target reference voltage are output.

2. The apparatus as claimed in claim 1, characterized in that, The input unit includes an acquisition module, a first reference voltage generation module, a second reference voltage generation module, and a power supply voltage reference value generation module; The acquisition module is used to acquire the power supply voltage of the OLED pixel area in real time; The first reference voltage generation module is used to amplify the initial reference voltage based on a first amplification factor and then perform buffering to obtain the first reference voltage. The second reference voltage generation module is used to amplify the initial reference voltage based on the second amplification factor, and then perform voltage division and buffering to obtain the second reference voltage. The power supply voltage reference value generation module is used to amplify the initial reference voltage based on the third amplification factor and then perform buffering to obtain the power supply voltage reference value.

3. The apparatus as described in claim 2, characterized in that, The acquisition module includes a first unity-gain buffer; The non-inverting input of the first unity-gain buffer is electrically connected to the voltage sampling terminal of the OLED, and the inverting input of the first unity-gain buffer is electrically connected to the output terminal of the first unity-gain buffer, for outputting the power supply voltage of the OLED pixel area; The first reference voltage generation module includes a first operational amplifier, a second unity-gain buffer, a first resistor, and a second resistor; The non-inverting input terminal of the first operational amplifier is used to input the initial reference voltage, the inverting input terminal of the first operational amplifier is electrically connected to the second terminal of the first resistor and the first terminal of the second resistor, and the output terminal of the first operational amplifier is electrically connected to the first terminal of the first resistor and the non-inverting input terminal of the second unity-gain buffer. The second terminal of the second resistor is grounded; The inverting input terminal and the output terminal of the second unity-gain buffer are electrically connected to output the first reference voltage; The second reference voltage generation module includes a second operational amplifier, a third unity-gain buffer, a third resistor, a fourth resistor, and a first variable resistor; The non-inverting input terminal of the second operational amplifier is used to input the initial reference voltage, the inverting input terminal of the second operational amplifier is electrically connected to the second terminal of the third resistor and the first terminal of the fourth resistor, and the output terminal of the second operational amplifier is electrically connected to the first terminal of the third resistor and the first terminal of the first variable resistor. The second terminal of the fourth resistor is grounded; The second terminal of the first rheostat is grounded; The non-inverting input terminal of the third unity-gain buffer is electrically connected to the third terminal of the first variable resistor, and the inverting input terminal of the third unity-gain buffer is electrically connected to the output terminal of the third unity-gain buffer, for outputting the second reference voltage; The power supply voltage reference value generation module includes a third operational amplifier, a fourth unity-gain buffer, a fifth resistor, and a sixth resistor; The non-inverting input terminal of the third operational amplifier is used to input the initial reference voltage. The inverting input terminal of the third operational amplifier is electrically connected to the second terminal of the fifth resistor and the first terminal of the sixth resistor. The output terminal of the third operational amplifier is electrically connected to the first terminal of the fifth resistor and the non-inverting input terminal of the fourth unity-gain buffer. The second terminal of the sixth resistor is grounded; The inverting input terminal and the output terminal of the fourth unity-gain buffer are electrically connected to output the power supply voltage reference value.

4. The apparatus as described in claim 3, characterized in that, The first reference voltage generation module also includes a second rheostat; The first end of the second rheostat is electrically connected to the second end of the first resistor, the second end of the second rheostat is electrically connected to the first end of the second resistor, and the third end of the second rheostat is electrically connected to the inverting input terminal of the first operational amplifier. The second reference voltage generation module also includes a third rheostat; The first terminal of the third rheostat is electrically connected to the second terminal of the third resistor, the second terminal of the third rheostat is electrically connected to the first terminal of the fourth resistor, and the third terminal of the third rheostat is electrically connected to the inverting input terminal of the second operational amplifier. The power supply voltage reference value generation module also includes a fourth rheostat; The first terminal of the fourth rheostat is electrically connected to the second terminal of the fifth resistor, the second terminal of the fourth rheostat is electrically connected to the first terminal of the sixth resistor, and the third terminal of the fourth rheostat is electrically connected to the inverting input terminal of the third operational amplifier.

5. The apparatus as claimed in claim 1, characterized in that, The computing unit includes a fifth operational amplifier, a seventh resistor, and an eighth resistor; The inverting input of the fifth operational amplifier is electrically connected to the seventh resistor and is used to input the power supply voltage of the OLED pixel area. The non-inverting input of the fifth operational amplifier is electrically connected to the eighth resistor and is used to input the power supply voltage reference value. The output of the fifth operational amplifier is used to output the voltage change.

6. The apparatus as claimed in claim 3, characterized in that, The detection unit includes a first comparator, a second comparator, an OR gate, and a NOT gate; The non-inverting input of the first comparator is used to input the voltage change, the inverting input of the first comparator is electrically connected to the fourth terminal of the first rheostat, and the output of the first comparator is electrically connected to the first receiving terminal of the OR gate. The inverting input of the second comparator is used to input the voltage change, the non-inverting input of the second comparator is electrically connected to the fifth terminal of the first rheostat, and the output of the second comparator is electrically connected to the second receiving terminal of the OR gate. The output of the OR gate is electrically connected to the input of the NOT gate, and is used to output a first control signal. The NOT gate is used to output a second control signal.

7. The apparatus as claimed in claim 5, characterized in that, The output unit includes a sixth operational amplifier, a seventh operational amplifier, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a first transmission gate, a second transmission gate, a third transmission gate, and a fourth transmission gate; The inverting input terminal of the sixth operational amplifier is electrically connected to the eighth resistor to input the voltage change; the non-inverting input terminal of the sixth operational amplifier is electrically connected to the ninth resistor to input the first reference voltage; and the output terminal of the sixth operational amplifier is electrically connected to the first transmission gate to output the first target reference voltage. The second transmission gate is used to output the first reference voltage; The inverting input terminal of the seventh operational amplifier is electrically connected to the tenth resistor to input the voltage change; the non-inverting input terminal of the seventh operational amplifier is electrically connected to the eleventh resistor to input the second reference voltage; and the output terminal of the seventh operational amplifier is electrically connected to the third transmission gate to output the second target reference voltage. The fourth transmission gate is used to output the second reference voltage.

8. The apparatus according to any one of claims 1 to 7, characterized in that, The device also includes a base voltage generating unit; The base voltage generating unit is used to perform voltage division processing on the received initial second reference voltage to obtain the base voltage; The calculation unit is used to determine the voltage change based on the substrate voltage, the power supply voltage reference value, and the power supply voltage of the OLED pixel area. The output unit is used to adjust the first reference voltage and the second reference voltage according to the base voltage and the voltage change, so as to obtain the first target reference voltage and the second target reference voltage. Under the control of the first control signal and the second control signal, the first reference voltage and the second reference voltage are output, or the first target reference voltage and the second target reference voltage are output.

9. The apparatus as claimed in claim 7, characterized in that, It also includes a first adjustment resistor, a second adjustment resistor, and a third adjustment resistor; The first end of the first adjustment resistor is electrically connected to the inverting input terminal of the fifth operational amplifier, and the second end of the first adjustment resistor is electrically connected to the output terminal of the fifth operational amplifier. The first end of the second adjustment resistor is electrically connected to the inverting input terminal of the sixth operational amplifier, and the second end of the second adjustment resistor is electrically connected to the output terminal of the sixth operational amplifier. The first end of the third adjustment resistor is electrically connected to the inverting input terminal of the seventh operational amplifier, and the second end of the third adjustment resistor is electrically connected to the output terminal of the seventh operational amplifier.

10. A driving device, characterized in that, Includes a low-dropout linear regulator (LDO), a GAMMA circuit, and a voltage regulation device as described in any of claims 1 to 9; The output terminal of the LDO is electrically connected to the input terminal of the voltage regulation device. The LDO is used to provide an initial reference voltage to the voltage regulation device and to provide a power supply voltage to the OLED. The first input terminal of the GAMMA circuit is electrically connected to the first output terminal of the voltage regulation device, and the second input terminal of the GAMMA circuit is electrically connected to the second output terminal of the voltage regulation device. The GAMMA circuit is used to provide data voltage to the OLED according to the first reference voltage and the second reference voltage, or the first target reference voltage and the second target reference voltage, output by the voltage regulation device.

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