A TFT_LCD driving chip peak current control circuit and method for reducing source driving

Abstract

The application provides a control circuit for reducing the peak current of a source of a TFT_LCD driving chip, which comprises a group of source basic driving units, including a driving buffer circuit, a polarity exchange control circuit, a positive peak current control circuit, a negative peak current control circuit, two polarity load channels S1 and S2, the driving buffer circuit is composed of a positive voltage buffer and a negative voltage buffer, the input voltage VIP_P of the positive voltage buffer is connected with the output of the positive peak current control circuit, the input voltage VIP_N of the negative voltage buffer is connected with the output of the negative peak current control circuit, the input of the positive peak current control circuit is a positive gray scale voltage VREFP, the input of the negative peak current control circuit is a negative gray scale voltage VREFN, the output OUTP of the positive voltage buffer and the output OUTN of the negative positive voltage buffer are connected with the input end of the polarity exchange circuit. The application also provides a corresponding control method. The circuit can better reduce the peak current, has low cost and is easy to popularize.

Description

Technical Field

[0001] This invention belongs to the field of chips, specifically, it relates to display driver chips, especially TFT-LCD chips, particularly to chip control for TFT-LCD displays, and especially to a control circuit and corresponding control method for reducing the peak current of the source drive during the driving process of a TFT-LCD display. Background Technology

[0002] Currently, in the process of driving TFT-LCD screen displays, the source drives the display by using a source buffer composed of operational amplifiers to drive the input data lines of the display. In the initial stage of driving the data lines of the display by the source buffer, a large current spike is generated. This current spike will have a significant adverse effect on the power supply and will also generate significant EMI noise, causing serious interference to other circuits and devices.

[0003] Therefore, in existing technologies, there is a pressing need to reduce the aforementioned current spikes in the source buffer. However, currently, there is no highly effective method to reduce the peak current of the buffer drive. Relatively speaking, some commonly used existing technologies for reducing the peak current of the buffer drive include: (1) Soft start: In the initial stage of driving, the buffer samples the output of a small power transistor for driving, and then the power transistor is changed to a combination of a small power transistor and a large power transistor for driving. This technique has limited effect on reducing the peak driving current, cannot smooth the waveform of the peak current, and cannot effectively reduce EMI noise.

[0004] (2) Power transistor gate voltage limiting: The maximum value of the gate voltage of the output power transistor is clamped to prevent the power transistor from generating too much current. This technique has limited effect on reducing drive current spikes and cannot smooth the waveform of the spike current, thus it cannot effectively reduce EMI noise.

[0005] (3) Spread spectrum technique: The timing of each source drive is regularly delayed to allow the energy of the buffer drive to spread across the frequency band, thereby reducing the power spectral density of the noise and thus reducing EMI noise. This technique cannot reduce the magnitude of the peak current of each source drive, nor can it smooth and shape the current waveform. It can only reduce the frequency of EMI noise, and its effect is very limited.

[0006] Taking the three commonly used existing technologies mentioned above as examples, their shortcomings are: firstly, they have very limited effect on reducing drive current spikes; secondly, they cannot smooth and shape the waveform of the spike current, and their effects are limited in both reducing the spike current and reducing EMI noise. Therefore, it is essential to continue to propose control circuits and corresponding control methods that can better reduce the peak current of the source drive. Summary of the Invention

[0007] To address the technical deficiencies of existing technologies, the purpose of this invention is to provide: 1. A control circuit for reducing the peak current of the source drive in a TFT-LCD driver chip, characterized in that it includes at least one set of basic source drive units, wherein each set of basic source drive units includes at least one drive buffer circuit, one polarity switching control circuit, one positive peak current control circuit, one negative peak current control circuit, and two polarity load channels S1 and S2. The drive buffer circuit consists of a positive voltage buffer and a negative voltage buffer. The input voltage VIP_P of the positive voltage buffer is connected to the output of the positive peak current control circuit, and the input voltage VIP_N of the negative voltage buffer is connected to the output of the negative peak current control circuit. The input to the positive peak current control circuit is the positive grayscale voltage VREFP, and the input to the negative peak current control circuit is the negative grayscale voltage VREFN. The output OUTP of the positive voltage buffer and the output OUTN of the negative positive voltage buffer are connected to the input terminal of the polarity switching circuit, and the output terminal of the polarity switching circuit drives the channel loads S1 and S2 with voltage.

[0008] Preferably, in the positive peak current control circuit, the positive grayscale voltage VREFP is connected to the drain of the second NMOS transistor NM2, the source of the second NMOS transistor NM2 is connected to the drain of the seventh NMOS transistor NM7, the source of the seventh NMOS transistor NM7 is connected to the third NMOS transistor NM3, the source of the third NMOS transistor NM3 is connected to the output OUTP of the positive voltage buffer, and the source of the second NMOS transistor NM2 is connected to the input VIP_P of the positive voltage buffer, forming a current loop between the positive grayscale voltage VREFP and the output OUTP of the positive voltage buffer, the corresponding current being represented as iref_p; the first PMOS transistor P The source of M1 is connected to the positive power supply VDP. The drain of the first PMOS transistor PM1 is connected to the second PMOS transistor PM2. The source of the second PMOS transistor PM2 is connected to the drain of the first NMOS transistor NM1. The source of the second NMOS transistor NM2 is connected in series with the seventh NMOS transistor NM7, the sixth NMOS transistor NM6, the fifth NMOS transistor NM5, and the fourth NMOS transistor NM4. The source of the fourth NMOS transistor NM4 is connected to ground GND. The source of the first NMOS transistor NM1 is connected to the positive voltage buffer input VIP_P, forming a current discharge path from the positive power supply VDP to VIP_P and then to ground GND. The corresponding current is represented as ib_p. In the negative peak current control circuit, the negative grayscale voltage VREFN is connected to the drain of the twelfth PMOS transistor PM12, the source of the twelfth PMOS transistor PM12 is connected to the drain of the seventeenth PMOS transistor PM17, the source of the seventeenth PMOS transistor PM17 is connected to the thirteenth PMOS transistor PM13, the source of the thirteenth PMOS transistor PM13 is connected to the output OUTN of the negative voltage buffer, and the source of the twelfth PMOS transistor PM12 is connected to the input VIP_N of the negative voltage buffer, forming a current loop between the negative grayscale voltage VREFN and the output OUTN of the negative voltage buffer, with the corresponding current represented as iref_n; the source of the eleventh NMOS transistor NM11 is grounded. GND, the drain of the eleventh NMOS transistor NM11 is connected to the twelfth NMOS transistor NM12, the source of the twelfth NMOS transistor NM12 is connected to the drain of the eleventh PMOS transistor PM11, the source of the twelfth PMOS transistor PM12 is connected in series with the seventeenth PMOS transistor PM17, the sixteenth NMOS transistor NM16, the fifteenth PMOS transistor PM15, and the fourteenth PMOS transistor PM14, the source of the fourteenth PMOS transistor PM14 is connected to the negative power supply VDN, and the source of the eleventh PMOS transistor PM11 is connected to the negative voltage buffer input VIP_N, forming a current discharge path from GND to VIP_N and then to the negative power supply VDN, the corresponding current is represented as ib_n.

[0009] According to another aspect of the present invention, a control method for reducing the peak current of the source drive in a TFT-LCD driver chip is also provided. This method is used to reduce the peak current of the source drive based on the above-mentioned control circuit. The method is characterized in that, during one working cycle of the basic source drive unit, the positive voltage buffer and the negative voltage buffer are first turned off and stop working, and the discharge tubes CSP and CSN in the polarity switching circuit are turned on to discharge the charge on the channel loads S1 and S2 to ground GND. Then, the polarity switching circuit selects the correct polarity path for the channel loads S1 and S2. When the positive voltage buffer and the negative voltage buffer start driving the channel loads S1 and S2, the positive voltage buffer and the negative voltage buffer are enabled, and the voltage on the channel loads S1 and S2 rises rapidly to a stable voltage value. When the channel loads S1 and S2 are driven to a stable voltage, the spike current control circuit is turned off, and the positive and negative voltage buffers are restored to normal buffer drive circuits to continue driving the channel loads until the end of a drive cycle. Then, the positive voltage buffer and the negative voltage buffer are turned off, thus completing one drive cycle of the source basic drive unit for the load.

[0010] Preferably, when the enable signal EN_OP of the positive voltage buffer and the negative voltage buffer changes from 1 to 0, the positive voltage buffer and the negative voltage buffer stop working; at this time, switches PS1, PS2 and NS1, NS2 are in the open state, and switches PS3, PS4 and NS3, NS4 are in the closed state. The channel load S1 carries a positive voltage, and the channel load S2 carries a negative voltage; the enable signal EN of the peak current control circuit is 0, and the transmission gates TG_P and TG_N in the peak current control circuit are in the open state, sending the grayscale voltages VREFP and VREFN to the positive and negative voltage buffers. The input terminals VIP and VIN of the device are closed, and the second PMOS transistor PM2, the seventh NMOS transistor NM7, and the seventh PMOS transistor PM7 are in the off state, so that the peak current control circuit is in the off state. At the same time, in the polarity switching circuit, one end of the ground discharge switch CSP and CSN is connected to ground, and the other end is connected to the load channels S1 and S2. The ground discharge switch CSP and CSN change from closed to open, and the channel loads S1 and S2 begin to discharge to ground GND to 0V through PS2, PS4, CSP and NS2, NS4, CSN.

[0011] Preferably, after the channel loads S1 and S2 complete their discharge to ground, switches PS1, PS2 and NS1, NS2 in the polarity switching circuit change from open to closed, and switches PS3, PS4 and NS3, NS4 change from closed to open. The negative voltage buffer selects the negative polarity driving path for the channel load S1 through NS3 and NS4, and the positive voltage buffer selects the positive polarity driving path for the channel load S2 through PS3 and PS4. At this time, the source basic driving unit has completed the preparation before driving the positive voltage buffer and the negative voltage buffer in this driving cycle, and begins to enter the driving stage of the positive voltage buffer and the negative voltage buffer.

[0012] Preferably, after the source basic driving unit completes the pre-driving preparation work, the peak current control circuit enable EN changes from 0 to 1. In the positive and negative peak current control circuits, the transmission gates TG_P and TG_N change from on to off. The second PMOS transistor PM2, the seventh NMOS transistor NM7, the twelfth NMOS transistor NM12, and the seventeenth PMOS transistor PM17 change from off to on. The input grayscale voltage VREFP is weakly connected to the positive voltage buffer input terminal VIP_P through the second NMOS transistor NM2, and the input grayscale voltage VREFN is weakly connected to the negative voltage buffer input terminal VIP_N through the twelfth PMOS transistor PM12. The positive and negative peak current control circuits then begin to operate. For the positive voltage buffer, the positive grayscale input voltage VREFP is connected to the positive voltage buffer output terminal OUTP through the second NMOS transistor NM2, the seventh NMOS transistor NM7, and the third NMOS transistor PM17. NM3 forms a current loop, with the current magnitude denoted as iref_p. The MOS transistors operate in the saturation region. At this time, the source of the third NMOS transistor NM3 is connected to OUTP, and OUTP is discharged to 0V. The drain of the third NMOS transistor NM3 is connected to the source of the seventh NMOS transistor NM7. The drain of the seventh NMOS transistor NM7 is connected to the source of the second NMOS transistor NM2, and the gate is connected to the gate of the second NMOS transistor NM2. The gate-source voltage difference of the third NMOS transistor NM3 is much greater than that of the second NMOS transistor NM2. The on-resistance Ron3 of the third NMOS transistor NM3 is much smaller than that of the second NMOS transistor NM2. At this time, the voltage at the input terminal VIP_P of the positive voltage buffer can be expressed as: VIP_P = Ron3 / (Ron2 + Ron3) ≈ 0V, Ron2 >> Ron3. That is, during the driving period, the input voltage VIP_P of the positive voltage buffer will be pulled to a voltage slightly higher than that of OUTP by OUTP.For the negative voltage buffer, the negative grayscale input voltage VREFN and the output terminal OUTN of the negative voltage buffer are connected through the 12th PMOS transistor PM12, the 17th PMOS transistor PM17, and the 13th PMOS transistor PM13 to form a current loop with a current magnitude of iref_n. At this time, the source of the 13th PMOS transistor PM13 is connected to OUTN, and OUTN is discharged to 0V. The drain of the 13th PMOS transistor PM13 is connected to the source of the 17th PMOS transistor PM17, and the drain of the 17th PMOS transistor PM17 is connected to the source of the 12th PMOS transistor PM12. The gate of the 13th PMOS transistor PM13 is connected to the source of the 12th PMOS transistor PM12. The gate of transistor PM12 is connected to the gate of the thirteenth PMOS transistor PM13. The gate-source voltage of PM13 is much greater than that of PM12, and the on-resistance Ron13 of PM13 is much less than that of PM12. Therefore, the input voltage VIP_N of the negative voltage buffer can be expressed as: VIP_N = Ron13 / (Ron12 + Ron13) ≈ 0V, Ron12 >> Ron13. This means that during the driving period, the input voltage VIP_N of the negative voltage buffer will be pulled to a voltage slightly lower than that of OUTN.

[0013] Preferably, when the peak current control circuit starts working, the input voltages VIP_P and VIP_N of the positive voltage buffer and the negative voltage buffer are first pulled to near 0V by OUTP and OUTN. Then, the buffer enable EN_OP changes from 0 to 1, and the positive and negative voltage buffers begin to operate. The input voltage VIP_P of the positive voltage buffer increases as the output voltage OUTP increases, and the input voltage VIP_N of the negative voltage buffer decreases as the output voltage OUTN decreases. As the operation progresses, when the output OUTP of the positive voltage buffer and the positive voltage on the channel load S2 gradually increase and slowly approach the input positive grayscale voltage VREFP, when the output OUTN of the negative voltage buffer and the positive voltage on the channel load S2 gradually increase and approach the input positive grayscale voltage VREFP, the output voltage VIP_P of the negative voltage buffer and the positive voltage on the channel load S2 gradually increase and approach the input positive grayscale voltage VREFP. As the negative voltage on channel load S1 gradually decreases and approaches the input negative grayscale voltage VREFN, the peak current control circuit enable EN changes from 1 to 0. The second PMOS transistor PM2, the seventh NMOS transistor NM7, the twelfth NMOS transistor NM12, and the seventeenth PMOS transistor PM17 change from being on to being off. The transmission gates TG_P and TG_N change from being off to being on. The positive and negative peak current control circuits stop working. At this time, the positive and negative voltage buffer input terminals VIP_P and VIP_N are strongly connected to the positive and negative grayscale voltages VREFP and VREFN through the transmission gates TG_P and TG_N. The positive and negative voltage buffers become ordinary buffer drive circuits and continue to drive the channel loads S1 and S2.

[0014] Preferably, when the peak current control circuit is working, for the positive peak current control circuit, VREFP and VIP_P are weakly connected through the second NMOS transistor NM2. This requires the second NMOS transistor NM2 to have a sufficiently large on-resistance Ron2. If Ron2 is too small, a current loop will be formed between the positive voltage buffer output terminal OUTP and the positive grayscale voltage VREFP through the second NMOS transistor NM2, the seventh NMOS transistor NM7, and the third NMOS transistor NM3. The loop current iref_p will become relatively large, adversely affecting the positive grayscale voltage VREFP. The gate and drain of the first NMOS transistor NM1 are shorted to form a diode structure, and the second N... The gate of MOSFET NM2 is connected to the gate of the first NMOS transistor NM1, and the source of the second NMOS transistor NM2 is connected to the source of the first NMOS transistor NM1. This means the on-resistance Ron2 of the second NMOS transistor NM2 is inversely proportional to the current ib_p flowing through the first NMOS transistor NM1. Meanwhile, the gate and drain of the zeroth PMOS transistor PM0 are shorted to form a diode structure. The gates of the first PMOS transistor PM1 and the zeroth PMOS transistor PM0 are connected to form a current mirror. The current ib_p is generated through ib replication. Therefore, by adjusting the magnitude of the current ib in the zeroth PMOS transistor PM0, the on-resistance Ron2 of the second NMOS transistor NM2 can be controlled, making Ron2... On2 has a sufficiently large on-resistance. For the negative peak current control circuit, VREFN and VIP_N are weakly connected through the twelfth PMOS transistor PM12. This requires the twelfth PMOS transistor PM12 to have a sufficiently large on-resistance Ron12. If Ron12 is too small, the negative voltage buffer output OUTN and the positive grayscale voltage VREFN will form a current loop through the twelfth PMOS transistor PM12, the seventeenth PMOS transistor PM17, and the thirteenth PMOS transistor PM13. The gate of the eleventh PMOS transistor PM11 and its drain are shorted to form a diode structure. The gate of the twelfth PMOS transistor PM12 is connected to the gate of the eleventh PMOS transistor PM11. The source of the twelfth PMOS transistor PM12 is connected to the source of the eleventh PMOS transistor PM11. That is, the on-resistance Ron12 of the twelfth PMOS transistor PM12 is inversely proportional to the current ib_n flowing through the eleventh PMOS transistor PM11. The gate and drain of the tenth NMOS transistor NM10 are shorted to form a diode structure. The gate of the eleventh NMOS transistor NM11 is connected to the gate of the tenth NMOS transistor NM10 to form a current mirror. The current ib_n is generated by ib replication. That is, by adjusting the magnitude of the NM0 current ib, the on-resistance Ron12 of the twelfth PMOS transistor PM12 can be controlled, so that Ron12 has a sufficiently large on-resistance.

[0015] Preferably, when the peak current control circuit is working, when the positive voltage buffer and negative voltage buffer are slowly driven to near the stable voltage under the control and regulation of the positive voltage buffer and negative peak current control circuit, the VIP_P and VIP_N voltages are required to recover to a state close to the grayscale voltages VREFP and VREFN; while the positive peak control circuit continuously injects ib_p current into the VIP_P node through the first PMOS transistor PM1, the second PMOS transistor PM2, and the first NMOS transistor NM1. When the positive voltage buffer is driven to near the stable voltage... At this time, the VIP_P voltage will be significantly higher than VREFP. To solve this problem, the source of the fourth NMOS transistor NM4 is grounded to GND, and the drain of the sixth NMOS transistor NM6 is connected to VIP_P. A current of magnitude ib_p is drawn from the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, and the sixth NMOS transistor NM6 to ground GND. At the same time, considering that when the positive input grayscale voltage VREFP is close to the power supply voltage VDP, the first PMOS transistor PM1, the second PMOS transistor PM2, and the first NMOS transistor NM1 will be cut off, resulting in a current ib_p. When p is zero, the VIP_P voltage is pulled low by the currents of the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, and the sixth NMOS transistor NM6. The fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are connected in series at the drain of the fourth NMOS transistor NM4. The gate voltage is connected to the DP_H1 and DP_H2 control signals. When the positive input grayscale voltage VREFP is too high, DP_H1 and DP_H2 change from 1 to 0, controlling the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 to turn off and cut off the ib_p current to ground. Meanwhile, in the negative peak control circuit, the eleventh NMOS transistor... MOSFETs NM11, NM12, and PM11 continuously inject ib_n current into the VIP_N node. When the negative voltage buffer is driven to near the stable voltage, the VIP_N voltage will be significantly higher than VREFN. At this time, the source of the fourteenth PMOS transistor PM14 is connected to the negative power supply VDN, and the drain of the sixteenth NMOS transistor NM16 is connected to VIP_N. A current of magnitude ib_n is drawn from the negative power supply VDN through the fourteenth PMOS transistor PM14, the fifteenth PMOS transistor PM15, and the sixteenth NMOS transistor NM16.When the negative input grayscale voltage VREFN approaches the power supply voltage VDN, the eleventh NMOS transistor NM11, the twelfth NMOS transistor NM12, and the eleventh PMOS transistor PM11 will be cut off, resulting in a zero current ib_n. This causes the VIP_N voltage to be pulled low by the currents of the fourteenth PMOS transistor PM14, the fifteenth PMOS transistor PM15, and the sixteenth NMOS transistor NM16. The drain of the fourteenth PMOS transistor PM14 is connected in series with the fifteenth PMOS transistor PM15 and the sixteenth NMOS transistor NM16. The gate voltage is connected to the DN_H1 and DN_H2 control signals. When the positive input grayscale voltage VREFN is too low, DN_H1 and DN_H2 change from 0 to 1, controlling the fifteenth PMOS transistor PM15 and the sixteenth NMOS transistor NM16 to turn off, cutting off the current from ib_n to VDN.

[0016] Preferably, when the enable signal EN of the positive and negative peak current control circuit changes from 1 to 0, the peak current control circuit stops working. At this time, the positive and negative voltage buffers become ordinary drive buffers and continue to drive the channel loads S1 and S2 with voltage until the end of this source drive cycle. The enable signal EN_OP of the positive voltage buffer and the negative voltage buffer changes from 1 to 0, causing the positive and negative voltage buffers to stop working, thus completing one drive cycle of the source basic unit. Then, the channel loads S1 and S2 are discharged to ground, and the next drive cycle of the source basic unit begins.

[0017] Existing technologies cannot effectively reduce the peak value of the source drive current, resulting in very limited reduction of EMI noise. This patent proposes a novel buffer circuit that can smoothly shape the drive current, greatly reducing the peak buffer drive current and significantly improving EMI noise. Attached Figure Description

[0018] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A block diagram of a control circuit for reducing the peak source drive current of a TFT-LCD driver chip, according to a specific embodiment of the present invention, is shown. Figure 2 A circuit diagram of a control circuit for reducing the peak current of the source drive in a TFT-LCD driver chip, according to a first embodiment of the present invention, is shown. Figure 3 This diagram illustrates a comparison of the driving voltage and current waveforms in the operating state of a control circuit for reducing the peak source driving current of a TFT-LCD driver chip, according to a first embodiment of the present invention; and Figure 4 A schematic diagram showing the comparison between the driving current magnitude and output voltage of a control circuit for reducing the peak source driving current of a TFT-LCD driver chip according to a first embodiment of the present invention during the driving load process. Detailed Implementation

[0019] To better illustrate the technical solution of the present invention, the present invention will be further described below with reference to the accompanying drawings.

[0020] Refer to the above Figures 1 to 4As understood by those skilled in the art, in the embodiment, the positive grayscale voltage VREFP is connected to the drain of the second NMOS transistor NM2, the source of the second NMOS transistor NM2 is connected to the drain of the seventh NMOS transistor NM7, the source of the seventh NMOS transistor NM7 is connected to the third NMOS transistor NM3, the source of the third NMOS transistor NM3 is connected to the output OUTP of the positive voltage buffer, and the source of the second NMOS transistor NM2 is connected to the input VIP_P of the positive voltage buffer, forming a current loop between the positive grayscale voltage VREFP and the output OUTP of the positive voltage buffer. This current is denoted as iref_p, and its magnitude is controlled by the first NMOS transistor. The magnitude of the current ib_p of NM1 is used to adjust the input voltage VIP_P through the output OUTP of the positive voltage buffer. The source of the first PMOS transistor PM1 is connected to the positive power supply VDP. The drain of the first PMOS transistor PM1 is connected to the second PMOS transistor PM2. The source of the second PMOS transistor PM2 is connected to the drain of the first NMOS transistor NM1. The source of the second NMOS transistor NM2 is connected in series with the seventh NMOS transistor NM7, the sixth NMOS transistor NM6, the fifth NMOS transistor NM5, and the fourth NMOS transistor NM4. The source of the fourth NMOS transistor NM4 is connected to ground GND. The source of the first NMOS transistor NM1 is connected to the input VIP_P of the positive voltage buffer, forming a... A current discharge path is established between the positive power supply VDP, VIP_P, and ground GND. This current is denoted as ib_p. The magnitude of the ib_p current is determined by the current mirror formed by the zeroth PMOS transistor PM0 and the first PMOS transistor PM1. ib_p can be adjusted by the current ib of the zeroth PMOS transistor PM0. This current discharge path prevents ib_p from affecting the input VIP_P of the positive voltage buffer. Furthermore, the operating state of the positive peak current control circuit is enabled by controlling the switching states of the seventh NMOS transistor NM7, the transmission gate TG_P, and the second PMOS transistor PM2. In the negative peak current control circuit, the negative grayscale voltage VREFN is connected to the drain of the twelfth PMOS transistor PM12. The source of the 12th PMOS transistor PM12 is connected to the drain of the 17th PMOS transistor PM17. The source of the 17th PMOS transistor PM17 is connected to the 13th PMOS transistor PM13. The source of the 13th PMOS transistor PM13 is connected to the output OUTN of the negative voltage buffer. The source of the 12th PMOS transistor PM12 is connected to the input VIP_N of the negative voltage buffer, forming a current loop between the negative grayscale voltage VREFN and the output OUTN of the negative voltage buffer. This current is denoted as iref_n. The magnitude of the iref_n current is controlled by the current ib_n of the 11th PMOS transistor PM11. That is, the input voltage VIP_N is adjusted through the output OUTN of the negative voltage buffer.The source of the eleventh NMOS transistor NM11 is grounded to GND. The drain of the eleventh NMOS transistor NM11 is connected to the twelfth NMOS transistor NM12. The source of the twelfth NMOS transistor NM12 is connected to the drain of the eleventh PMOS transistor PM11. The source of the twelfth PMOS transistor PM12 is connected in series with the seventeenth PMOS transistor PM17, the sixteenth NMOS transistor NM16, the fifteenth PMOS transistor PM15, and the fourteenth PMOS transistor PM14. The source of the fourteenth PMOS transistor PM14 is connected to the negative power supply VDN, and the source of the eleventh PMOS transistor PM11 is connected to the negative voltage buffer. The input VIP_N is connected, forming a current discharge path from GND to VIP_N and then to the negative power supply VDN. This current is ib_n, and its magnitude is determined by the current mirror formed by the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11. ib_n can be adjusted by the current ib of the tenth NMOS transistor NM10. This current discharge path prevents ib_n from affecting the input VIP_N of the negative voltage buffer. Furthermore, the switching states of the seventeenth PMOS transistor PM17, the transmission gate TG_N, and the twelfth NMOS transistor NM12 enable the control of the negative peak current control circuit.

[0021] Furthermore, those skilled in the art will understand that during one working cycle of the Source basic driving unit, the positive and negative voltage buffers will first shut down and stop working, and the discharge tubes CSP and CSN in the polarity switching circuit will be turned on to discharge the charge on the channel loads S1 and S2 to ground GND. Then, the polarity switching circuit will select the correct polarity path for the channel loads S1 and S2 to prepare for the positive and negative buffers to drive the channel loads S1 and S2.

[0022] When the positive and negative buffers begin driving channel loads S1 and S2, the positive and negative voltage buffers are enabled. At this time, the positive and negative voltage buffers output a large peak current to drive the channel loads S1 and S2, and the voltage on the channel loads S1 and S2 rises rapidly to a stable voltage value. The spike current control circuit operates at the initial moment when the positive and negative voltage buffers begin driving, effectively controlling the output current of the positive and negative voltage buffers and shaping the output current waveform to make the output current of the positive and negative voltage buffers very smooth without current peaks. When the channel loads S1 and S2 are driven to a stable voltage, the spike current control circuit is turned off, allowing the positive and negative voltage buffers to revert to normal buffer driving circuits and continue driving the channel loads until the end of one driving cycle, at which point the positive and negative voltage buffers are turned off, thus completing one cycle of driving the loads by the source basic driving unit.

[0023] Furthermore, when the enable signal EN_OP of the positive and negative voltage buffer changes from 1 to 0, the positive and negative voltage buffers stop working; at this time, switches PS1, PS2 and NS1, NS2 are in the open state, and switches PS3, PS4 and NS3, NS4 are in the closed state. The channel load S1 carries a positive voltage, and the channel load S2 carries a negative voltage; the peak current control circuit enable EN is 0, and the transmission gates TG_P and TG_N in the peak current control circuit are in the open state, sending the grayscale voltages VREFP and VREFN to the input of the positive and negative voltage buffers. With the VIP and VIN terminals closed, the second PMOS transistor PM2, the seventh NMOS transistor NM7, and the seventh PMOS transistor PM7 are all in the off state, thus turning off the peak current control circuit. At the same time, in the polarity switching circuit, one end of the ground discharge switches CSP and CSN is connected to ground, and the other end is connected to the load channels S1 and S2. The ground discharge switches CSP and CSN change from off to on, and the channel loads S1 and S2 begin to discharge to ground GND to 0V through PS2, PS4, CSP, NS2, NS4, and CSN.

[0024] Furthermore, after the channel loads S1 and S2 complete their discharge to ground, switches PS1, PS2 and NS1, NS2 in the polarity switching circuit change from open to closed, while switches PS3, PS4 and NS3, NS4 change from closed to open. The negative voltage buffer selects a negative polarity drive path for channel load S1 through NS3 and NS4, and the positive voltage buffer selects a positive polarity drive path for channel load S2 through PS3 and PS4. At this point, the source basic drive unit has completed the preparations before driving the positive and negative voltage buffers in this drive cycle and begins the driving phase of the positive and negative voltage buffers.

[0025] Furthermore, after the source basic driving unit completes the pre-driving preparations, the peak current control circuit enable EN changes from 0 to 1. In the positive and negative peak current control circuits, the transmission gates TG_P and TG_N change from on to off. The second PMOS transistor PM2, the seventh NMOS transistor NM7, the twelfth NMOS transistor NM12, and the seventeenth PMOS transistor PM17 change from off to on. The input grayscale voltage VREFP is weakly connected to the positive voltage buffer input terminal VIP_P through the second NMOS transistor NM2, and the input grayscale voltage VREFN is weakly connected to the negative voltage buffer input terminal VIP_N through the twelfth PMOS transistor PM12. The positive and negative peak current control circuits then begin operation. For the positive voltage buffer, the positive grayscale input voltage VREFP is connected to the positive voltage buffer output terminal OUTP through the second NMOS transistor NM2, the seventh NMOS transistor NM7, and the third NMOS transistor PM17. The S-channel transistor NM3 forms a current loop with a current magnitude of iref_p, and the MOSFET operates in the saturation region. At this time, the source of the third NMOS transistor NM3 is connected to OUTP, and OUTP is discharged to 0V. The drain of the third NMOS transistor NM3 is connected to the source of the seventh NMOS transistor NM7, and the drain of the seventh NMOS transistor NM7 is connected to the source of the second NMOS transistor NM2. The gate of the seventh NMOS transistor NM7 is connected to the gate of the second NMOS transistor NM2. The gate-source voltage difference of the third NMOS transistor NM3 is much greater than that of the second NMOS transistor NM2. The on-resistance Ron3 of the third NMOS transistor NM3 is much smaller than that of the second NMOS transistor NM2. At this time, the voltage at the input terminal VIP_P of the positive voltage buffer can be expressed as: VIP_P=Ron3 / (Ron2+Ron3)≈0V, Ron2>>Ron3. That is, the input voltage VIP_P of the positive voltage buffer will be pulled to a voltage slightly higher than OUTP during the driving period.For the negative voltage buffer, the negative grayscale input voltage VREFN and the output terminal OUTN of the negative voltage buffer are connected through the 12th PMOS transistor PM12, the 17th PMOS transistor PM17, and the 13th PMOS transistor PM13 to form a current loop with a current magnitude of iref_n. At this time, the source of the 13th PMOS transistor PM13 is connected to OUTN, and OUTN is discharged to 0V. The drain of the 13th PMOS transistor PM13 is connected to the source of the 17th PMOS transistor PM17, and the drain of the 17th PMOS transistor PM17 is connected to the source of the 12th PMOS transistor PM12. The gate of the 13th PMOS transistor PM13 is connected to the source of the 12th PMOS transistor PM12. The gate of transistor PM12 is connected to the gate of the thirteenth PMOS transistor PM13. The gate-source voltage of PM13 is much greater than that of PM12, and the on-resistance Ron13 of PM13 is much less than that of PM12. Therefore, the input voltage VIP_N of the negative voltage buffer can be expressed as: VIP_N = Ron13 / (Ron12 + Ron13) ≈ 0V, Ron12 >> Ron13. This means that during the driving period, the input voltage VIP_N of the negative voltage buffer will be pulled to a voltage slightly lower than that of OUTN.

[0026] Furthermore, when the peak current control circuit starts working, the input voltages VIP_P and VIP_N of the positive and negative voltage buffers are first pulled to near 0V by OUTP and OUTN. Then, the buffer enable EN_OP changes from 0 to 1, and the positive and negative voltage buffers begin to operate. The input voltage VIP_P of the positive voltage buffer increases as the output voltage OUTP increases, while the input voltage VIP_N of the negative voltage buffer decreases as the output voltage OUTN decreases. As the operation progresses, when the output OUTP of the positive voltage buffer and the positive voltage on the channel load S2 gradually increase and slowly approach the input positive grayscale voltage VREFP, when the output OUTN of the negative voltage buffer and the positive voltage on the channel load S2 gradually increase and approach the input positive grayscale voltage VREFP, the output voltage OUTN of the negative voltage buffer and the positive voltage on the channel load S2 gradually increase and approach the input positive grayscale voltage VREFP. As the negative voltage on load S1 gradually decreases and approaches the input negative grayscale voltage VREFN, the peak current control circuit enable EN changes from 1 to 0. The second PMOS transistor PM2, the seventh NMOS transistor NM7, the twelfth NMOS transistor NM12, and the seventeenth PMOS transistor PM17 change from being on to being off. The transmission gates TG_P and TG_N change from being off to being on. The positive and negative peak current control circuits stop working. At this time, the positive and negative voltage buffer input terminals VIP_P and VIP_N are strongly connected to the positive and negative grayscale voltages VREFP and VREFN through the transmission gates TG_P and TG_N. The positive and negative voltage buffers become ordinary buffer drive circuits and continue to drive the channel loads S1 and S2.

[0027] Furthermore, when the peak current control circuit is working, for the positive peak current control circuit, VREFP and VIP_P are weakly connected through the second NMOS transistor NM2. This requires the second NMOS transistor NM2 to have a sufficiently large on-resistance Ron2. If Ron2 is too small, a current loop will form between the positive voltage buffer output terminal OUTP and the positive grayscale voltage VREFP through the second NMOS transistor NM2, the seventh NMOS transistor NM7, and the third NMOS transistor NM3. The loop current iref_p will become relatively large, adversely affecting the positive grayscale voltage VREFP. The gate and drain of the first NMOS transistor NM1 are shorted to form a diode structure, and the gate of the second NMOS transistor NM2... The gate of the first NMOS transistor NM1 is connected to the gate of the second NMOS transistor NM2, and the source of the second NMOS transistor NM2 is connected to the source of the first NMOS transistor NM1. Therefore, the on-resistance Ron2 of the second NMOS transistor NM2 is inversely proportional to the current ib_p flowing through the first NMOS transistor NM1. The gate and drain of the zeroth PMOS transistor PM0 are shorted to form a diode structure. The gates of the first PMOS transistor PM1 and the zeroth PMOS transistor PM0 are connected to form a current mirror. The current ib_p is generated through ib replication. Therefore, by adjusting the magnitude of the current ib in the zeroth PMOS transistor PM0, the on-resistance Ron2 of the second NMOS transistor NM2 can be controlled, ensuring that Ron2 has a sufficiently large on-resistance. For negative peak values... In terms of the current control circuit, VREFN and VIP_N are weakly connected through the twelfth PMOS transistor PM12. This requires PM12 to have a sufficiently large on-resistance Ron12. If Ron12 is too small, a current loop will form between the negative voltage buffer output OUTN and the positive grayscale voltage VREFN through PM12, PM17, and PM13. The loop current iref_n will become relatively large, negatively impacting the negative grayscale voltage VREFN. The gate and drain of the eleventh PMOS transistor PM11 are shorted to form a diode structure. The gate of the twelfth PMOS transistor PM12 is connected to the eleventh PMOS transistor PM13. The gate of the S-channel transistor PM11 is connected to the source of the 12th PMOS transistor PM12, which is connected to the source of the 11th PMOS transistor PM11. That is, the on-resistance Ron12 of the 12th PMOS transistor PM12 is inversely proportional to the current ib_n flowing through the 11th PMOS transistor PM11. The gate and drain of the 10th NMOS transistor NM10 are shorted to form a diode structure. The gate of the 11th NMOS transistor NM11 is connected to the gate of the 10th NMOS transistor NM10 to form a current mirror. The current ib_n is generated by ib replication. That is, by adjusting the magnitude of the NM0 current ib, the on-resistance Ron12 of the 12th PMOS transistor PM12 can be controlled to make Ron12 have a sufficiently large on-resistance.

[0028] Refer to the above Figures 1 to 4As understood by those skilled in the art, when the peak current control circuit is operating, and the positive and negative voltage buffers are slowly driven to near the stable voltage under the control and adjustment of the positive and negative peak current control circuit, the VIP_P and VIP_N voltages are required to recover to a state close to the grayscale voltages VREFP and VREFN. Meanwhile, the positive peak control circuit continuously injects ib_p current into the VIP_P node through the first PMOS transistor PM1, the second PMOS transistor PM2, and the first NMOS transistor NM1. When the positive voltage buffer is driven to near the stable voltage... This would cause the VIP_P voltage to be significantly higher than VREFP. To solve this problem, the source of the fourth NMOS transistor NM4 is grounded to GND, and the drain of the sixth NMOS transistor NM6 is connected to VIP_P. A current of magnitude ib_p is drawn from the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, and the sixth NMOS transistor NM6 to ground GND. At the same time, considering that when the positive input grayscale voltage VREFP is close to the power supply voltage VDP, the first PMOS transistor PM1, the second PMOS transistor PM2, and the first NMOS transistor NM1 will be cut off, resulting in a current ib_p of zero. This situation causes the VIP_P voltage to be pulled low by the currents of the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, and the sixth NMOS transistor NM6. The fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are connected in series at the drain of the fourth NMOS transistor NM4. The gate voltage is connected to the DP_H1 and DP_H2 control signals. When the positive input grayscale voltage VREFP is too high, DP_H1 and DP_H2 change from 1 to 0, controlling the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 to turn off and cut off the ib_p current to ground. Meanwhile, in the negative peak control circuit, the eleventh NMOS transistor N... M11, the twelfth NMOS transistor NM12, and the eleventh PMOS transistor PM11 continuously inject ib_n current into the VIP_N node. When the negative voltage buffer is driven to near the stable voltage, the VIP_N voltage will be significantly higher than VREFN. To solve this problem, the source of the fourteenth PMOS transistor PM14 is connected to the negative power supply VDN, and the drain of the sixteenth NMOS transistor NM16 is connected to VIP_N. A current of magnitude ib_n is drawn from the negative power supply VDN through the fourteenth PMOS transistor PM14, the fifteenth PMOS transistor PM15, and the sixteenth NMOS transistor NM16.Simultaneously, considering that when the negative input grayscale voltage VREFN approaches the power supply voltage VDN, the eleventh NMOS transistor NM11, the twelfth NMOS transistor NM12, and the eleventh PMOS transistor PM11 will be cut off, resulting in a zero current ib_n. This causes the VIP_N voltage to be pulled low by the currents of the fourteenth PMOS transistor PM14, the fifteenth PMOS transistor PM15, and the sixteenth NMOS transistor NM16. The fifteenth PMOS transistor PM15 and the sixteenth NMOS transistor NM16 are connected in series at the drain of the fourteenth PMOS transistor PM14, and their gate voltages are connected to the DN_H1 and DN_H2 control signals. When the positive input grayscale voltage VREFN is too low, DN_H1 and DN_H2 change from 0 to 1, controlling the fifteenth PMOS transistor PM15 and the sixteenth NMOS transistor NM16 to turn off and cut off the current from ib_n to VDN.

[0029] Furthermore, when the enable signal EN of the positive and negative peak current control circuit changes from 1 to 0, the peak current control circuit stops working. At this time, the positive and negative voltage buffer becomes a normal drive buffer and continues to drive the channel loads S1 and S2 with voltage until the end of this source drive cycle. Then, the enable signal EN_OP of the positive and negative voltage buffer changes from 1 to 0, causing the positive and negative voltage buffer to stop working, thus completing one drive cycle of the source basic unit. Immediately afterwards, the channel loads S1 and S2 are discharged to ground, and the next drive cycle of the source basic unit begins.

[0030] Refer to the above Figures 1 to 4 As understood by those skilled in the art, the source drive circuit of the peak current control circuit greatly reduces the peak drive current of the positive and negative voltage buffers. Compared with ordinary buffer drive, the peak current can be reduced by more than 10 times. However, the time required to drive to a stable voltage is longer. In practical applications, the peak current magnitude and drive time must be balanced by adjusting the magnitude of the ib current according to the working requirements of the TFT-LCD display.

[0031] Refer to the above Figures 1 to 4 As will be understood by those skilled in the art, the technical objectives of this invention can also be achieved through the following technical approach: 1. Before the amplifier OP is enabled by the enable signal EN_OP, the buffer output voltage OUTP will be discharged to ground GND, the transmission gate TG will open, and the input reference voltage VREF will be sent to the non-inverting terminal VIP of OP. At this time, the second PMOS transistor PM2 and the seventh NMOS transistor NM7 will be turned off, and the current paths Ip and In will be turned off.

[0032] 2. The gate and drain of the first NMOS transistor NM1 are short-circuited to form a diode connection, which is connected to the gate of the second NMOS transistor NM2, providing a gate voltage bias for the second NMOS transistor NM2. The sources of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected together, ensuring that both NMOS transistors have the same Vgs voltage. In the on-state, they have the same on-resistance. That is, the on-resistance RsecondNMOS2 of the second NMOS transistor NM2 is controlled by controlling the current Ip of the first NMOS transistor NM1. Simultaneously, the gate voltage of the third NMOS transistor NM3 is connected to the gate of the first NMOS transistor NM1, making the Vgs voltage of the third NMOS transistor NM3 greater than that of the first NMOS transistor NM1. Therefore, the on-resistance RsecondNMOS2 of the second NMOS transistor NM2 will be much greater than the on-resistance RthirdNMOS3 of the third NMOS transistor NM3.

[0033] 3. When the OP starts working, the EN_OP signal changes from 0 to 1, and the OP begins to drive the load. Simultaneously, the transmission gate TG is turned off, and the second PMOS transistor PM2 and the seventh NMOS transistor NM7 are turned on. At this time, VREF and VIP are weakly connected through the second NMOS transistor NM2, opening the Ip and In current paths. Ip and In are set to be equal in magnitude, and this current is conducted to ground GND so that Ip and In do not affect the VIP voltage. In the initial stage of the OP driving the load, because the OP output voltage VOUTP is very small, a current path of Iin is formed between VREF and OUTP through the second NMOS transistor NM2, the seventh NMOS transistor NM7, and the third NMOS transistor NM3. As long as the on-resistance R of the second NMOS transistor NM2 is large enough, the current Iin will become very small, making the effect of OUTP on VREF negligible. The source of the third NMOS transistor NM3 is connected to OUTP, so its Vgs3 will be relatively large. The Vgs2 of the second NMOS transistor NM2 is clamped by the first NMOS transistor NM1, making Vgs2 smaller than Vgs3. This means the on-resistance R2 of the second NMOS transistor NM2 is much larger than the on-resistance R3 of the third NMOS transistor NM3. The voltage between VREF and OUTP is divided by the on-resistances R2 and R3 of the second and third NMOS transistors, respectively. Therefore, VIP = R3NM3 / (V2NM3 / V3NM3). (Rsecond NMOS transistor NM2 + Rthird NMOS transistor NM3), Iin = (VREF - OUTP) / (Rsecond NMOS transistor NM2 + Rthird NMOS transistor NM3). Since Rsecond NMOS transistor NM2 is very large and much larger than Rthird NMOS transistor NM3, VIP has a very small voltage in the initial stage of driving, close to VOUTP. Most of the voltage of VREF drops across the source and drain terminals of the second NMOS transistor NM2. By controlling the current Ip flowing through the first NMOS transistor NM1, the on-resistance Rsecond NMOS transistor NM2 can be controlled, thereby controlling the current Iin flowing through the second NMOS transistor NM2, making Iin small enough not to affect VREF.

[0034] 4. The current Ip flowing through the first PMOS transistor PM1 is equal in magnitude to the current In flowing through the fourth NMOS transistor NM4. This current is discharged to GND through the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, and the seventh NMOS transistor NM7 to prevent this current from affecting VIP. As the OP drives the load, the OP's output voltage OUTP gradually increases, causing Vgs3 of the third NMOS transistor NM3 to gradually decrease and the on-resistance R of the third NMOS transistor NM3 to gradually increase. Due to the voltage division relationship between the on-resistances R of the second NMOS transistor NM2 and R of the third NMOS transistor NM3, the VIP voltage increases as the VOUTP voltage increases. Since the OUTP voltage increases slowly with the VIP voltage, the OP's power supply current will not experience current spikes and will become very smooth.

[0035] 5. When the OP drives the load to near the stable voltage VREF, the VIP begins to approach VREF, and the control signal EN changes from 1 to 0. This turns off the second PMOS transistor PM2 and the seventh NMOS transistor NM7, thereby shutting off the Ip and In currents. The current path Iin between VREF and OUTP is also turned off. At the same time, the transmission gate TG opens, allowing VREF and VIP to be strongly connected through the transmission gate TG, and the OP becomes a normal buffer drive circuit.

[0036] This patent can effectively smooth and shape the source buffer drive current, preventing current spikes throughout the drive process. Compared to ordinary buffer drive, it can reduce the maximum current peak by 10 to 20 times, which can significantly solve the EMI noise interference problem caused by excessive current peaks during source drive of LCD TFT displays. At the same time, it greatly reduces the performance requirements of the driver chip for power transient response.

[0037] refer to Figure 4 It shows a comparison of the drive current and output voltage during the process of driving a load for a buffer, by Figure 4 As can be seen, the peak current is reduced by 15 times, and the solution proposed in this patent has a significant advantage.

[0038] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A control circuit for reducing the peak current of the source drive in a TFT-LCD driver chip, characterized in that, It includes at least one set of basic source driving units, wherein the set of basic source driving units includes at least one driving buffer circuit, one polarity switching control circuit, one positive peak current control circuit, one negative peak current control circuit, and two polarity load channels S1 and S2. The drive buffer circuit consists of a positive voltage buffer and a negative voltage buffer. The input voltage VIP_P of the positive voltage buffer is connected to the output of the positive peak current control circuit, and the input voltage VIP_N of the negative voltage buffer is connected to the output of the negative peak current control circuit. The input to the positive peak current control circuit is the positive grayscale voltage VREFP, and the input to the negative peak current control circuit is the negative grayscale voltage VREFN. The output OUTP of the positive voltage buffer and the output OUTN of the negative voltage buffer are connected to the input terminal of the polarity switching circuit, and the output terminal of the polarity switching circuit drives the channel loads S1 and S2 with voltage. When the peak current control circuit starts working, the input voltages VIP_P and VIP_N of the positive and negative voltage buffers are first pulled to near 0V by OUTP and OUTN. Then, the buffer enable EN_OP changes from 0 to 1, and the positive and negative voltage buffers begin to operate. The input voltage VIP_P of the positive voltage buffer increases as the output voltage OUTP increases, and the input voltage VIP_N of the negative voltage buffer decreases as the output voltage OUTN decreases. As the operation continues, when the positive voltage on the output OUTP of the positive voltage buffer and the positive voltage on the channel load S2 gradually increase and approach the input positive grayscale voltage VREFP, and when the negative voltage on the output OUTN of the negative voltage buffer and the negative voltage on the channel load S1 gradually decrease and approach the input negative grayscale voltage VREFN, the positive and negative peak current control circuits stop working.

2. The control circuit according to claim 1, characterized in that, In the positive peak current control circuit, the positive grayscale voltage VREFP is connected to the drain of the second NMOS transistor (NM2), the source of the second NMOS transistor (NM2) is connected to the drain of the seventh NMOS transistor (NM7), the source of the seventh NMOS transistor (NM7) is connected to the third NMOS transistor (NM3), the source of the third NMOS transistor (NM3) is connected to the output OUP of the positive voltage buffer, and the source of the second NMOS transistor (NM2) is connected to the input VIP_P of the positive voltage buffer, forming a current loop between the positive grayscale voltage VREFP and the output OUTP of the positive voltage buffer, with the corresponding current represented as iref_p; the source of the first PMOS transistor (PM1) is connected to the positive peak current control circuit. The power supply VDP is connected to the drain of the first PMOS transistor (PM1) and the source of the second PMOS transistor (PM2). The drain of the second PMOS transistor (PM2) is connected to the drain of the first NMOS transistor (NM1). The source of the second NMOS transistor (NM2) is connected in series with the seventh NMOS transistor (NM7), the sixth NMOS transistor (NM6), the fifth NMOS transistor (NM5), and the fourth NMOS transistor (NM4). The source of the fourth NMOS transistor (NM4) is connected to ground GND. The source of the first NMOS transistor (NM1) is connected to the positive voltage buffer input VIP_P, forming a current discharge path from the positive power supply VDP to VIP_P and then to ground GND. The corresponding current is represented as ib_p. In the negative peak current control circuit, the negative grayscale voltage VREFN is connected to the drain of the twelfth PMOS transistor (PM12), the source of the twelfth PMOS transistor (PM12) is connected to the drain of the seventeenth PMOS transistor (PM17), the source of the seventeenth PMOS transistor (PM17) is connected to the drain of the thirteenth PMOS transistor (PM13), the source of the thirteenth PMOS transistor (PM13) is connected to the output OUTN of the negative voltage buffer, and the source of the twelfth PMOS transistor (PM12) is connected to the input VIP_N of the negative voltage buffer, forming a current loop between the negative grayscale voltage VREFN and the output OUTN of the negative voltage buffer, with the corresponding current represented as iref_n; the source of the eleventh NMOS transistor (NM11) is grounded to G. ND, the drain of the eleventh NMOS transistor (NM11) is connected to the source of the twelfth NMOS transistor (NM12), the drain of the twelfth NMOS transistor (NM12) is connected to the drain of the eleventh PMOS transistor (PM11), the source of the twelfth PMOS transistor (PM12) is connected in series with the seventeenth PMOS transistor (PM17), the sixteenth PMOS transistor (PM16), the fifteenth PMOS transistor (PM15), and the fourteenth PMOS transistor (PM14), the source of the fourteenth PMOS transistor (PM14) is connected to the negative power supply VDN, and the source of the eleventh PMOS transistor (PM11) is connected to the negative voltage buffer input VIP_N, forming a current discharge path from GND to VIP_N and then to the negative power supply VDN, the corresponding current is represented as ib_n.

3. A control method for reducing the peak source drive current in a TFT-LCD driver chip, used in the control circuit of claim 1 or 2 to reduce the peak source drive current, characterized in that... During one working cycle of the Source basic drive unit, the positive voltage buffer and the negative voltage buffer will first turn off and stop working, and the discharge tubes CSP and CSN in the polarity switching circuit will turn on to discharge the charge on the channel loads S1 and S2 to ground GND. Then the polarity switching circuit selects the correct polarity path for the channel loads S1 and S2. When the positive voltage buffer and the negative voltage buffer start driving the channel loads S1 and S2, the positive voltage buffer and the negative voltage buffer are enabled, and the voltage on the channel loads S1 and S2 rises rapidly to a stable voltage value. When the channel loads S1 and S2 are driven to a stable voltage, the spike current control circuit is turned off, and the positive and negative voltage buffers are restored to normal buffer drive circuits to continue driving the channel loads until the end of a drive cycle. Then, the positive voltage buffer and the negative voltage buffer are turned off, thus completing one drive cycle of the source basic drive unit for the load.

4. The control method according to claim 3, characterized in that, When the enable signal EN_OP of the positive voltage buffer and the negative voltage buffer changes from 1 to 0, the positive voltage buffer and the negative voltage buffer stop working. At this time, switches PS1, PS2 and NS1, NS2 are in the open state, and switches PS3, PS4 and NS3, NS4 are in the closed state. The channel load S1 carries a positive voltage, and the channel load S2 carries a negative voltage. The enable signal EN of the peak current control circuit is 0, and the transmission gates TG_P and TG_N in the peak current control circuit are in the open state, sending the grayscale voltages VREFP and VREFN to the input terminals V of the positive and negative voltage buffers. IP and VIN, while the second PMOS transistor (PM2), the seventh NMOS transistor (NM7), and the second NMOS transistor (NM2) and the seventh PMOS transistor (PM7) are in the off state, so that the peak current control circuit is in the off state; at the same time, in the polarity switching circuit, one end of the ground discharge switch CSP and CSN is connected to ground, and the other end is connected to the load channels S1 and S2. The ground discharge switch CSP and CSN change from off to on, and the channel loads S1 and S2 begin to discharge to ground GND to 0V through PS2, PS4, CSP and NS2, NS4, CSN.

5. The control method according to claim 4, characterized in that, After the channel loads S1 and S2 complete their discharge to ground, switches PS1, PS2 and NS1, NS2 in the polarity switching circuit change from open to closed, and switches PS3, PS4 and NS3, NS4 change from closed to open. The negative voltage buffer selects the negative polarity driving path for the channel load S1 through NS3 and NS4, and the positive voltage buffer selects the positive polarity driving path for the channel load S2 through PS3 and PS4. At this time, the source basic driving unit has completed the preparation before driving the positive voltage buffer and the negative voltage buffer in this driving cycle, and begins to enter the driving stage of the positive voltage buffer and the negative voltage buffer.

6. The control method according to any one of claims 3 to 5, characterized in that, After the source basic driving unit completes the pre-driving preparations, the peak current control circuit's enable EN changes from 0 to 1. In the positive and negative peak current control circuits, the transmission gates TG_P and TG_N change from on to off. The second PMOS transistor (PM2), the seventh NMOS transistor (NM7), the twelfth NMOS transistor (NM12), and the seventeenth PMOS transistor (PM17) change from off to on. The input grayscale voltage VREFP is weakly connected to the positive voltage buffer input terminal VIP_P through the second NMOS transistor (NM2), and the input grayscale voltage VREFN is weakly connected to the negative voltage buffer input terminal VIP_N through the twelfth PMOS transistor (PM12). The positive and negative peak current control circuits then begin operation. For the positive voltage buffer, the positive grayscale input voltage VREFP and the positive voltage buffer output terminal OUTP are connected through the second NMOS transistor (NM2), the seventh NMOS transistor (NM7), and the third NMOS transistor (NM3) to form a current loop. The current magnitude is represented by iref_p, and the MOS transistor operates in the saturation region. At this time, the source of the third NMOS transistor (NM3) is connected to OUTP, and OUTP is discharged to 0V. The drain of the third NMOS transistor (NM3) is connected to the source of the seventh NMOS transistor (NM7), the drain of the seventh NMOS transistor (NM7) is connected to the source of the second NMOS transistor (NM2), and the gate of the third NMOS transistor (NM3) is connected to the gate of the second NMOS transistor (NM2). The source voltage difference is much greater than the gate-source voltage difference of the second NMOS transistor (NM2), and the on-resistance Ron3 of the third NMOS transistor (NM3) is much smaller than the on-resistance Ron2 of the second NMOS transistor (NM2). At this time, the voltage at the input terminal VIP_P of the positive voltage buffer can be expressed as: VIP_P=Ron3 / (Ron2+Ron3)≈0V, (Ron2>>Ron3). That is, the input voltage VIP_P of the positive voltage buffer will be pulled to a voltage slightly higher than OUTP during the driving period.For the negative voltage buffer, the negative grayscale input voltage VREFN and the output terminal OUTN of the negative voltage buffer are connected through the 12th PMOS transistor (PM12), 17th PMOS transistor (PM17), and 13th PMOS transistor (PM13) to form a current loop with a current magnitude of iref_n. At this time, the source of the 13th PMOS transistor (PM13) is connected to OUTN, and OUTN is discharged to 0V. The drain of the 13th PMOS transistor (PM13) is connected to the source of the 17th PMOS transistor (PM17), and the drain of the 17th PMOS transistor (PM17) is connected to the source of the 12th PMOS transistor (PM12). The gate of the thirteenth PMOS transistor (PM13) is connected to the gate of the twelfth PMOS transistor (PM12). The gate-source voltage of the thirteenth PMOS transistor (PM13) is much greater than that of the twelfth PMOS transistor (PM12), and the on-resistance Ron13 of the thirteenth PMOS transistor (PM13) is much smaller than that of the twelfth PMOS transistor (PM12). Therefore, the voltage at the input terminal VIP_N of the negative voltage buffer can be expressed as: VIP_N = Ron13 / (Ron12 + Ron13) ≈ 0V, (Ron12 >> Ron13). This means that during the driving period, the input voltage VIP_N of the negative voltage buffer will be pulled to a voltage slightly lower than that of OUTN.

7. The control method according to claim 6, characterized in that, When the peak current control circuit enable EN changes from 1 to 0, the second PMOS transistor (PM2), the seventh NMOS transistor (NM7), the twelfth NMOS transistor (NM12), and the seventeenth PMOS transistor (PM17) change from being on to being off, and the transmission gates TG_P and TG_N change from being off to being on. The positive and negative peak current control circuits stop working. At this time, the positive and negative voltage buffer input terminals VIP_P and VIP_N are strongly connected to the positive and negative grayscale voltages VREFP and VREFN through the transmission gates TG_P and TG_N. The positive and negative voltage buffers become ordinary buffer drive circuits and continue to drive the channel loads S1 and S2 with voltage.

8. The control method according to claim 6 or 7, characterized in that, When the peak current control circuit is working, for the positive peak current control circuit, VREFP and VIP_P are weakly connected through the second NMOS transistor (NM2). This requires the second NMOS transistor (NM2) to have a sufficiently large on-resistance Ron2. If Ron2 is too small, a current loop will form between the positive voltage buffer output terminal OUTP and the positive grayscale voltage VREFP through the second NMOS transistor (NM2), the seventh NMOS transistor (NM7), and the third NMOS transistor (NM3). The loop current iref_p will become relatively large, adversely affecting the positive grayscale voltage VREFP. The gate and drain of the first NMOS transistor (NM1) are shorted to form a diode structure, and the second NMOS transistor (NM2)... The gate of the second NMOS transistor (NM2) is connected to the gate of the first NMOS transistor (NM1), and the source of the second NMOS transistor (NM2) is connected to the source of the first NMOS transistor (NM1). Therefore, the on-resistance Ron2 of the second NMOS transistor (NM2) is inversely proportional to the current ib_p flowing through the first NMOS transistor (NM1). The gate and drain of the zeroth PMOS transistor (PM0) are shorted to form a diode structure. The gates of the first PMOS transistor (PM1) and the zeroth PMOS transistor (PM0) are connected to form a current mirror. The current ib_p is generated through ib replication. Therefore, by adjusting the magnitude of the current ib in the zeroth PMOS transistor (PM0), the on-resistance Ron2 of the second NMOS transistor (NM2) can be controlled, making Ron2... n2 has a sufficiently large on-resistance; for the negative peak current control circuit, VREFN and VIP_N are weakly connected through the twelfth PMOS transistor (PM12), requiring the twelfth PMOS transistor (PM12) to have a sufficiently large on-resistance Ron12. If Ron12 is too small, the negative voltage buffer output terminal OUTN and the positive gray-level voltage VREFN form a current loop through the twelfth PMOS transistor (PM12), the seventeenth PMOS transistor (PM17), and the thirteenth PMOS transistor (PM13); the gate of the eleventh PMOS transistor (PM11) is shorted to the drain to form a diode structure, and the gate of the twelfth PMOS transistor (PM12) is connected to the gate of the eleventh PMOS transistor (PM11). The source of the twelfth PMOS transistor (PM12) is connected to the source of the eleventh PMOS transistor (PM11), meaning that the on-resistance Ron12 of the twelfth PMOS transistor (PM12) is inversely proportional to the current ib_n flowing through the eleventh PMOS transistor (PM11). The gate and drain of the tenth NMOS transistor (NM10) are shorted to form a diode structure. The gate of the eleventh NMOS transistor (NM11) is connected to the gate of the tenth NMOS transistor (NM10) to form a current mirror. The current ib_n is generated by ib replication. That is, by adjusting the magnitude of the NM0 current ib, the on-resistance Ron12 of the twelfth PMOS transistor (PM12) can be controlled, so that Ron12 has a sufficiently large on-resistance.

9. The control method according to claim 7 or 8, characterized in that, When the peak current control circuit is working, under the control and regulation of the positive voltage buffer and negative voltage buffer, the channel loads S1 and S2 are slowly driven to near the stable voltage. This requires the VIP_P and VIP_N voltages to recover to a state close to the grayscale voltages VREFP and VREFN. However, the positive peak current control circuit continuously injects ib_p current into the VIP_P node through the first PMOS transistor (PM1), the second PMOS transistor (PM2), and the first NMOS transistor (NM1). When the positive voltage buffer is driven to near the stable voltage, this causes the VIP_P voltage to be significantly higher than VREFP. To solve this problem, the first... The source of the fourth NMOS transistor (NM4) is grounded to GND. The drain of the sixth NMOS transistor (NM6) is connected to the source of the seventh NMOS transistor (NM7), and the drain of the seventh NMOS transistor (NM7) is connected to VIP_P. A current of magnitude ib_p is drawn from the fourth NMOS transistor (NM4), the fifth NMOS transistor (NM5), and the sixth NMOS transistor (NM6) to GND. Simultaneously, considering that when the positive input grayscale voltage VREFP approaches the power supply voltage VDP, the first PMOS transistor (PM1), the second PMOS transistor (PM2), and the first NMOS transistor (NM1) will be cut off, resulting in a zero current ib_p, causing the current in VIP_P to... The voltage is pulled low by the currents of the fourth NMOS transistor (NM4), the fifth NMOS transistor (NM5), the sixth NMOS transistor (NM6), and the seventh NMOS transistor (NM7). The fifth NMOS transistor (NM5) and the sixth NMOS transistor (NM6) are connected in series at the drain of the fourth NMOS transistor (NM4). The gate voltage is connected to the DP_H1 and DP_H2 control signals. When the positive input grayscale voltage VREFP is too high, DP_H1 and DP_H2 change from 1 to 0, controlling the fifth NMOS transistor (NM5) and the sixth NMOS transistor (NM6) to turn off and cut off the ib_p current to ground. Meanwhile, in the negative peak control circuit, the eleventh NMOS transistor (NM11) and the twelfth NMOS transistor (NM7) are connected in series. The eleventh PMOS transistor (PM11) continuously injects ib_n current into the VIP_N node. When the negative voltage buffer is driven to near the stable voltage, the VIP_N voltage will be significantly higher than VREFN. At this time, the source of the fourteenth PMOS transistor (PM14) is connected to the negative power supply VDN, the drain of the sixteenth PMOS transistor (PM16) is connected to the source of the seventeenth PMOS transistor (PM17), and the drain of the seventeenth PMOS transistor (PM17) is connected to VIP_N. A current of magnitude ib_n is drawn from the negative power supply VDN through the fourteenth PMOS transistor (PM14), the fifteenth PMOS transistor (PM15), and the sixteenth PMOS transistor (PM16).When the negative input grayscale voltage VREFN approaches the power supply voltage VDN, the eleventh NMOS transistor (NM11), twelfth NMOS transistor (NM12), and eleventh PMOS transistor (PM11) will be cut off, resulting in a zero current ib_n. This causes the VIP_N voltage to be pulled low by the currents of the fourteenth PMOS transistor (PM14), fifteenth PMOS transistor (PM15), sixteenth PMOS transistor (PM16), and seventeenth PMOS transistor (PM17). The drain of the fourteenth PMOS transistor (PM14) is connected in series with the fifteenth PMOS transistor (PM15) and the sixteenth PMOS transistor (PM16). The gate voltage is connected to the DN_H1 and DN_H2 control signals. When the positive input grayscale voltage VREFN is too low, DN_H1 and DN_H2 change from 0 to 1, controlling the fifteenth PMOS transistor (PM15) and the sixteenth PMOS transistor (PM16) to turn off and cut off the current from ib_n to VDN.

10. The control method according to any one of claims 3 to 9, characterized in that, When the enable signal EN of the positive and negative peak current control circuit changes from 1 to 0, the peak current control circuit stops working. At this time, the positive and negative voltage buffers become ordinary drive buffers and continue to drive the channel loads S1 and S2 with voltage until the end of this source drive cycle. The enable signal EN_OP of the positive voltage buffer and the negative voltage buffer changes from 1 to 0, causing the positive and negative voltage buffers to stop working, thus completing one drive cycle of the source basic unit. Then, the channel loads S1 and S2 are discharged to ground, and the next drive cycle of the source basic unit begins.

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