Data processing method and apparatus, and related device

Abstract

The application provides a data processing method, device and related equipment, the method comprising: obtaining to-be-transmitted data comprising first data and second data; generating to-be-transmitted data blocks comprising first data blocks generated by the first data and second data blocks generated by the second data, and error correction data blocks corresponding thereto; the sum of the number of symbols in the second data blocks and the error correction data blocks is adapted to the data transmission amount of a data channel for transmitting redundant data, and the ratio of the number of symbols in the second data blocks and the error correction data blocks is less than or equal to 1:3; interleaving the error correction data blocks to obtain target data blocks comprising an effective data area and a redundant data area; the redundant data area is transmitted based on the data channel for transmitting redundant data, comprises multiple rows of data, the second data and the error correction data are included in at least one row of data, and only the error correction data is included in at least one row of data; and the target data blocks are transmitted to a preset device. The application can ensure error correction capability while transmitting more data.

Description

Technical Field

[0001] This application relates to the field of computer integrated circuit design and manufacturing technology, specifically to data processing methods, apparatus and related equipment. Background Technology

[0002] In computer systems, ECC (Error Correction Code) is a commonly used error correction technique used to detect and correct errors by adding redundant error correction data to the data. However, the addition of redundancy inevitably increases the overall size of the data, which to some extent reduces the actual amount of data that can be stored and transmitted, making it impossible to store and transmit more data.

[0003] Against this backdrop, how to provide a data processing method that can store and transmit more data while ensuring data transmission quality has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of this application provide a data processing method, apparatus, and related equipment to achieve the storage and transmission of more data while ensuring data transmission quality.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0006] In a first aspect, embodiments of this application provide a data processing method, including:

[0007] Acquire the data to be transmitted; wherein the data to be transmitted includes first data and second data;

[0008] Based on the data to be transmitted, a data block to be transmitted and an error correction data block corresponding to the data block to be transmitted are generated. The data block to be transmitted includes a first data block generated from the first data and a second data block generated from the second data. A data block to be transmitted and its corresponding error correction data block constitute an error correction data group. The sum of the number of symbols in the second data block and the number of symbols in the error correction data block is adapted to the data transmission volume of the data channel transmitting redundant data, and the ratio of the number of symbols in the second data block and the error correction data block is less than or equal to 1:3.

[0009] The error correction data group is interleaved to obtain a target data block, which includes an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data; wherein, the redundant data area is transmitted based on the data channel of the redundant data, and the redundant data area includes multiple rows of data, at least one row of data includes both the second data and the error correction data, and at least one row of data includes only the error correction data;

[0010] Based on the transmission rules of the target data block, the target data block is transmitted to a preset device.

[0011] Secondly, embodiments of this application provide a data processing method, including:

[0012] A target data block is obtained, which is obtained based on the interleaving of error correction data groups. The error correction data groups include a data block to be transmitted and a corresponding error correction data block. The data block to be transmitted includes a first data block generated from first data and a second data block generated from second data. The target data block includes an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data. The redundant data area is transmitted based on the data channel of the redundant data. The redundant data area includes multiple rows of data, at least one row of data includes both the second data and the error correction data, and at least one row of data includes only the error correction data.

[0013] The target data block is de-interleaved to obtain the error-corrected data group;

[0014] Based on the error correction data blocks in the error correction data group, correct the data errors of the data blocks to be transmitted in the error correction data group;

[0015] Based on the error-corrected data block to be transmitted, generate the data to be transmitted.

[0016] Thirdly, embodiments of this application provide a data processing apparatus, including:

[0017] A first data acquisition module is used to acquire data to be transmitted; wherein the data to be transmitted includes first data and second data;

[0018] The processing module is configured to generate a data block to be transmitted and an error correction data block corresponding to the data block to be transmitted based on the data to be transmitted. The data block to be transmitted includes a first data block generated from first data and a second data block generated from second data. A data block to be transmitted and its corresponding error correction data block constitute an error correction data group. The sum of the number of symbols in the second data block and the number of symbols in the error correction data block is adapted to the data transmission volume of the data channel transmitting redundant data, and the ratio of the number of symbols in the second data block and the error correction data block is less than or equal to 1:3.

[0019] An interleaving module is used to interleave the error correction data group to obtain a target data block. The target data block includes an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data. The redundant data area is transmitted based on the data channel of the redundant data. The redundant data area includes multiple rows of data. At least one row of data includes both the second data and the error correction data. At least one row of data includes only the error correction data.

[0020] The data transmission module is used to transmit the target data block to a preset device based on the transmission rules of the target data block.

[0021] Fourthly, embodiments of this application provide a data processing apparatus, including:

[0022] The second data acquisition module is used to acquire a target data block, which is obtained based on the interleaving of error correction data groups. The error correction data groups include a data block to be transmitted and a corresponding error correction data block. The data block to be transmitted includes a first data block generated from first data and a second data block generated from second data. The target data block includes an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data. The redundant data area is transmitted based on the data channel of the redundant data. The redundant data area includes multiple rows of data, at least one row of data includes both the second data and the error correction data, and at least one row of data includes only the error correction data.

[0023] The deinterleaving module is used to deinterleave the target data block to obtain the error-corrected data group;

[0024] The error correction module is used to correct data errors in the data block to be transmitted in the error correction data group based on the error correction data block in the error correction data group.

[0025] The data to be transmitted generation module is used to generate data to be transmitted based on the error-corrected data block.

[0026] Fifthly, embodiments of this application provide a memory controller.

[0027] The memory controller is configured with the data processing device as described in the third aspect above;

[0028] and / or

[0029] The memory controller is configured with the data processing device as described in the fourth aspect above.

[0030] Sixthly, embodiments of this application provide an electronic device including a memory controller as described in the fifth aspect above.

[0031] In a seventh aspect, embodiments of this application provide a storage medium that stores one or more computer-executable instructions. When the one or more computer-executable instructions are executed, they implement the data processing method as described in the first aspect above, and / or implement the data processing method as described in the second aspect above.

[0032] Eighthly, embodiments of this application provide a computer program product including one or more computer-executable instructions, wherein when the one or more computer-executable instructions are executed, they implement the data processing method as described in the first aspect above, and / or implement the data processing method as described in the second aspect above.

[0033] This application provides a data processing method, apparatus, and related equipment. The method includes: acquiring data to be transmitted; wherein the data to be transmitted includes first data and second data; generating a data block to be transmitted and an error correction data block corresponding to the data block based on the data to be transmitted, wherein the data block to be transmitted includes a first data block generated from the first data and a second data block generated from the second data, and a data block to be transmitted and its corresponding error correction data block constitute an error correction data group; wherein the sum of the number of symbols in the second data block and the number of symbols in the error correction data block is adapted to a data channel for transmitting redundant data. The data transmission volume is such that the ratio of the number of symbols in the second data block and the error correction data block is less than or equal to 1:3; the error correction data group is interleaved to obtain a target data block, which includes an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data; wherein the redundant data area is transmitted based on the redundant data data channel, and the redundant data area includes multiple rows of data, at least one row of data includes both the second data and the error correction data, and at least one row of data includes only the error correction data; based on the transmission rules of the target data block, the target data block is transmitted to a preset device.

[0034] As can be seen, the data processing method provided in this application embodiment adapts the sum of the number of symbols in the second data block and the number of symbols in the error correction data block to the data transmission volume of the data channel transmitting redundant data. In the data interleaving step, the error correction data and the second data are interleaved to obtain a redundant data area, which is transmitted based on the data channel transmitting redundant data. This enables the simultaneous transmission of error correction data and the second data in the data channel transmitting redundant data. Furthermore, by making the ratio of the number of symbols in the second data block and the error correction data block less than or equal to 1:3, and in the data interleaving step, ensuring that at least one row of data in the redundant data area of ​​the interleaved target data block includes both the second data and the error correction data, and that at least one row of data includes only the error correction data, the amount of error correction data is guaranteed, thereby transmitting more data while ensuring error correction capability. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0036] Figure 1 It is a diagram of a data structure;

[0037] Figure 2 This is a diagram of another data structure;

[0038] Figure 3 This is a schematic diagram of an optional flow of a data processing method provided in an embodiment of this application;

[0039] Figure 4 This is provided by the embodiments of this application. Figure 3 Optional schematic diagram of step S110;

[0040] Figure 5 This is an optional schematic diagram of the data processing flow provided in the embodiments of this application;

[0041] Figure 6 This is an optional schematic diagram of data interleaving provided in an embodiment of this application;

[0042] Figure 7 This is a schematic diagram of a burst length data structure provided in an embodiment of this application;

[0043] Figure 8 This is an optional schematic diagram of a hardware module provided in an embodiment of this application;

[0044] Figure 9This is a schematic diagram of an optional flow of another data processing method provided in an embodiment of this application;

[0045] Figure 10 This is an optional schematic diagram of another hardware module provided in an embodiment of this application;

[0046] Figure 11 This is a reference schematic diagram of a data structure for transmitting data to an X4 chip in a burst length, provided by an embodiment of this application.

[0047] Figure 12 This is a data structure reference diagram of four-channel RS8(20,17) encoded error-correcting data group interleaving with next burst length transmission provided in the embodiments of this application;

[0048] Figure 13 This is an optional block diagram of the data processing apparatus provided in the embodiments of this application;

[0049] Figure 14 This is an optional block diagram of another data processing device provided in the embodiments of this application. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0051] As described in the background section, ECC (Error Correction Code) is a commonly used error correction technique in computer systems, used to detect and correct errors by adding redundant error correction data to the data. However, the addition of redundancy inevitably increases the overall size of the data, thereby reducing the actual amount of data that can be stored and transmitted, making it impossible to store and transmit more data.

[0052] refer to Figure 1The diagram illustrates a data structure corresponding to an X4-chip (i.e., each memory chip has 4 transmission channels) data storage structure. This structure comprises 10 memory chips: 8 data chips (Data0, Data1, Data2, Data3, Data4, Data5, Data6, and Data7) and 2 ECC chips (ECC0 and ECC1). The data chips are memory chips storing valid data, and the ECC chips are memory chips storing error correction data. The 10 memory chips correspond to 40 transmission channels (i.e., 40-bit channels), supporting the transmission or reception of 512 bits of valid data and 128 bits of error correction data in a single Burst Length 16 transmission.

[0053] Burst Length refers to the number of consecutive data units (also called "bups") transmitted without changing the address. Burst Length 16 means transmitting 16 consecutive data units without changing the address. For example... Figure 1 Burst 0, Burst 1...Burst 15, where Burst 0 is the first data unit of the burst transmission, Burst 1 is the second data unit of the burst transmission, and so on, until Burst 15, which is the last data unit of the burst transmission.

[0054] In the data transmission / storage process, data is encoded and interleaved based on symbols as the smallest transmission / storage unit. In the data storage process, one symbol's data should be stored in one storage granularity. Figure 1 Taking an 8-bit symbol as an example, during the encoding and interleaving process, the data metadata is divided into two equal rows, each with 4 bits (the diagram only shows the configuration of symbol 1 marked by the diagonal in ECC 1; in reality, each Data / ECC region has one bit of metadata configured in every two rows), thus forming a structure like... Figure 1 The data structure shown is used to transmit / store the data in the data structure to the X4 chip based on the corresponding transmission channel.

[0055] In terms of storage and error correction capabilities, Figure 1 In the data structure shown, RS (Reed-Solomon code) encoding is used as an example (an encoding that uses 2t error correction symbols to correct t symbol errors, where t is a positive integer).

[0056] In one alternative implementation, the corresponding data transmission channel can be considered as 40-bit wide, where 8-bit is the ECC width. In RS encoding with 8 bits as a symbol, RS8(10,8) or RS16(10,8) encoding is applicable.

[0057] In RS8(10,8), RS8 indicates that RS encoding uses 8-bit symbols; the numbers in (10,8) represent the number of symbols, where 10 represents the total number of symbols (valid data symbols + ECC symbols), and 8 represents the number of valid data symbols. Similarly, in RS16(10,8), RS16 indicates that RS encoding uses 16-bit symbols (not shown in the diagram); the numbers in (10,8) represent the number of symbols, where 10 represents the total number of symbols (valid data symbols + ECC symbols), and 8 represents the number of valid data symbols.

[0058] In other words, including 8-bit ECC in each frame can correct 4-bit data. That is, even Figure 1 In the structure shown, if one of the X4 memory chips fails completely, the data of that X4 memory chip can be completely calculated using only ECC, thus achieving chipkill.

[0059] However, to correct 4-bit errors in every frame, an 8-bit ECC is required, leaving no spare bits for storing additional data. In other words, if 8 bits of a 40-bit data transmission channel are used as the ECC bit width, the error correction data will occupy the entire ECC space (i.e., ECC 0 + ECC 1), leaving no room to store additional information such as data attributes or tags.

[0060] In another alternative implementation, refer to Figure 2 Four bits of the 8-bit ECC width can be used to store additional information (such as...). Figure 2 The shaded area in the middle (the part with the diagonal line) only uses the remaining 4 bits for error correction (e.g., Figure 2 (Midpoint shaded area). However, 4-bit ECC cannot correct 4-bit errors and cannot achieve complete correction for a single X4 chip. Although this data structure can store additional information, its error correction capability is reduced, which can significantly impact system stability.

[0061] In RS encoding, which uses 8 bits as a code element, RS8(20,18) encoding is used. The specific meaning of RS8(20,18) can be found in the explanation of RS8(10,8) or RS16(10,8) in RS encoding above, and will not be repeated here.

[0062] It can be seen that using 4 bits of the 8-bit ECC width to store additional information and only using the remaining 4 bits for error correction can store an additional 64 bits of other information (such as encryption information, identification information, etc.), but this method comes at the cost of sacrificing error correction capability.

[0063] Understandably, the two methods described above either use data from two ECC bits to correct an error in one X4 memory chip, leaving no room for additional information; or they use data from one ECC bit to correct an error in half of an X4 memory chip, sacrificing error correction capability to store additional information. In other words, to utilize ECC bits to simultaneously achieve error correction and store additional information, a trade-off must be struck. If all ECC bits are used for error correction, there is no space left to store additional information. Conversely, if some ECC bits are reserved for storing additional information, the error correction capability will decrease accordingly.

[0064] In view of this, embodiments of this application provide a data processing method, apparatus, and related equipment. The method includes: acquiring data to be transmitted; the data to be transmitted includes first data and second data; based on the data to be transmitted, generating a data block to be transmitted and an error correction data block corresponding to the data block to be transmitted, wherein the data block to be transmitted includes a first data block generated from the first data and a second data block generated from the second data, and a data block to be transmitted and its corresponding error correction data block constitute an error correction data group; wherein the sum of the number of symbols in the second data block and the number of symbols in the error correction data block is adapted to the data communication of transmitting redundant data. The data transmission volume of the channel, and the ratio of the number of symbols of the second data block and the error correction data block is less than or equal to 1:3; the error correction data group is interleaved to obtain a target data block, the target data block including an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data; wherein, the redundant data area is transmitted based on the data channel of the redundant data, the redundant data area includes multiple rows of data, at least one row of data includes both the second data and the error correction data, and at least one row of data includes only the error correction data; based on the transmission rules of the target data block, the target data block is transmitted to a preset device.

[0065] As can be seen, the data processing method provided in this application embodiment adapts the sum of the number of symbols in the second data block and the number of symbols in the error correction data block to the data transmission volume of the data channel transmitting redundant data. In the data interleaving step, the error correction data and the second data are interleaved to obtain a redundant data area, which is transmitted based on the data channel transmitting redundant data. This enables the simultaneous transmission of error correction data and the second data in the data channel transmitting redundant data. Furthermore, by making the ratio of the number of symbols in the second data block and the error correction data block less than or equal to 1:3, and in the data interleaving step, ensuring that at least one row of data in the redundant data area of ​​the interleaved target data block includes both the second data and the error correction data, and that at least one row of data includes only the error correction data, the amount of error correction data is guaranteed, thereby transmitting more data while ensuring error correction capability.

[0066] To better understand the solutions provided in the embodiments of this application, the specific details of the data processing solutions will be further explained below.

[0067] In this application embodiment, a data processing method is provided, with reference to Figure 3 The diagram illustrates an optional flow chart of a data processing method, the method comprising:

[0068] Step S100: Obtain the data to be transmitted.

[0069] The data to be transmitted can refer to data prepared for transmission or data prepared for storage. The data to be transmitted includes first data and second data. Specifically, the first data can be binary data, and its corresponding data volume can be determined based on the data transmission mechanism or data storage mechanism of the hardware device. In an optional example, the data volume of the first data corresponds to the data volume that can be transmitted by a hardware burst length, such as 128 bits, 256 bits, or 512 bits. The second data can also be binary data, and its corresponding data volume can be determined based on a preset encoding method, the data volume of the first data, and the ratio of the number of symbols in the second data block to the number of symbols in the error correction data block. Taking RS8(20, 17) encoding, the first data block having a data size of 256 bits, and the ratio of the number of symbols in the second data block to the number of symbols in the error correction data block being 1:3 as an example, when the encoding is RS8(20, 17), the number of symbols in the error correction data block is 3, then the corresponding number of symbols in the second data block is 1 (the second data block has a data size of 8 bits), and the number of symbols in the first data block is 16 (the first data block has a data size of 128 bits).

[0070] The size of the second data needs to satisfy the condition that the number of subsequent second data blocks after partitioning is the same as the number of first data blocks after partitioning the first data. In the example above, the 256-bit first data can be partitioned into four 128-bit first data blocks, so the corresponding number of second data blocks is also four. At this time, the size of the second data is 32 bits (i.e., four 8-bit second data blocks).

[0071] The first data is valid data, the second data is valid data, or one or more of the following: identification data, attribute data, verification data, and encryption information corresponding to the valid data. The second data can be understood as additional data that can be transmitted or stored.

[0072] Step S110: Based on the data to be transmitted, generate a data block to be transmitted and an error correction data block corresponding to the data block to be transmitted.

[0073] The data block to be transmitted includes a first data block generated from first data and a second data block generated from second data. A data block to be transmitted and its corresponding error correction data block constitute an error correction data group. The first data block and the second data block are data blocks that conform to the data bit length requirements of a preset encoding method, and are used as the data to be transmitted part in the error correction data group, so that the data to be transmitted can be corrected based on the error correction data in the error correction data group in subsequent processes.

[0074] In the optional implementation, refer to Figure 4 The step of generating a data block to be transmitted and an error correction data block corresponding to the data block to be transmitted based on the data to be transmitted may include:

[0075] Step S111: Divide the first data into multiple first data blocks, and divide the second data into multiple second data blocks.

[0076] Among them, a first data block and a second data block are data blocks to be transmitted.

[0077] The step of dividing the first data into multiple first data blocks and the second data into multiple second data blocks specifically involves dividing the first data into multiple first data blocks with a first preset number of bits and dividing the second data into multiple second data blocks with a second preset number of bits. In this step, the number of first data blocks and the number of second data blocks can be determined based on the data volume of the first and second data and a preset encoding method. It should be noted that the number of first data blocks and the number of second data blocks are the same.

[0078] The error correction data block is a redundant data block obtained based on the data block to be transmitted and a specific encoding algorithm, used to correct errors in the data to be transmitted.

[0079] In some optional examples, a specific encoding algorithm can be determined based on hardware and system configuration, and that specific encoding algorithm can be fixedly configured in the hardware. For example, specific hardware can be configured as an encoding module to execute the specific encoding algorithm.

[0080] The error-correcting data block can be understood as an error-correcting data set corresponding to the data block to be transmitted. In this step, the sum of the number of symbols in the second data block and the number of symbols in the error-correcting data block is adapted to the data transmission volume of the data channel transmitting redundant data, and the ratio of the number of symbols in the second data block and the error-correcting data block is less than or equal to 1:3, for example, the ratio of the number of symbols in the second data block and the error-correcting data block is 1:3.

[0081] It is understandable that the number of first and second data blocks can be determined based on the data volume of the first and second data blocks and the preset encoding method. In this example, refer to... Figure 5 The illustrated optional data processing flow diagram takes as an example that the data to be transmitted includes 512 bits of first data and 32 bits of second data, with a code element ratio of 1:3 between the second data block and the error correction data block, and the encoding method is RS8(20, 17). The corresponding first and second data blocks have a total of 17 code elements: the first data block has 16 code elements (128 bits), the second data block has 1 code element (8 bits), and the error correction data block has 3 code elements (24 bits). The first data is divided into multiple first data blocks, and the second data is divided into multiple second data blocks, with the number of first data blocks being the same as the number of second data blocks. That is, the 512 bits of first data are divided into 4 first data blocks, and the 32 bits of second data are divided into 4 second data blocks. Each first data block and each second data block constitutes one data block to be transmitted.

[0082] Continue to refer to Figure 4 Step S112: Encode the data block to be transmitted to generate an error correction data block corresponding to the data block to be transmitted.

[0083] The error-correcting data block is redundant data obtained based on the data block to be transmitted and using a specific algorithm. A data block to be transmitted and its corresponding error-correcting data block constitute an error-correcting data group, thereby allowing error correction of the data to be transmitted to be performed based on the error-correcting data in the error-correcting data group.

[0084] Specifically, the error-correcting data block has nk symbols, corresponding to (nk)*m data bits and information bits, which can correct m bits of data from t symbols in the data to be transmitted. ((nk) is an integer multiple of 3).

[0085] It can be seen that the embodiments of this application break through the traditional RS coding theory (that is, the coding that uses 2t error correction symbols to correct t symbol errors, where t is a positive integer), and realizes the correction of 2t symbol errors using 3t error correction symbols.

[0086] The number of error-correcting data blocks is the same as the number of the first or second data blocks. In this example, continue to refer to... Figure 5 Taking a scenario where the data to be transmitted includes 512 bits of first data and 32 bits of second data, with a code element ratio of 1:3 between the second data block and the error correction data block, and the encoding method is RS8(20, 17), the corresponding first and second data blocks have a total of 17 code elements. Specifically, the first data block has 16 code elements (128 bits), and the second data block has 1 code element (8 bits). The corresponding error correction data block has 3 code elements (24 bits). Dividing the 512 bits of first data and the 32 bits of second data into 4 first data blocks and 4 second data blocks generates 4 corresponding error correction data blocks.

[0087] In a specific example, an encoding module can be configured in the hardware to calculate the error-correcting data block corresponding to the first and second data blocks. (See reference) Figure 8 The illustrated schematic diagram shows an optional hardware module provided in an embodiment of this application, which generates error correction data (also known as error correction code) based on the data to be transmitted by setting an encoding module.

[0088] Continue to refer to Figure 3 Step S120: Interweave the error-correcting data group to obtain the target data block.

[0089] The target data block includes a valid data area obtained by interleaving first data and a redundant data area obtained by interleaving error correction data and second data. The redundant data area is transmitted via a redundant data channel and includes multiple rows of data. At least one row includes both second data and error correction data, and at least one row includes only error correction data. The redundant data area also includes multiple columns of data, at least one column containing only error correction data, and at least one column alternating between error correction data and second data.

[0090] To adapt to the hardware bit width, the error correction data group can be interleaved into a target data block that conforms to the hardware bit width. In this embodiment, a symbol is averaged as two rows of data. For example, if a symbol in the first data is 01001010 (the symbol data from left to right is the first, second, ..., eighth bit), then this data is represented in the data block as an average configuration of two rows of data (for example, odd-numbered bits are arranged sequentially in the first row, and even-numbered bits are arranged sequentially in the second row; that is, the first row is 0011, and the second row is 1000).

[0091] The target data block may include one or more error correction data groups, the specific number of which is determined based on the number of bits in the symbols within the error correction data group. Specifically, for an 8-bit error correction data group with RS8(20,17) symbol encoding, two error correction data groups can be interleaved to form the target data block; for an 16-bit error correction data group with RS16(20,17) symbol encoding, one error correction data group can be interleaved to form the target data block.

[0092] Understandably, in the hardware transmission channels, some channels are used only for transmitting the first data, some for transmitting the second data and error correction data (with error correction data and second data alternating), and some for transmitting only error correction data. The channels used only for transmitting the first data are concentrated on one side to form the valid data area, while the channels used for transmitting the second data and error correction data, and the channels used only for transmitting error correction data, are concentrated on the other side to form the redundant data area. Correspondingly, in the specific interleaving process, the first data block is sequentially configured on one side of the target data block based on its symbol to form the valid data area, and the second data block and error correction data block are sequentially configured on the other side of the target data block based on its symbol to form the redundant data area.

[0093] In the specific interleaving process, the target data block includes at least one error correction data group, and the data in the error correction data group can be arranged sequentially based on the order of the error correction data group. It should be noted that the first data block, the second data block, and the error correction data block in the error correction data group should be configured separately. That is, the data in the first data block should be arranged on the side of the target data block used to configure the valid data area, and the data in the second data block and the error correction data block should be arranged on the side of the target data block used to configure the redundant data area.

[0094] refer to Figure 6The diagram shows an optional data interleaving scheme. The target data block includes two error correction data groups, namely the first error correction data group and the second error correction data group. Each error correction data group includes n symbols (n=20 in the diagram). The first k-1 symbols are the symbols in the first data block (k=17 in the diagram). One of the symbols from the kth to the nth symbols is the symbol in the second data block (kth symbol in the diagram). The symbols from the kth to the nth symbols, excluding those in the second data block, are the symbols in the error correction data block. The first (1) symbol represents the first symbol in the first error correction data group, the first (2) symbol represents the second symbol in the first error correction data group, the first (n) symbol represents the nth symbol in the first error correction data group, and so on. The second (n) symbol represents the nth symbol in the second error correction data group. n and k-1 are even numbers greater than 0.

[0095] The target data blocks are arranged sequentially based on the error correction data groups. Specifically, the first data block of each error correction data group is arranged sequentially on the side used to configure the valid data area, while the second and third data blocks are arranged sequentially on the side used to configure the redundant data area. For details, please refer to [link / reference]. Figure 6 Taking the aforementioned target data block as an example, which includes two error correction data groups, the result is as follows in the target data block:

[0096] In the target data block, the data blocks are arranged sequentially from top to bottom based on the order of the error correction data groups. The first data block is arranged sequentially on the side used to configure the valid data area, and the second data block and the error correction data block are arranged sequentially on the side used to configure the redundant data area.

[0097] like Figure 6 As shown, at least one row of data on the redundant data area side includes both the second data and the error correction data (e.g., ...). Figure 6 The data in the first, second, fifth, and sixth rows from top to bottom, and at least one row of data includes only error correction data (such as...). Figure 6 The data in the third, fourth, seventh, and eighth rows from top to bottom; at least one column of data should contain only error correction data (e.g., ...). Figure 6 In the first to fourth columns of data arranged from right to left, at least one column of data alternates between error-correction data and second data (e.g., ...). Figure 6 (Data in columns 5 through 8, arranged from right to left).

[0098] refer to Figure 8The illustrated embodiment of this application provides an optional hardware module. An encoding module is configured to generate error-correcting data based on the data to be transmitted. An interleaving module is connected to the encoding module, allowing the interleaving of the data to be transmitted (first data and second data) and the error-correcting data to be performed after the encoding module generates the error-correcting data block, thereby generating a target data block for transmission and storage in memory.

[0099] In this process, the column data in the target data block is aligned based on the hardware transmission channel. When there are multiple target data blocks, they are aligned based on the column direction, and the target data blocks are transmitted sequentially based on the hardware transmission channel.

[0100] Continue to refer to Figure 3 Step S130: Based on the transmission rules of the target data block, transmit the target data block to the preset device.

[0101] The data to be transmitted can refer to data that is prepared for transmission or data that is prepared for storage. Accordingly, the target data block obtained after processing the data to be transmitted can be used to transmit to a preset location (such as the data receiving end) or to transmit to memory and store.

[0102] The transmission rules for the target data blocks may include the correspondence between each column of data and the hardware port, thereby transmitting each column of data based on different hardware ports. Furthermore, the transmission rules may also include the number of target data blocks transmitted in a burst length; for example, when a burst length corresponds to the data volume of multiple target data blocks, the data of multiple target data blocks is transmitted sequentially corresponding to the burst length. (See reference) Figure 7 The number of target data blocks transmitted in one burst length can be 2. When the data volume of 2 target data blocks corresponds to one burst length, the data of 2 target data blocks are transmitted sequentially according to one burst length.

[0103] It should be noted that the target data block obtained after the data to be transmitted is required to undergo data decoding and error correction after being transmitted to the data receiving end, in order to determine whether there are any errors in the data transmission process and to correct any erroneous data. On the other hand, the target data block obtained after the data to be saved is saved after being transmitted to memory, and data decoding and error correction are required when reading it, in order to determine whether there are any errors in the saved data and to correct any erroneous data.

[0104] As can be seen, the data processing method provided in this application embodiment adapts the sum of the number of symbols in the second data block and the number of symbols in the error correction data block to the data transmission volume of the data channel transmitting redundant data. In the data interleaving step, the error correction data and the second data are interleaved to obtain a redundant data area, which is transmitted based on the data channel transmitting redundant data. This enables the simultaneous transmission of error correction data and the second data in the data channel transmitting redundant data. Furthermore, by making the ratio of the number of symbols in the second data block and the error correction data block less than or equal to 1:3, and in the data interleaving step, ensuring that at least one row of data in the redundant data area of ​​the interleaved target data block includes both the second data and the error correction data, and that at least one row of data includes only the error correction data, the amount of error correction data is guaranteed, thereby transmitting more data while ensuring error correction capability.

[0105] In a further example, embodiments of this application also provide a data processing method for correcting errors in data to be transmitted based on error correction data in a target data block. Specifically, refer to... Figure 9 The diagram illustrates an alternative flow chart of another data processing method, which includes:

[0106] Step S200: Obtain the target data block.

[0107] The target data block is data that has been encoded and interleaved and transmitted to a preset device, and is received by the preset device or obtained from the preset device. For example, the target data block can be data received by the receiving end, or it can be data stored in memory that is read from memory.

[0108] The target data block is obtained by interleaving error correction data groups, for example, by interleaving target data blocks using the method described in the aforementioned embodiments; the error correction data group includes a data block to be transmitted and a corresponding error correction data block, the data block to be transmitted includes a first data block generated from first data and a second data block generated from second data; the target data block includes an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data; wherein, the redundant data area is transmitted based on the data channel of the redundant data, the redundant data area includes multiple rows of data, at least one row of data includes both the second data and the error correction data, and at least one row of data includes only the error correction data; the redundant data area includes multiple columns of data, at least one column of data contains only the error correction data, and at least one column of data contains alternating rows of error correction data and the second data.

[0109] In the process of acquiring the target data block, acquisition can be based on hardware transmission rules. These transmission rules may include acquiring data from different hardware ports based on the correspondence between each column of data and the hardware port. Specifically, different data in the target data block are transmitted through different transmission channels. That is, in the hardware transmission channels, some channels are used only for transmitting the first data, some channels are used for transmitting error correction data and the second data (alternating between error correction data and the second data), and some channels are used only for transmitting error correction data. Correspondingly, in the specific acquisition process, the data acquired from the transmission channel that only transmits the first data is the data in the first data block; the data acquired from the transmission channel that transmits the error correction data and the second data are the data in the error correction data block and the second data block, and the data acquired from the transmission channel that only transmits the error correction data is the data in the error correction data block. (Reference) Figure 10 The diagram shows another optional structure of the hardware module. Taking reading data from memory as an example, the first data, the second data, and the error correction data can be distinguished based on the data transmission channel during the reading process.

[0110] Furthermore, the transmission rule may further include the number of target data blocks transmitted based on a burst length, and obtaining the corresponding number of target data blocks. For example, when a burst length corresponds to multiple (e.g., 2) target data blocks, the data of multiple (e.g., 2) target data blocks are transmitted sequentially corresponding to a burst length.

[0111] In this process, the column data in the target data block is aligned based on the hardware transmission channel. When there are multiple target data blocks, they are aligned based on the column direction. Therefore, the target data blocks can be obtained sequentially based on the data transmission order in the hardware transmission channel.

[0112] It should be noted that when there are multiple target data blocks corresponding to a burst length of data, that is, when there are multiple target data blocks transmitted in a burst length, and the corresponding storage granular data transmitted within a burst length corresponds to the symbols of multiple target data blocks, the processing flow of this step may include: obtaining data of a burst length; dividing the data of the burst length into multiple target data blocks based on the symbol length in the target data blocks, and thus obtaining the multiple target data blocks.

[0113] Continue to refer to Figure 9 Step S210: Deinterleave the target data block to obtain an error-corrected data group.

[0114] The error correction data group includes a data block to be transmitted and a corresponding error correction data block. The data block to be transmitted includes a first data block generated from first data and a second data block generated from second data. The first and second data blocks are data blocks of the required number of bits based on a preset encoding method, obtained by segmenting the data to be transmitted. The error correction data block is a redundant data block obtained based on the data in the data block to be transmitted and using a specific encoding algorithm.

[0115] In the specific deinterleaving process, the target data block includes at least one error correction data group. This step can determine the code data and its corresponding arrangement order in the same error correction data group based on a preset data arrangement order (e.g., the reverse order of data arrangement in the interleaving process).

[0116] Specifically, when the data of the error correction data group in the target data block are arranged sequentially based on the order of the error correction data group, the first data block and / or the second data block and / or the error correction data block in the error correction data group can be extracted sequentially.

[0117] The arrangement of the first data block, the second data block, and the error correction data block in the target data block is detailed in the preceding description. Based on this arrangement, the arrangement of symbols belonging to the same error correction data group in the target data block can be determined, and thus the deinterleaving of the target data block can be performed based on this symbol arrangement.

[0118] Continue to refer to Figure 9 Step S220: Based on the error correction data block in the error correction data group, correct the data error of the data block to be transmitted in the error correction data group.

[0119] The error-correcting data block is a redundant data block obtained based on the data in the data block to be transmitted, using a specific encoding algorithm. Correspondingly, error correction can be performed on the data block to be transmitted based on a specific decoding algorithm.

[0120] It is understood that the specific encoding algorithm can perform error correction on the data block to be transmitted based on its corresponding specific decoding algorithm. In hardware, given a specific encoding algorithm, the corresponding specific decoding algorithm is also determined. Accordingly, the specific decoding algorithm can be fixedly configured in the hardware; for example, specific hardware can be configured as a decoding module to execute the specific decoding algorithm. (Reference) Figure 10 Configure a decoding module to decode the data. This decoding module can be connected to the deinterleaving module to decode the deinterleaved data.

[0121] Specifically, correcting data errors in the data block to be transmitted in the error correction data group in this step may include the following process: based on the error correction data block in the error correction data group, calculate the location of the erroneous data in the data block to be transmitted; correct the data error at the location of the erroneous data in the data block to be transmitted.

[0122] Understandably, based on a specific decoding algorithm, by calculating the first data in the first data block, the second data in the second data block, and the error correction data in the error correction data block, the location of the erroneous data in the data block to be transmitted can be determined. In binary data, data is either "0" or "1". Therefore, after determining the location of the erroneous data in the data block to be transmitted, the data at that location can be corrected by converting the erroneous data. For example, when the erroneous data is "0", it can be converted to "1", or when the erroneous data is "1", it can be converted to "0".

[0123] In one alternative implementation, the method for calculating the location of erroneous data in the data block to be transmitted may, for example, utilize concomitant data to determine the location and value of the error.

[0124] Taking RS8(20, 17) encoding as an example, the corresponding data block to be transmitted has a total of 17 code elements. The first data block has 16 code elements, totaling 128 bits; the second data block has 1 code element, totaling 8 bits. The corresponding error correction data block has 3 code elements, totaling 24 bits. The specific implementation of using syntactic data to determine the error location and error value can be as follows:

[0125] (1) Calculate the syndrome; the syndrome data are (s0, s1, s2), where,

[0126] s0 = 2 0 e i +2 0 e j s1 = 2 i e i +2 i+1 e j s2 = 2 2i e i +2 2(i+1) e j ,

[0127] Among them, e i For the error value at error location i, e j The error value is at position i+1.

[0128] (2) Using the adjoint data, a multiple equation can be constructed, for example, a quadratic equation, ax 2+bx+c=0, where a=2s0, b=3s1, c=s2. Therefore, the error location and error value can be solved based on the aforementioned polynomial equation.

[0129] In some embodiments, the multiple equations may be quadratic equations. In other embodiments, other equations (e.g., cubic equations) or combinations of different types of equations (e.g., combinations of quadratic and cubic equations) can be constructed using the adjoint data. Additionally, error locations and error values ​​can be solved using methods other than equations (e.g., lookup tables) based on the adjoint data.

[0130] Based on the quadratic equation constructed above, ax 2 +bx+c=0, where a=2s0, b=3s1, c=s2. Using the finite field quadratic equation solution method, we can find two solutions x0 and x1 for x. A finite field, also called a Galois field, is a field containing only a finite number of elements. For example, it can be written as GF(2... n ), where n represents the number of bits in the field.

[0131] (3) Obtain the two solutions x0 and x1 of the quadratic equation, and determine the valid solution and the error location. Wherein, according to x = 2 i We obtain the value of i. If i is even and i < 20, then the valid solution is x, and the error positions are i and i+1. Specifically, when x0 is a valid solution, the error positions are i0 and i0+1; when x1 is a valid solution, the error positions are i1 and i1+1.

[0132] It is understandable that, when determining whether the two solutions x0 and x1 of the quadratic equation are valid solutions, it is necessary to substitute the two solutions x0 and x1 into x = 2. i To find the value of i, we need to find the corresponding value of x. Only when i is even and i < 20 is the corresponding x a valid solution, thus identifying the error positions as i and i+1. For example, to determine whether x0 is a valid solution, we need to substitute x0 into x = 2. i We obtain i0. Only when i0 is even and i0 < 20 is x0 a valid solution, thus identifying the error positions as i0 and i0+1. Similarly, to determine if x1 is a valid solution, we need to substitute x1 into x = 2. i We obtain i1. Only when i1 is even and i1 < 20 is x1 a valid solution, and thus we can determine the error positions as i1 and i1+1.

[0133] (4) The error value is calculated based on the number of valid solutions. The process for calculating the error value differs depending on the number of valid solutions. Therefore, the valid solutions can be categorized into three cases based on their number:

[0134] Case 1: The number of valid solutions is 0;

[0135] Case 2: The number of valid solutions is 1;

[0136] Case 3: There are 2 valid solutions.

[0137] The following section provides a detailed explanation of how to solve for the error value in cases 1, 2, and 3.

[0138] For case 1, if the number of valid solutions is 0 (neither x0 nor x1 is a valid solution), it indicates that the error is uncorrectable, and the error correction process ends.

[0139] For case 2, if the number of valid solutions is 1 (x0 is a valid solution, or x1 is a valid solution), then the error value e is calculated based on the valid solution and the adjoint data. i With e j ,in:

[0140] e j =e i +s0; where x0 is a valid solution, In the given equation, x is x0, and when x1 is a valid solution, In this context, x is x1.

[0141] In an optional implementation, the method to correct data errors at erroneous data positions in the data block to be transmitted can be: compare the data at position i with the data at position e. i Perform an XOR operation, combining the data at position i+1 with e. j Perform an XOR operation to obtain the corrected data, where i and i+1 are the error positions.

[0142] When x0 is a valid solution, the error positions are i0 and i0+1; when x1 is a valid solution, the error positions are i1 and i1+1.

[0143] For case 3, if the number of valid solutions is 2 (x0 and x1 are both valid solutions), then it is further determined whether the second data contains a check bit. Based on whether the second data contains a check bit, there are two cases:

[0144] Case 3.1: If there are two valid solutions (x0 and x1 are both valid solutions), and the second data contains a check bit, then the error value is calculated based on the valid solutions and the syndrome data. and in:

[0145]

[0146] In an optional implementation, the method to correct data errors at erroneous data positions in the data block to be transmitted can be: compare the data at position i0 with... Perform an XOR operation, combining the data at position i0+1 with... Perform an XOR operation to obtain the first data set; then AND the data at position i1 with... Perform an XOR operation, combining the data at position i1+1 with... Perform an XOR operation to obtain a second data group; substitute the first and second data groups into the check bit operation; if only one of the values ​​of the first and second data groups after the operation is equal to the check bit, then this data group is used as the corrected data; if neither the first nor the second data group is equal to the check bit after the operation, or if both the first and second data groups are equal to the check bit after the operation, then the error is an uncorrectable error, and the error correction process ends. Wherein, when x0 is a valid solution, the error positions are i0 and i0+1; when x1 is a valid solution, the error positions are i1 and i1+1.

[0147] It should be noted that substituting the first data group and the second data group into the check bit operation can be understood as the check bit in the second data being obtained through a certain calculation method (such as parity check), and this calculation method can be applied to the first data group and the second data group.

[0148] Case 3.2: If there are two valid solutions (x0 and x1 are both valid solutions) and there is no check bit in the second data, it indicates that the error is uncorrectable and the error correction process ends.

[0149] The method described above for calculating the location of erroneous data in the data block to be transmitted is only one optional example. Other methods can also be used to solve the problem, and this application does not limit the method.

[0150] In hardware, an error correction module can be fixedly configured to correct errors in the data to be transmitted. (See reference) Figure 10 Configure an error correction module connected to the decoding module so that errors in the data can be corrected through the error correction module.

[0151] Continue to refer to Figure 9 Step S230: Generate data to be transmitted based on the corrected data block to be transmitted.

[0152] The data to be transmitted can be understood as data waiting to be transmitted in the data transmission process, or data to be saved before being stored in memory in the process of data storage to memory. In a specific example, when the data to be transmitted includes multiple first data blocks and second data blocks, the first data blocks and second data blocks can be combined based on preset rules to generate the data to be transmitted, thereby transmitting the data to be transmitted to the target device, such as to the CPU (Central Processing Unit).

[0153] Below, based on specific examples, we will further explain the data processing method and its corresponding effects in the scenario where data is stored in memory, according to the embodiments of this application.

[0154] In this example, the error correction data group interleaving can be either two RS8 (20, 17) encoded error correction data groups or one RS16 (20, 17) encoded error correction data group. Regardless of the interleaving method, it can correct errors across the entire memory chip, achieving chipkill. The erroneous code data can reside in the same memory chip or in different memory chips.

[0155] The interleaving method in this example can correspond to 8 bits, 16 bits, etc. (Refer to...) Figure 11 The diagram illustrates a data structure for transmission to an X4 chip in a burst length, with data types of 8 bits and 16 bits from left to right. The burst length can be 8 bits, 16 bits, etc.; the diagram uses 16 bits as an example. When the data type is 8 bits, the reference... Figure 11 The shaded area shown in symbol 3 indicates that one symbol is averaged as two rows of data (i.e., arranged in a row direction); when the symbol data is 16 bits, refer to... Figure 11 The shaded area shown in symbol 4 indicates that one symbol is configured with an average of 4 rows of data (i.e., arranged in the row direction).

[0156] Taking an 8-bit symbol as an example, where the first data in the data to be transmitted is 512 bits, Figure 12 A reference diagram of the data structure for transmission of a burst-length data block with four RS8 (20, 17) encoded error-correcting data blocks interleaved is shown. Burst 0-7 is the first eight beats, corresponding to the transmission of one target data block, and Burst 8-15 is the last eight beats, corresponding to the transmission of another target data block.

[0157] As can be seen, the 8-bit data corresponding to two adjacent frames of a storage chip is one 8-bit symbol. There are two error correction data groups interleaved in the first eight frames. In the target data block, the 32 columns on the left are used to configure the first data, and the 8 columns on the right are used to configure the second data and error correction data. In the specific storage chip, the 0-7 of the X4 chip (Data 0, Data 1, Data 2, Data 3, Data 4, Data 5, Data 6 and Data 7 in the figure) can be used as the storage location corresponding to the first data of the target data block, and the 8-9 of the X4 chip (ECC 0 and ECC 1 in the figure) can be used as the storage location corresponding to the second data and error correction data of the target data block.

[0158] Continue to refer to Figure 12 A first data block is defined as 0-127 in the first data of the target data block, a second data block is defined as 0-7 in the error correction data, and an error correction data block is defined as 8-31 in the error correction data. This first data block, second data block, and error correction data block can be used as error correction data group 0. A second data block is defined as 128-255 in the first data, a second data block is defined as 32-39 in the error correction data, and an error correction data block is defined as 40-63 in the error correction data. This first data block, second data block, and error correction data block can be used as error correction data group 1.

[0159] In this target data block, each error correction data group uses RS8(20,17) error correction code, which can correct any two adjacent 8-bit symbols. In other words, any error that occurs in any memory chip can be corrected by using RS8(20,17) error correction code.

[0160] Specifically, taking the errors in 0-7 and 64-71 in the first data (i.e., a total of 2 8-bit symbols are wrong, as shown in the shaded area of ​​the grid in the figure) as an example, 0-7 and 64-71 in the original data all belong to error correction data group 0. Based on an error correction data group, any two adjacent 8-bit symbols can be corrected, and the above-mentioned erroneous data can all be corrected.

[0161] It is understood that the data mapping and error correction capabilities of the target data blocks corresponding to the first eight and the last eight are completely consistent. Therefore, the solution provided in this application embodiment can correct all errors of any memory chip and achieve chipkill.

[0162] As can be seen, the data processing method provided in this application embodiment adapts the sum of the number of symbols in the second data block and the number of symbols in the error correction data block to the data transmission volume of the data channel transmitting redundant data. In the data interleaving step, the error correction data and the second data are interleaved to obtain a redundant data area, which is transmitted based on the data channel transmitting redundant data. This enables the simultaneous transmission of error correction data and the second data in the data channel transmitting redundant data. Furthermore, by making the ratio of the number of symbols in the second data block and the error correction data block less than or equal to 1:3, and in the data interleaving step, ensuring that at least one row of data in the redundant data area of ​​the interleaved target data block includes both the second data and the error correction data, and that at least one row of data includes only the error correction data, the amount of error correction data is guaranteed, thereby transmitting more second data while ensuring error correction capability.

[0163] The data processing apparatus provided in the embodiments of this application will be described below. The data processing apparatus described below can be considered as a software or hardware functional module required to implement the data processing method provided in the embodiments of this application. The content of the data processing apparatus described below can be referred to in correspondence with the content of the method and hardware module described above.

[0164] In the optional implementation, Figure 13 An optional block diagram of a data processing apparatus provided in an embodiment of this application is shown. The data processing apparatus is used to implement a data processing method with data interleaving, such as... Figure 13 As shown, the data processing apparatus may include:

[0165] The first data acquisition module 300 is used to acquire data to be transmitted; wherein the data to be transmitted includes first data and second data.

[0166] The processing module 310 is configured to generate a data block to be transmitted and an error correction data block corresponding to the data block to be transmitted based on the data to be transmitted. The data block to be transmitted includes a first data block generated from first data and a second data block generated from second data. A data block to be transmitted and its corresponding error correction data block constitute an error correction data group. The sum of the number of symbols in the second data block and the number of symbols in the error correction data block is adapted to the data transmission volume of the data channel transmitting redundant data, and the ratio of the number of symbols in the second data block and the error correction data block is less than or equal to 1:3.

[0167] The interleaving module 320 is used to interleave the error correction data group to obtain a target data block. The target data block includes an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data. The redundant data area is transmitted based on the data channel of the redundant data. The redundant data area includes multiple rows of data. At least one row of data includes both the second data and the error correction data. At least one row of data includes only the error correction data.

[0168] The data transmission module 330 is used to transmit the target data block to a preset device based on the transmission rules of the target data block.

[0169] Optionally, the redundant data area includes multiple columns of data, at least one column of data contains only error correction data, and in at least one column of data, error correction data and second data are arranged alternately.

[0170] Optionally, the processing module 310, configured to generate a data block to be transmitted and an error correction data block corresponding to the data block to be transmitted based on the data to be transmitted, may include:

[0171] The first data is divided into multiple first data blocks, and the second data is divided into multiple second data blocks. A first data block and a second data block constitute a data block to be transmitted; wherein the number of first data blocks is the same as the number of second data blocks.

[0172] The data block to be transmitted is encoded to generate an error correction data block corresponding to the data block to be transmitted.

[0173] Optionally, dividing the first data into multiple first data blocks and dividing the second data into multiple second data blocks specifically involves dividing the first data into multiple first data blocks with a first preset number of bits and dividing the second data into multiple second data blocks with a second preset number of bits.

[0174] Optionally, the target data block includes at least one error correction data group, and the interleaving module 320 is used to interleave the error correction data group to obtain the target data block, specifically by arranging the data of the error correction data group in sequence based on the order of the error correction data group.

[0175] Optionally, the target data block includes two error correction data groups, namely a first error correction data group and a second error correction data group. Each error correction data group includes n code elements. The first k-1 code elements are the code elements in the first data block, one of the code elements from the kth code element to the nth code element is the code element in the second data block, and the code elements from the kth code element to the nth code element excluding the code elements that are in the second data block are the code elements in the error correction data block.

[0176] Here, the first n-th code element represents the nth code element in the first error correction data group, and the second n-th code element represents the nth code element in the second error correction data group, where n and k-1 are even numbers greater than 0.

[0177] Optionally, the first data is valid data, the second data is valid data, or one or more of the following: identification data, attribute data, verification data, and encryption information corresponding to the valid data.

[0178] Optionally, a burst length corresponds to the data volume of multiple target data blocks. The data transmission module 330 is used to transmit the target data blocks to a preset device based on the transmission rules of the target data blocks. Specifically, it transmits the data of multiple target data blocks sequentially within a burst length.

[0179] In the optional implementation, Figure 14 This illustration shows an optional block diagram of another data processing apparatus provided in an embodiment of this application, the data processing apparatus being used to implement a data processing method with data deinterleaving, such as... Figure 14 As shown, the data processing apparatus may include:

[0180] The second data acquisition module 400 is used to acquire a target data block, which is obtained based on the interleaving of error correction data groups. The error correction data group includes a data block to be transmitted and a corresponding error correction data block. The data block to be transmitted includes a first data block generated from first data and a second data block generated from second data. The target data block includes an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data. The redundant data area is transmitted based on the data channel of the redundant data. The redundant data area includes multiple rows of data, at least one row of data includes both the second data and the error correction data, and at least one row of data includes only the error correction data.

[0181] The deinterleaving module 410 is used to deinterleave the target data block to obtain an error-corrected data group.

[0182] The error correction module 420 is used to correct data errors in the data block to be transmitted in the error correction data group based on the error correction data block in the error correction data group.

[0183] The data to be transmitted generation module 430 is used to generate data to be transmitted based on the error-corrected data block.

[0184] Optionally, the redundant data area includes multiple columns of data, at least one column of data contains only error correction data, and in at least one column of data, error correction data and second data are arranged alternately.

[0185] Optionally, the second data acquisition module 400 is used to acquire the target data block, specifically, to acquire the target data block based on hardware transmission rules;

[0186] The transmission rules include:

[0187] Based on the correspondence between each column of data and the hardware port, the data of each column of the target data block is obtained from different hardware ports;

[0188] Based on the number of target data blocks transmitted in a burst length, obtain the corresponding number of target data blocks.

[0189] Optionally, the second data acquisition module 400 is used to acquire the target data block, including:

[0190] Obtain a burst of data;

[0191] Based on the symbol length in the target data block, the data of that burst length is divided into multiple target data blocks.

[0192] Optionally, the target data block includes at least one error correction data group. The deinterleaving module 410 is used to deinterleave the target data block to obtain the error correction data group. Specifically, it determines the code data in the same error correction data group and its corresponding arrangement order based on a preset data arrangement order.

[0193] Optionally, determining the code data elements and their corresponding arrangement order within the same error correction data group based on a preset data arrangement order includes:

[0194] When the data of the error correction data group in the target data block are arranged sequentially according to the order of the error correction data group, the first data block and / or the second data block and / or the error correction data block in the error correction data group are extracted sequentially.

[0195] Optionally, the error correction module 420 is used to correct data errors in the data block to be transmitted in the error correction data group based on the error correction data block in the error correction data group, including:

[0196] Based on the error correction data blocks in the error correction data group, calculate the location of the erroneous data in the data block to be transmitted;

[0197] Correct the data error in the data block to be transmitted where there is an incorrect data location.

[0198] Optionally, the data to be transmitted generation module 430 is used to generate data to be transmitted based on the error-corrected data blocks to be transmitted. Specifically, it generates the data to be transmitted by combining the first data block and the second data block based on preset rules, wherein the number of the first data block and the number of the second data block are the same.

[0199] The first data is valid data, the second data is valid data, or one or more of the following: identification data, attribute data, verification data, and encryption information corresponding to the valid data.

[0200] This application also provides a memory controller, which may be configured with a data processing device having an interleaving module as provided in the above embodiments, and / or the memory controller may be configured with a data processing device having a deinterleaving module as provided in the above embodiments.

[0201] This application also provides an electronic device that may include the memory controller described above.

[0202] This application also provides a storage medium that stores one or more computer-executable instructions. When the one or more computer-executable instructions are executed, they implement the data processing method with interleaving processing in this application embodiment, and / or implement the data processing method with deinterleaving processing in this application embodiment.

[0203] This application also provides a computer program product, which may include one or more computer-executable instructions. When the one or more computer-executable instructions are executed, they implement the data processing method with interleaving processing in this application embodiment, and / or implement the data processing method with deinterleaving processing in this application embodiment.

[0204] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0205] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A data processing method, characterized in that, include: Acquire the data to be transmitted; wherein the data to be transmitted includes first data and second data; Based on the data to be transmitted, a data block to be transmitted and an error correction data block corresponding to the data block to be transmitted are generated. The data block to be transmitted includes a first data block generated from the first data and a second data block generated from the second data. A data block to be transmitted and its corresponding error correction data block constitute an error correction data group. The sum of the number of symbols in the second data block and the number of symbols in the error correction data block is adapted to the data transmission volume of the data channel transmitting redundant data, and the ratio of the number of symbols in the second data block and the error correction data block is less than or equal to 1:

3. The error correction data group is interleaved to obtain a target data block, which includes an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data; wherein, the redundant data area is transmitted based on the data channel of the redundant data, and the redundant data area includes multiple rows of data, at least one row of data includes both the second data and the error correction data, and at least one row of data includes only the error correction data; Based on the transmission rules of the target data block, the target data block is transmitted to a preset device.

2. The data processing method according to claim 1, characterized in that, The redundant data area includes multiple columns of data, at least one column of data contains only error correction data, and in at least one column of data, error correction data and second data are arranged alternately.

3. The data processing method according to claim 1 or 2, characterized in that, The step of generating a data block to be transmitted and an error correction data block corresponding to the data block to be transmitted based on the data to be transmitted includes: The first data is divided into multiple first data blocks, and the second data is divided into multiple second data blocks. A first data block and a second data block constitute a data block to be transmitted; wherein the number of first data blocks is the same as the number of second data blocks. The data block to be transmitted is encoded to generate an error correction data block corresponding to the data block to be transmitted.

4. The data processing method according to claim 3, characterized in that, The process of dividing the first data into multiple first data blocks and the second data into multiple second data blocks specifically involves dividing the first data into multiple first data blocks with a first preset number of bits and dividing the second data into multiple second data blocks with a second preset number of bits.

5. The data processing method according to claim 1, characterized in that, The target data block includes at least one error correction data group. The step of interleaving the error correction data group to obtain the target data block specifically involves arranging the data of the error correction data group in sequence based on the order of the error correction data group.

6. The data processing method according to claim 5, characterized in that, The target data block includes two error correction data groups, namely the first error correction data group and the second error correction data group. Each error correction data group includes n code elements. The first k-1 code elements are the code elements in the first data block. One of the code elements from the kth code element to the nth code element is the code element in the second data block. The code elements from the kth code element to the nth code element, excluding the code elements that belong to the second data block, are the code elements in the error correction data block. Here, the first n-th code element represents the nth code element in the first error correction data group, and the second n-th code element represents the nth code element in the second error correction data group, where n and k-1 are even numbers greater than 0.

7. The data processing method according to claim 1, characterized in that, The first data is valid data, the second data is valid data, or one or more of the following: identification data, attribute data, verification data, and encryption information corresponding to the valid data.

8. The data processing method according to claim 1, characterized in that, One burst length corresponds to the data volume of multiple target data blocks. The transmission rules of the target data blocks are used to transmit the target data blocks to the preset device. Specifically, the data of multiple target data blocks are transmitted sequentially within one burst length.

9. A data processing method, characterized in that, include: A target data block is obtained, which is obtained based on the interleaving of error correction data groups. The error correction data groups include a data block to be transmitted and a corresponding error correction data block. The data block to be transmitted includes a first data block generated from first data and a second data block generated from second data. The target data block includes an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data. The redundant data area is transmitted based on the data channel of the redundant data. The redundant data area includes multiple rows of data, at least one row of data includes both the second data and the error correction data, and at least one row of data includes only the error correction data. The target data block is de-interleaved to obtain the error-corrected data group; Based on the error correction data blocks in the error correction data group, correct the data errors of the data blocks to be transmitted in the error correction data group; Based on the error-corrected data block to be transmitted, generate the data to be transmitted.

10. The data processing method according to claim 9, characterized in that, The redundant data area includes multiple columns of data, at least one column of data contains only error correction data, and in at least one column of data, error correction data and second data are arranged alternately.

11. The data processing method according to claim 9, characterized in that, The acquisition of the target data block specifically refers to acquiring the target data block based on the hardware transmission rules; The transmission rules include: Based on the correspondence between each column of data and the hardware port, the data of each column of the target data block is obtained from different hardware ports; Based on the number of target data blocks transmitted in a burst length, obtain the corresponding number of target data blocks.

12. The data processing method according to claim 9, characterized in that, The acquisition of the target data block includes: Obtain a burst of data; Based on the symbol length in the target data block, the data of that burst length is divided into multiple target data blocks.

13. The data processing method according to claim 9, characterized in that, The target data block includes at least one error correction data group. The step of deinterleaving the target data block to obtain the error correction data group specifically involves determining the code data elements belonging to the same error correction data group and their corresponding arrangement order based on a preset data arrangement order.

14. The data processing method according to claim 13, characterized in that, The process of determining the code data elements and their corresponding arrangement order within the same error correction data group based on a preset data arrangement order includes: When the data of the error correction data group in the target data block are arranged sequentially according to the order of the error correction data group, the first data block and / or the second data block and / or the error correction data block in the error correction data group are extracted sequentially.

15. The data processing method according to claim 9, characterized in that, The step of correcting data errors in the data block to be transmitted in the error correction data group based on the error correction data block in the error correction data group includes: Based on the error correction data blocks in the error correction data group, calculate the location of the erroneous data in the data block to be transmitted; Correct the data error in the data block to be transmitted where there is an incorrect data location.

16. The data processing method according to claim 9, characterized in that, The step of generating data to be transmitted based on the error-corrected data blocks specifically involves combining the first data block and the second data block according to preset rules to generate the data to be transmitted, wherein the number of the first data blocks is the same as the number of the second data blocks.

17. The data processing method according to claim 9, characterized in that, The first data is valid data, the second data is valid data, or one or more of the following: identification data, attribute data, verification data, and encryption information corresponding to the valid data.

18. A data processing apparatus, characterized in that, include: A first data acquisition module is used to acquire data to be transmitted; wherein the data to be transmitted includes first data and second data; The processing module is configured to generate a data block to be transmitted and an error correction data block corresponding to the data block to be transmitted based on the data to be transmitted. The data block to be transmitted includes a first data block generated from first data and a second data block generated from second data. A data block to be transmitted and its corresponding error correction data block constitute an error correction data group. The sum of the number of symbols in the second data block and the number of symbols in the error correction data block is adapted to the data transmission volume of the data channel transmitting redundant data, and the ratio of the number of symbols in the second data block and the error correction data block is less than or equal to 1:

3. An interleaving module is used to interleave the error correction data group to obtain a target data block. The target data block includes an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data. The redundant data area is transmitted based on the data channel of the redundant data. The redundant data area includes multiple rows of data. At least one row of data includes both the second data and the error correction data. At least one row of data includes only the error correction data. The data transmission module is used to transmit the target data block to a preset device based on the transmission rules of the target data block.

19. A data processing apparatus, characterized in that, include: The second data acquisition module is used to acquire a target data block, which is obtained based on the interleaving of error correction data groups. The error correction data groups include a data block to be transmitted and a corresponding error correction data block. The data block to be transmitted includes a first data block generated from first data and a second data block generated from second data. The target data block includes an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data. The redundant data area is transmitted based on the data channel of the redundant data. The redundant data area includes multiple rows of data, at least one row of data includes both the second data and the error correction data, and at least one row of data includes only the error correction data. The deinterleaving module is used to deinterleave the target data block to obtain the error-corrected data group; The error correction module is used to correct data errors in the data block to be transmitted in the error correction data group based on the error correction data block in the error correction data group. The data to be transmitted generation module is used to generate data to be transmitted based on the error-corrected data block.

20. A memory controller, characterized in that, The memory controller is configured with the data processing device as described in claim 18; And / or, The memory controller is configured with the data processing apparatus as described in claim 19.

21. An electronic device, characterized in that, Includes the memory controller as described in claim 20.

22. A storage medium, characterized in that, The storage medium stores one or more computer-executable instructions, which, when executed, implement the data processing method as described in any one of claims 1 to 8, and / or implement the data processing method as described in any one of claims 9 to 17.

23. A computer program product, characterized in that, It includes one or more computer-executable instructions, which, when executed, implement the data processing method as described in any one of claims 1 to 8, and / or implement the data processing method as described in any one of claims 9 to 17.

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