An ARP entry processing method, a chip, a switching device and a storage medium

Abstract

The application provides an ARP entry processing method, a chip, a switching device and a storage medium. The method obtains an ARP entry sent by another network device through an interface, and synchronizes the ARP entry to a second chip in the switching device. When the interface fails, only the destination IP address in a first storage table is deleted, and the destination MAC address in a second storage table is completely reserved. When the interface recovers and the ARP entry is relearned, the second chip directly locates the existing destination MAC address in the second storage table, and updates the existing MAC address to the destination MAC address in the new ARP entry through a single write operation. Since the chain table node in the hash table of the second chip is not removed in the above deletion and update processes, the calculation resources required for hash table reorganization are saved, and the time-consuming overhead caused by the data migration of the hash table due to the ARP entry processing is avoided.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, and in particular to an ARP entry processing method, a chip, a switching device, and a storage medium. Background Technology

[0002] In complex network environments, switching devices, as the core hubs for data forwarding, inevitably face the problem of physical interface oscillation, i.e., frequent disconnections and reconnections of interfaces due to line interference, equipment failures, or environmental factors. Upon interface failure, the switching device must immediately clear all ARP entries associated with that interface to ensure that the device does not forward data to the failed interface. After the interface recovers, the restored network traffic will trigger a large number of ARP entry rebuilds. Since packet forwarding relies on the mapping of destination IP addresses to destination MAC addresses, the switching device must relearn ARP entries through the interaction of broadcast requests and unicast responses.

[0003] In the above process, the deletion and reconstruction of each ARP entry involves computation and storage operations. If interface oscillations occur frequently, the amount of deletion and reconstruction operations accumulated in a short period of time will increase dramatically, excessively occupying the computing resources of the switching equipment. This can easily lead to data packet forwarding obstruction, critical service response timeouts, and potentially cause network service interruptions. Summary of the Invention

[0004] To overcome the aforementioned problems in the prior art, this disclosure provides an ARP entry processing method, a chip, a switching device, and a storage medium.

[0005] According to a first aspect of the embodiments of this specification, an ARP entry processing method is provided, the method being applied to a first chip in a switching device; the switching device further includes a second chip, the first chip including a plurality of interfaces for communicating with other network devices; the first chip is used to obtain ARP entries sent by other network devices through the interfaces, store them locally, and synchronize the ARP entries to the second chip, the type of the ARP entries including Layer 3 unicast; the second chip includes a hash table for storing ARP entries, a first storage table and a second storage table, the first storage table being used to store the destination IP address in the Layer 3 unicast ARP entries, and the second storage table being used to store the destination MAC address in the ARP entries; The method includes: If a faulty interface is detected, all ARP entries corresponding to the faulty interface are deleted from this chip. For ARP entries of type Layer 3 unicast, the destination IP address in the deleted ARP entry is sent to the second chip, so that the second chip deletes the corresponding destination IP address in the first storage table; When a new ARP entry is received after the faulty interface is powered on again, the new ARP entry is stored locally and sent to the second chip so that the second chip updates the hash table according to the new ARP entry, stores the destination IP address in the new ARP entry in the first storage table, and first assigns an existing destination MAC address to the destination IP address in the new ARP entry in the second storage table, and then updates the existing destination MAC address to the destination MAC address in the new ARP entry.

[0006] According to a second aspect of the embodiments of this specification, a chip is provided, suitable for a switching device, the switching device further comprising a second chip, the chip including a plurality of interfaces for communicating with other network devices; the chip is used to obtain ARP entries sent by other network devices through the interfaces, store them locally, and synchronize the ARP entries to the second chip, the type of the ARP entries including Layer 3 unicast; the second chip includes a hash table for storing ARP entries, a first storage table and a second storage table, the first storage table being used to store the destination IP address in the Layer 3 unicast ARP entries, and the second storage table being used to store the destination MAC address in the ARP entries; The chip is used to delete all ARP entries corresponding to the faulty interface on its own chip when a faulty interface is detected, and to synchronize the ARP entries for Layer 3 unicast ARP entries to the second chip in the following manner: The destination IP address in the deleted ARP table entry is sent to the second chip, so that the second chip deletes the corresponding destination IP address in the first storage table; And when a new ARP entry is received after the faulty interface is powered on again, the new ARP entry is stored locally and sent to the second chip; so that the second chip updates the hash table according to the new ARP entry, stores the destination IP address in the new ARP entry in the first storage table, and first assigns an existing destination MAC address to the destination IP address in the new ARP entry in the second storage table, and then updates the existing destination MAC address to the destination MAC address in the new ARP entry.

[0007] According to a third aspect of the embodiments of this specification, a switching device is provided, including the chip described in the second aspect and a second chip.

[0008] According to a fourth aspect of the embodiments of this specification, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in the first aspect.

[0009] This embodiment obtains ARP entries sent by other network devices through an interface and synchronizes these ARP entries to the second chip. In the event of an interface failure, only the destination IP address in the first storage table is deleted, while the destination MAC address in the second storage table is fully preserved. When the interface recovers and relearns ARP entries, the second chip directly locates the existing destination MAC address in the second storage table and updates it to the new destination MAC address in the ARP entry through a single write operation. Since the deletion and update process does not involve removing linked list nodes from the hash table of the second chip, the computational resources required for hash table reorganization are saved, thus avoiding the time-consuming overhead caused by hash table data migration due to ARP entry processing. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a chip shown in an exemplary embodiment of this application; Figure 2 This is a schematic diagram of a switching device illustrated in an exemplary embodiment of this application; Figure 3 This is a schematic diagram of a switching device illustrated in another exemplary embodiment of this application; Figure 4 This is a flowchart illustrating an ARP entry processing method according to an exemplary embodiment of this application; Figure 5 This is a flowchart illustrating an ARP entry processing method according to another exemplary embodiment of this application. Detailed Implementation

[0011] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0012] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0013] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0014] In complex network environments, switching equipment, as the core hub for data forwarding, inevitably faces the problem of physical interface oscillation—that is, the interface frequently disconnects and reconnects due to line interference, equipment failure, or environmental factors.

[0015] In the event of an interface failure, the switching device must immediately clear all ARP entries associated with that interface. ARP entries are critical forwarding entries maintained by the device, recording the mapping between IP addresses and MAC addresses, used for address translation from the network layer (IP) to the data link layer (MAC). Clearing these entries ensures that the device will not forward data to the failed interface.

[0016] After the interface is restored, the restored network traffic will trigger a large number of ARP entry rebuilds. Since packet forwarding depends on the mapping of destination IP address to destination MAC address, the switching device needs to relearn ARP entries through the interaction of broadcast requests and unicast responses.

[0017] In the above process, the deletion and reconstruction of each ARP entry involves computation and storage operations. If interface oscillations occur frequently, the amount of deletion and reconstruction operations accumulated in a short period of time will increase dramatically, excessively occupying the computing resources of the switching equipment. This can easily lead to packet forwarding obstruction, critical service response timeouts, and ultimately, network service interruption.

[0018] Based on this, the embodiments in this specification improve the functionality of the chips in the switching equipment to optimize the processing efficiency of ARP entries, thereby enhancing the stability of network services.

[0019] like Figure 1 As shown, Figure 1 This is a schematic diagram of a chip according to an exemplary embodiment of this specification. For ease of distinction, this chip is hereinafter referred to as the first chip 11. The first chip 11 is provided with several interfaces for communication with other network devices. Specifically, the first chip 11 can be a control plane processor in a switching device, which serves as the management system and network protocol stack of the switching device, used to implement logical decisions and ARP entry management.

[0020] The following will combine Figure 2 and Figure 3The application of the first chip 11 in the embodiment of this specification in the switching device 10 will be described. Figure 2 This is a schematic diagram of a switching device 10 according to an exemplary embodiment of this specification. The switching device 10 includes a first chip 11 and a second chip 12. The first chip 11 is used to obtain ARP entries sent by other network devices through the interface, store them locally, and synchronize the ARP entries to the second chip 12. The type of ARP entry includes Layer 3 unicast. The second chip 12 includes a hash table 120 for storing ARP entries, a first storage table 121, and a second storage table 122. The first storage table 121 is used to store the destination IP address in the Layer 3 unicast ARP entries, and the second storage table 122 is used to store the destination MAC address in the ARP entries.

[0021] In the switching device 10, when the first chip 11, which acts as the control plane processor, learns an ARP entry, it obtains the ARP entries sent by other network devices through the interface, stores them locally, and synchronizes the ARP entries to the second chip 12.

[0022] The second chip 12, which can be a switching chip in the switching device 10, is used to achieve fast forwarding of packet data through hardware acceleration. Specifically, after receiving the ARP entry from the first chip 11, the second chip 12 stores the data in the ARP entry in three association tables, including a hash table 120, a first storage table 121, and a second storage table 122. The hash table 120 stores the complete ARP entry; the first storage table 121 stores the destination IP address in the ARP entry of type Layer 3 unicast, serving as a directory for Layer 3 unicast data forwarding; and the second storage table 122 stores the destination MAC address, interface information, service type, and other information of the ARP entry.

[0023] The second storage table 122 stores entries corresponding to service types that include at least Layer 3 unicast. The entries in the second storage table 122 can be categorized into multiple types based on service type, each corresponding to a different forwarding scenario. In practical applications of this application, the service types stored in the second storage table 122 may include IPUC (IP Unicast), ECMP (Equal Cost Multi Path), MPLS (Multiprotocol Label Switching), IP-tunnel, and Mcast (Multicast protocol communication), etc.

[0024] In switching device 10, although the first chip 11, acting as the control plane, maintains an ARP entry, the second chip 12, acting as the forwarding chip, still needs to independently store the complete ARP entry based on hash table 120. This is determined by the design architecture of the second chip 12, its hardware forwarding characteristics, and system reliability requirements. Specifically, the second chip 12 must ensure that it can continue to forward data packets based on its locally stored entries even when it is off-plane. Furthermore, the forwarding pipeline of the second chip 12 is self-contained hardware logic; query, modification, and forwarding operations are all completed within the second chip 12. Therefore, the first chip 11 needs to fully synchronize its ARP entries to the hash table 120 of the second chip 12 to ensure consistency between the two chips.

[0025] It should be noted that the design of the first storage table 121 and the second storage table 122 in the second chip 12 is the core hardware acceleration mechanism for achieving line-speed data forwarding. Specifically, the first storage table 121 is an index directory for IP addresses, storing the mapping of "destination IP address → index"; the second storage table 122 stores specific content such as "index → ​​destination MAC address and interface data". When performing a forwarding operation, the first entry in the first storage table 121 is searched based on the destination IP address to determine the index, and then the destination MAC address and interface data in the second storage table 122 are determined based on the index. The first storage table 121 and the second storage table 122 transform the complete ARP information in the hash table 120 into a forwarding path that is most suitable for hardware pipeline execution, efficient and resource-saving, ensuring that data packets can be forwarded and processed at the fastest speed and with the most stable latency.

[0026] It should be noted that in the second chip 12, the hash table 120, the first storage table 121, and the second storage table 122 form a closely related three-layer structure, and their cascading relationship determines the chain effect of the table entry deletion operation. When the first storage table 121 and the second storage table 122 simultaneously delete the related entries of the same ARP entry, it means that the physical forwarding resource is permanently lost. Therefore, the ARP entry remaining in the hash table 120 can neither serve the forwarding process nor stop occupying limited memory space. Thus, the second chip 12 will trigger the automatic clearing of the ARP entry in the hash table 120 to maintain the effectiveness of system resources.

[0027] To optimize ARP entry processing efficiency, the inventors identified the root causes of processing time consumption through comparative testing. They simulated traffic to learn 5000, 10000, and 20000 ARP entries, respectively, for both static and dynamic ARP entry learning scenarios. Based on these comparative tests, the inventors found that during static ARP entry learning, the interface oscillation response time increased linearly with the number of entries; while during dynamic ARP entry learning, the processing time under the same oscillation conditions exhibited a non-linear surge, and the time increased nearly tenfold when the data volume doubled.

[0028] Research revealed that the fundamental reason for this difference is that, for static ARP entries, the hash table 120 in the second chip 12 can store static ARP entries according to the configuration order of the first chip 11. That is, the storage order of dynamic ARP entries in the hash table 120 in the second chip 12 is the same as the configuration order. Furthermore, when the first chip 11 deletes a static ARP entry, the second chip 12 can also synchronously perform the deletion operation according to the storage order of the static ARP entry in the hash table 120. Therefore, there is no additional data migration time for storage space during the deletion and reconstruction process. For dynamic ARP entries, due to their dynamic aging and self-learning characteristics, the hash table 120 in the second chip 12 cannot store dynamic ARP entries according to the configuration order of the first chip 11. That is, the storage order of dynamic ARP entries in the hash table 120 is different from the configuration order. Furthermore, when the first chip 11 deletes a dynamic ARP entry, the second chip 12 cannot synchronously perform the deletion operation according to the storage order of the dynamic ARP entry in the hash table 120. Deletion requires traversing the collision chain from the head of the table to locate the dynamic ARP entry to be deleted. The high time consumption of dynamic ARP deletion and reconstruction stems from the data migration overhead of the hash table 120 in the second chip 12 (i.e., collision chain reconstruction). When deleting an ARP entry located in the middle of the hash table 120, due to the inherent storage characteristics of the hash table 120, the following operations must be performed: Unlink the predecessor node pointer; Relink the predecessor node to the successor node; Release the memory of the deleted node and update the linked list structure.

[0029] The migration process described above involves memory read / write operations and pointer updates, and its time consumption increases exponentially with the density of table entries. Therefore, the high time consumption of dynamic ARP is essentially due to a mismatch between the storage structure and the operational logic—while the hash table 120 in the second chip 12 improves query efficiency, it comes at the cost of data migration time during deletion. In scenarios involving interface oscillations, the migration overhead of a large number of ARP entries exceeds the real-time processing capacity of the second chip 12, thereby triggering network failures. Therefore, optimization should focus on fundamentally avoiding data migration.

[0030] Based on the above findings, the purpose of the switching device 10 in this embodiment of the specification is to improve the ARP entry processing efficiency by reusing the space resources of the second storage table 122 to avoid data migration of the hash table 120 in the case of interface oscillation.

[0031] To achieve the above objectives, the first chip 11 is used to delete all ARP entries corresponding to the faulty interface on its own chip when a faulty interface is detected, and to synchronize the ARP entries for Layer 3 unicast ARP entries to the second chip 12 in the following manner: The destination IP address in the deleted ARP entry is sent to the second chip 12, so that the second chip 12 deletes the corresponding destination IP address in the first storage table 121.

[0032] And when a new ARP entry is received after the faulty interface is powered on again, the new ARP entry is stored locally and sent to the second chip 12; so that the second chip 12 updates the hash table 120 according to the new ARP entry, stores the destination IP address in the new ARP entry in the first storage table 121, and first assigns an existing destination MAC address to the destination IP address in the new ARP entry in the second storage table 122, and then updates the existing destination MAC address to the destination MAC address in the new ARP entry.

[0033] In the embodiments described in this specification, when the first chip 11 detects an interface fault, it immediately deletes all ARP entries associated with that interface stored locally, and simultaneously synchronizes the destination IP address of the deleted entries to the second chip 12. The second chip 12 then deletes the entry corresponding to that destination IP address in the first storage table 121, but retains the original content of each entry in the second storage table 122.

[0034] After the faulty interface recovers and relearns the ARP entries, the first chip 11 synchronizes the new ARP entries to the second chip 12. At this time, the second chip 12 performs the following operations based on the new ARP entries: updates the hash table 120 that records complete ARP entries; writes the destination IP address from the new ARP entry into the first storage table 121; and then applies a reuse update mechanism to the second storage table 122. This reuse update mechanism first assigns an existing old MAC address to the new destination IP address, and then immediately overwrites the old destination MAC address with the actual destination MAC address of the new entry.

[0035] In one embodiment, the second chip 12 configures different operation interfaces for entries of different service types in the second storage table 122. These operation interfaces may include add, delete, and update interfaces. Technical personnel can configure the entries in the second storage table 122 based on the operation interfaces provided by the second chip 12. It should be noted that, based on a comprehensive consideration of the functional attributes, operation frequency, and security boundaries of different service types, the second chip 12 does not provide open operation interfaces for some service type entries in the second storage table 122. Instead, these are automatically maintained through the SDK (Software Development Kit) of the second chip 12. It can be understood that in step S1002, updating the existing destination MAC address to the destination MAC address in the new ARP entry is achieved through the Layer 3 unicast update interface in the second storage table 122.

[0036] It should be noted that the above steps are executed when the first chip 11 receives the Layer 3 unicast ARP entry, which is based on the inherent design of the second chip 12. In the second storage table 122, the characteristic of Layer 3 unicast is that its destination MAC address supports direct overwrite updates, eliminating the need for time-consuming entry deletion and reconstruction operations. In contrast, other forwarding types such as ECMP and MPLS, due to hardware limitations, require the complete deletion and reconstruction of the original entry when modifying the MAC address, making data migration overhead unavoidable. Meanwhile, most of the ARP entries that need to be deleted and reconstructed during interface oscillations are applied to Layer 3 unicast. These ARP entries typically serve unicast forwarding independently, and directly updating the MAC address will not disrupt the integrity of related business logic.

[0037] Layer 3 unicast traffic, due to its core role in network data transmission, has become a key optimization target. As the most basic and common forwarding type in IP networks, Layer 3 unicast carries the majority of communication traffic between devices, resulting in a large number of frequently updated ARP entries. When physical interfaces experience oscillations, the associated Layer 3 unicast ARP entries often constitute the majority of the total amount that needs to be deleted and rebuilt. If this large-scale reconstruction uses traditional data migration mechanisms, it will cause the hash table of the second chip to suffer extremely high linked list reorganization overhead, leading to a precipitous drop in forwarding performance. Therefore, the above method steps in this embodiment can be optimized specifically for the characteristics of Layer 3 unicast. Based on its dominant position in network traffic composition and the scale effect in oscillation scenarios, it accurately identifies the main reason for the large consumption of computing resources during interface oscillations. By reusing the second storage table space to avoid the reorganization of hash table collision chains, this solution reduces time-consuming operations on the service type with the highest traffic share, thereby achieving maximum benefits with minimal architectural changes.

[0038] It should be noted that although the aforementioned comparative experiment shows that the low efficiency of ARP entry processing is mainly due to the data migration of the hash table 120 of the second chip 12 caused by dynamic ARP deletion and reconstruction, the embodiments in this specification do not need to limit the processed ARP entries to dynamic ARP entries, and static ARP entries can also be processed in the same way.

[0039] In this embodiment, when an interface fails, only the destination IP address in the first storage table 121 is deleted, while the destination MAC address in the second storage table 122 is fully preserved. When the interface recovers and relearns ARP entries, the second chip 12 directly locates the existing destination MAC address in the second storage table 122 and updates it to the new destination MAC address in the ARP entry through a single write operation. Since the deletion and update process does not involve removing linked list nodes from the hash table 120 of the second chip 12, the computational resources required for hash table 120 reorganization are saved, thereby avoiding the time-consuming overhead caused by data migration in hash table 120 due to ARP entry processing.

[0040] Furthermore, this design simultaneously mitigates the risk of memory resource fluctuations. Traditional solutions require re-allocating memory and initializing data structures each time an entry is rebuilt; intensive memory allocation within a short period can easily exhaust the cache of the second chip 12. The reuse mechanism keeps the memory resources of the second storage table 122 constant during the oscillation cycle. Rebuilding a new ARP entry only requires overwriting, avoiding memory allocation operations and thus eliminating resource consumption caused by memory allocation operations in the second storage table 122.

[0041] In one or more embodiments of this specification, the first chip 11 also stores an index and the type of the index, the type of the index including three-layer unicast, the index being associated with an existing MAC address in the second storage table 122; the index is created when the ARP entry is synchronized to the second chip 12 before the interface fails.

[0042] For example, the index can be a numeric index, which is essentially a resource location identifier. Based on this index, when the second chip 12 performs a forwarding operation, it first looks up the entry in the first storage table 121 based on the destination IP address to determine the index, and then uses this index to determine the destination MAC address and interface data in the second storage table 122. Besides numeric indexes, this method can also use structured identifiers, such as designing the index as a composite field. Numeric indexes are a common choice due to their simplicity, while structured indexes demonstrate flexibility in multi-service convergence scenarios. It can be understood that regardless of the form used, the core function of the index is always to establish a stable relationship between the two storage tables.

[0043] The first chip 11 records the indexes and their corresponding types, which is a key prerequisite for achieving efficient updates. These indexes and their corresponding types were established before the interface failure occurred, and the timing of index generation is closely related to the initial synchronization process of ARP entries.

[0044] In one embodiment, after the first chip 11 sends the Layer 3 unicast ARP entry to the second chip 12, the second chip 12 will return a unique index corresponding to the entry when creating the entry in the second storage table 122. The first chip 11 then records the index and its type. Since the ARP entry is Layer 3 unicast, the type of the index is also recorded as Layer 3 unicast.

[0045] In another embodiment, the responsibility for index generation and management can be transferred to the first chip 11. When the first chip 11 needs to synchronize a new ARP entry to the second chip 12, its internal index management module will actively allocate a free index value. This allocation process follows a predefined resource pool mechanism: the first chip 11 maintains a range list of available indexes in the second storage table 122, and selects an unused index from the pool before each entry is sent, marking it as occupied. After selecting an index, the first chip 11 sends the index value, along with the destination IP address, destination MAC address, and index type of the ARP entry, to the second chip 12. After receiving the data, the second chip 12 directly writes the destination MAC address to the specified index position in the second storage table 122 without returning confirmation information. In this mode, the creation, allocation, and reclamation of indexes are autonomously controlled by the first chip 11, and the second chip 12 only acts as the execution end of index instructions.

[0046] It is understood that the indexes maintained by the first chip 11 cover all forwarding types supported by the second chip 12, including ECMP (Equal Cost Multipath), MPLS (Multiprotocol Label Switching), IP-tunnel (IP Tunnel Encapsulation), Mcast (Multicast Protocol Communication), and other types. Since the main optimization of this embodiment lies in the ARP entries for Layer 3 unicast during interface oscillation, and the generation methods for other index types are basically the same as those for Layer 3 unicast, the generation mechanisms for other index types will not be elaborated here.

[0047] Based on the foregoing, the first chip 11 is also used to find the index associated with the MAC address in all ARP entries deleted on the chip, and determine whether the type of the ARP entry is Layer 3 unicast based on the type of the index.

[0048] When an interface failure is detected and an ARP entry is deleted, the first chip 11 can first perform an index type verification process. Specifically, the first chip 11 will traverse all the indexes recorded by this chip that correspond to all MAC addresses associated with the deleted ARP entry, and verify one by one whether its type is Layer 3 unicast. The core function of this verification step is to establish an operational security boundary: the Layer 3 unicast type is the only condition that supports the subsequent reuse of the update path of the second storage table 122. If the index type is confirmed to be Layer 3 unicast, it indicates that the corresponding entry in the second storage table 122 has the ability to directly overwrite and update. At this time, the entry in the second storage table 122 associated with the index is retained, and only its binding relationship with the entry in the first storage table 121 is released.

[0049] This type verification mechanism avoids hardware operation risks associated with the second chip 12. The second chip 12 provides differentiated programming interfaces for entries of different types of second storage tables 122. If an update interface is called incorrectly for a non-layer 3 unicast type, an operation exception will be triggered.

[0050] The embodiments in this specification avoid the risk of incorrect call to the update interface of the second storage table 122 by pre-setting the index type and real-time verification, thus enabling the resource reuse strategy to be implemented safely.

[0051] like Figure 3 As shown, Figure 3 This is a schematic diagram of a switching device 10 according to another exemplary embodiment of this specification. A feature of this embodiment is that the second chip 12 further includes a third storage table 123 storing destination IP addresses in ARP entries other than Layer 3 unicast.

[0052] The first chip 11 is further configured to, upon detecting a faulty interface, delete all ARP entries corresponding to the faulty interface on this chip for non-Layer 3 unicast ARP entries, and send the destination IP address and destination MAC address in the deleted ARP entries to the second chip 12. The second chip 12 is further configured to delete the corresponding destination IP address in the third storage table 123 and the destination MAC address in the second storage table 122.

[0053] The first chip 11 is also used to, when a new ARP entry is received after the faulty interface is powered on again, store the new ARP entry locally and send the new ARP entry to the second chip 12; the second chip 12 is also used to update the hash table 120 according to the new ARP entry, store the destination IP address in the new ARP entry in the third storage table 123, and create a new entry in the second storage table 122 and store the destination MAC address in the new ARP entry.

[0054] For ARP entries that are not Layer 3 unicast (such as those serving multipath forwarding or label switching services), the processing mechanism employs a thorough resource destruction and reconstruction strategy, which is fundamentally different from the optimized path of Layer 3 unicast. When the first chip 11 detects an interface failure, it performs the following for such entries: while deleting the locally stored entry, it simultaneously sends the destination IP address and destination MAC address of the deleted entry to the second chip 12. This key difference triggers the second chip 12 to perform a cascading destruction operation—simultaneously deleting the corresponding destination IP address in the third storage table 123 and the associated MAC address in the second storage table 122.

[0055] During the reconstruction phase after the faulty interface is restored, the processing of non-Layer 3 unicast entries follows the traditional security path. When the first chip 11 sends the newly learned ARP entry to the second chip 12, the second chip 12 must perform a full reconstruction: allocate new storage space in the second storage table 122 to create the entry entity and fully write the new destination MAC address.

[0056] The above deletion and reconstruction logic stems from the inherent constraints of non-Layer 3 unicast services. Equivalent multipath forwarding entries maintain a dynamic path health status, while multicast services carry a tree-like topology, with their business logic deeply coupled to the underlying storage. Attempting to reuse existing MAC storage units would lead to catastrophic consequences: multipath weight calculations might reference faulty ports, and multicast tree replication nodes might point to incorrect interfaces. While destruction and reconstruction increase instantaneous overhead, they are the only way to ensure business atomicity. When interface oscillations affect massive numbers of entries, Layer 3 unicast services achieve millisecond-level recovery through reuse mechanisms, while non-unicast services must bear the cost of reconstruction. This differentiated approach is the solution this application sets for balancing chip resources and business security.

[0057] Based on the above embodiments, the first chip 11 stores the index and the index type based on the index table 111. The second chip 12 stores the first storage table 121, the second storage table 122, and the third storage table 123, each of which includes several entries. Specifically, the entries in the first storage table 121 store the destination IP address and the index; the entries in the second storage table 122 store the index and physical forwarding parameters, wherein the physical forwarding parameters may store the destination MAC address and the outgoing label; and the entries in the third storage table 123 store the incoming label and the index.

[0058] The first storage table 121 implements the navigation mapping from the destination IP address to the index. For example, indexes 1110 and 101 are numeric indexes. When the second chip 12 performs a forwarding operation, it can first locate index 1110 in the first storage table 121 through the destination IP address 110, and then directly obtain the destination MAC address 120 in the second storage table 122 through the index 1110. The entire process is completed within a single clock cycle.

[0059] The third storage table 123 implements the navigation mapping from ingress label to index. For example, the third storage table 123 uses the ingress label carried by the ECMP packet as the unique retrieval key and stores the strictly bound index value. When a packet carrying the destination IP address 210 arrives at the switching device 10, the second chip 12 locates the corresponding entry in the third storage table 123 through a lookup engine and obtains the preset index 200. Then, using index 200 as the key, the path action 220 is extracted from the second storage table 122. The path action can correspond to multiple different destination MAC addresses; therefore, the entry can also be located by the index associated with the destination MAC address and reconstructed based on the destination MAC address.

[0060] Based on the foregoing, Figure 3 The second chip 12 shown includes two tables for storing navigation mappings and physical forwarding parameters. In this embodiment, the table for storing physical forwarding parameters is the second storage table 122. The tables for storing navigation mappings in this embodiment are the first storage table 121 and the third storage table 123. It can be understood that, in addition to the first storage table 121 and the third storage table 123 corresponding to the two service types IPUC (Layer 3 Unicast) and ECMP (Equal Cost Multipath) respectively, those skilled in the art can also set up a fourth storage table, a fifth storage table, a sixth storage table, etc., for storing navigation mappings for service types such as MPLS (Multiprotocol Label Switching), IP-tunnel (IP Tunnel Encapsulation), and Mcast (Multicast Protocol Communication). Correspondingly, the second storage table 122 will also store different physical forwarding parameters according to the different forwarding operations of the service types in the fourth, fifth, and sixth storage tables. The processing methods for the fourth, fifth, and sixth storage tables are the same as those for the third storage table 123. Since the main purpose of this invention is to optimize the processing of ARP entries for Layer 3 unicast, the processing flows for other service types such as MPLS, ECMP, IP-tunnel, and Mcast will not be elaborated upon. It is understood that... Figure 3 The physical forwarding parameters stored in the second storage table 122 shown are only a simplified example. Physical forwarding parameters may also include data such as egress ports.

[0061] Based on the working principles of the first storage table 121, the second storage table 122 and the third storage table 123 in the second chip 12, the index table 111 in the first chip 11 exhibits core control value in the interface oscillation scenario, and its core function is to provide accurate operational decision-making basis for fault recovery.

[0062] In this embodiment, the index table 111 continuously accumulates historical records during normal device operation: whenever the first chip 11 synchronizes an ARP entry to the second chip 12, it synchronously captures the index returned by the second chip 12 and persists its type attribute, forming a "index value-type tag" record. For example, index 1110 is recorded as a three-layer unicast type, and such records are persistently stored in the index table 111 in time series.

[0063] When an interface failure is detected and triggers ARP entry deletion, the first chip 11 first locates all MAC addresses associated with the deleted entry, and then queries the historical index records corresponding to these MAC addresses in index table 111. At this time, by searching the type field of index 1110 and finding that it displays the "IPUC" flag, the first chip 11 determines that index 1110 is a Layer 3 unicast type, and the corresponding entry in the second storage table 122 is ready for updating; when index 1130 shows an ECMP type, it is excluded from the reuse mechanism.

[0064] In contrast, if the first chip 11 does not store indexes and index types, but instead initiates a query request to the second chip 12 before the deletion and update process to obtain the business type of the entries in the second storage table 122, it can also determine whether the entries in the second storage table 122 should be deleted or whether they meet the update conditions. However, in this implementation, the real-time query path requires the first chip 11 to initiate a type query to the second chip 12 before each deletion or update operation, which introduces multiple uncontrollable risks. Inter-chip communication relies on a shared bus and cache queue, and under high load conditions due to interface failure, response delays or packet loss are very likely to occur, causing the first chip 11 to fall into a passive state of waiting timeout. More seriously, if the returned type information is distorted due to bus congestion, it may trigger erroneous operations—for example, misjudging a Layer 3 unicast entry that should be retained as a type that needs to be deleted, causing service interruption.

[0065] Therefore, the indexes and their types stored in the first chip 11 of this embodiment are bound to hardware resources when the table entries are created, and their lifecycles are strictly synchronized with the table entries, thereby ensuring that only the three-layer unicast processing flow enters the efficient update channel. Through the abstraction of the index table 111, the first chip 11 does not need to understand the underlying hardware details of the second chip 12, and can formulate recovery strategies based solely on the type tags, maintaining accurate service diversion in an environment of interface oscillation.

[0066] In one or more embodiments of this specification, the first chip 11 is further configured to store the new ARP entry in a message queue before sending the new ARP entry to the second chip 12, and send a notification to the fault interface to cause the fault interface to stop sending the ARP entry again; and asynchronously retrieve the new ARP entry from the message queue to execute sending the new ARP entry to the second chip 12.

[0067] A message queue mechanism is introduced during ARP entry reconstruction to build an efficient traffic control and asynchronous processing system. When a new ARP entry is generated after the faulty interface recovers, the first chip 11 does not immediately transmit it to the second chip 12. Instead, it first performs a queuing operation: writing the ARP entry into a dedicated message queue buffer. At the same time, the first chip 11 immediately sends a notification to the faulty interface to unblock it, causing the faulty interface to stop the repeated transmission of the same ARP entry. This coordinated design precisely suppresses the traffic storms that may be caused by the inherent retransmission mechanism of the network protocol, eliminating the burden of redundant data processing at the source.

[0068] After the enqueue operation is completed, the entry processing immediately transitions to the asynchronous execution phase: the first chip 11 sequentially retrieves ARP entries from the queue based on a message scheduling strategy independent of the send / receive operations, and sends the ARP entries to the second chip 12. In this embodiment, the asynchronous processing mechanism based on message queues enables dynamic adaptation of the sending processing rates between the first chip 11 and the second chip 12. When the second chip 12 is overloaded, the scheduling frequency can be automatically reduced to prevent resource overload and transmission channel congestion. This mechanism, while ensuring service continuity, transforms sudden traffic spikes caused by interface oscillations into a stable and controllable chip workload, providing anti-oscillation resilience for large-scale network equipment.

[0069] Based on the same technical concept, this specification also provides an exemplary embodiment illustrating an ARP entry processing method. The method is applied to a first chip in a switching device; the switching device further includes a second chip, and the first chip includes several interfaces for communicating with other network devices; the first chip is used to obtain ARP entries sent by other network devices through the interfaces, store them locally, and synchronize the ARP entries to the second chip, wherein the type of the ARP entries includes Layer 3 unicast; the second chip includes a hash table for storing ARP entries, a first storage table, and a second storage table, wherein the first storage table is used to store the destination IP address in the Layer 3 unicast ARP entries, and the second storage table is used to store the destination MAC address in the ARP entries.

[0070] like Figure 4 As shown, Figure 4This is a flowchart illustrating an ARP entry processing method according to an exemplary embodiment of this specification. The ARP entry processing method includes the following steps: S1000: If a faulty interface is detected, delete all ARP entries corresponding to the faulty interface on this chip.

[0071] S1002A: For ARP entries of type Layer 3 unicast, the destination IP address in the deleted ARP entry is sent to the second chip, so that the second chip deletes the corresponding destination IP address in the first storage table. When the first chip detects an interface failure, it immediately deletes all ARP entries associated with that interface in its local storage, and simultaneously synchronizes the destination IP address of the deleted entry to the second chip. The second chip then deletes the entry corresponding to that destination IP address in the first storage table, but retains the original content of each entry in the second storage table.

[0072] S1004A: When a new ARP entry is received after the faulty interface is powered on again, the new ARP entry is stored locally and sent to the second chip so that the second chip updates the hash table according to the new ARP entry, stores the destination IP address in the new ARP entry in the first storage table, and first assigns an existing destination MAC address to the destination IP address in the new ARP entry in the second storage table, and then updates the existing destination MAC address to the destination MAC address in the new ARP entry.

[0073] Once the faulty interface recovers and relearns the ARP entries, the first chip synchronizes the new ARP entries to the second chip. At this point, the second chip performs the following operations based on the new ARP entries: updates the hash table that records all ARP entries; writes the destination IP address from the new ARP entry into the first storage table; and then applies a reuse update mechanism to the second storage table. This reuse update mechanism first assigns an existing old MAC address to the new destination IP address, and then immediately overwrites the old destination MAC address with the actual destination MAC address of the new entry.

[0074] In one or more embodiments of this specification, the first chip also stores an index and the type of the index, the index type including Layer 3 unicast; the index is associated with a MAC address in the second storage table. The index is created when the ARP entry is synchronized to the second chip before the interface fails.

[0075] Based on the foregoing, the ARP entry processing method in the embodiments of this specification further includes: Find the index associated with the MAC address in all deleted ARP entries on this chip, and determine whether the type of the ARP entry is Layer 3 unicast based on the type of the index.

[0076] In one or more embodiments of this specification, the second chip further includes a third storage table containing the destination IP address in ARP entries that are not of the Layer 3 unicast type. The ARP entry processing method in the embodiments of this specification further includes: S1002B: For ARP entries that are not Layer 3 unicast, the destination IP address and destination MAC address in the deleted ARP entry are sent to the second chip, so that the second chip deletes the corresponding destination IP address in the third storage table and the destination MAC address in the second storage table.

[0077] S1004B: When a new ARP entry is received after the faulty interface is powered on again, the new ARP entry is stored locally and sent to the second chip so that the second chip updates the hash table according to the new ARP entry, stores the destination IP address in the new ARP entry in the third storage table, and creates a new entry in the second storage table and stores the destination MAC address in the new ARP entry.

[0078] Based on the foregoing embodiments, such as Figure 5 As shown, Figure 5 This is a flowchart illustrating an ARP entry processing method according to another exemplary embodiment of this specification. The ARP entry processing method includes the following steps: S1000: In the event of a detected faulty interface, delete all ARP entries corresponding to the faulty interface on this chip; find the index associated with the MAC address in all ARP entries corresponding to the deleted faulty interface on this chip, and determine whether the type of the ARP entry is Layer 3 unicast based on the type of the index.

[0079] S1002A: For ARP entries of type Layer 3 unicast, the destination IP address in the deleted ARP entry is sent to the second chip, so that the second chip deletes the corresponding destination IP address in the first storage table. When the first chip detects an interface failure, it immediately deletes all ARP entries associated with that interface in its local storage, and simultaneously synchronizes the destination IP address of the deleted entry to the second chip. The second chip then deletes the entry corresponding to that destination IP address in the first storage table, but retains the original content of each entry in the second storage table.

[0080] S1004A: When a new ARP entry is received after the faulty interface is powered on again, the new ARP entry is stored locally and sent to the second chip so that the second chip updates the hash table according to the new ARP entry, stores the destination IP address in the new ARP entry in the first storage table, and first assigns an existing destination MAC address to the destination IP address in the new ARP entry in the second storage table, and then updates the existing destination MAC address to the destination MAC address in the new ARP entry.

[0081] S1002B: For ARP entries that are not Layer 3 unicast, the destination IP address and destination MAC address in the deleted ARP entry are sent to the second chip, so that the second chip deletes the corresponding destination IP address in the third storage table and the destination MAC address in the second storage table.

[0082] S1004B: When a new ARP entry is received after the faulty interface is powered on again, the new ARP entry is stored locally and sent to the second chip so that the second chip updates the hash table according to the new ARP entry, stores the destination IP address in the new ARP entry in the third storage table, and creates a new entry in the second storage table and stores the destination MAC address in the new ARP entry.

[0083] This specification also provides a switching device, which includes the first chip and the second chip provided in the above embodiments.

[0084] This specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method of any embodiment of this disclosure.

[0085] Computer-readable storage media include both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage, quantum memory, graphene-based storage media or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0086] The embodiments of the subject matter and functional operation described in this specification can be implemented in the following ways: digital electronic circuits, tangibly embodied computer software or firmware, computer hardware including the structures disclosed in this specification and their structural equivalents, or combinations thereof. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory program carrier for execution by a data processing apparatus or for controlling the operation of a data processing apparatus. Alternatively or additionally, the program instructions may be encoded on artificially generated propagation signals, such as machine-generated electrical, optical, or electromagnetic signals, which are generated to encode information and transmit it to a suitable receiving device for execution by the data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or combinations thereof.

[0087] The processing and logic flow described in this specification can be executed by one or more programmable computers that execute one or more computer programs to perform corresponding functions by operating on input data and generating output. The processing and logic flow can also be executed by dedicated logic circuitry—such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits), and the device can also be implemented as dedicated logic circuitry.

[0088] Suitable computers for executing computer programs include, for example, general-purpose and / or special-purpose microprocessors, or any other type of central processing unit. Typically, the central processing unit receives instructions and data from read-only memory and / or random access memory. The basic components of a computer include a central processing unit for implementing or executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices for storing data, such as disks, magneto-optical disks, or optical disks, or the computer will be operatively coupled to such mass storage devices to receive data from or transfer data to them, or both. However, a computer is not required to have such devices. Furthermore, a computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device such as a universal serial bus (USB) flash drive, to name a few.

[0089] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, such as semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, and CD-ROM and DVD-ROM disks. Processors and memory may be supplemented by or incorporated into dedicated logic circuitry.

[0090] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope of the claims, but rather are primarily intended to describe features of specific embodiments of a particular invention. Certain features described in the various embodiments herein may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented separately in various embodiments or in any suitable sub-combination. Furthermore, while features may function in certain combinations as described above and even initially claimed in this way, one or more features from a claimed combination may be removed from that combination in some cases, and a claimed combination may refer to a sub-combination or a variation thereof.

[0091] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or requiring all illustrated operations to be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0092] Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings are not necessarily shown in a specific order or sequence to achieve the desired result. In some implementations, multitasking and parallel processing may be advantageous.

[0093] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for processing ARP entries, characterized in that, The method is applied to a first chip in a switching device; the switching device further includes a second chip, and the first chip includes several interfaces for communicating with other network devices; the first chip is used to obtain ARP entries sent by other network devices through the interfaces, store them locally, and synchronize the ARP entries to the second chip, wherein the type of the ARP entries includes Layer 3 unicast; the second chip includes a hash table for storing ARP entries, as well as a first storage table and a second storage table, wherein the first storage table is used to store the destination IP address in the Layer 3 unicast ARP entries, and the second storage table is used to store the destination MAC address in the ARP entries; The method includes: If a faulty interface is detected, all ARP entries corresponding to the faulty interface are deleted from this chip. For ARP entries of type Layer 3 unicast, the destination IP address in the deleted ARP entry is sent to the second chip, so that the second chip deletes the corresponding destination IP address in the first storage table; When a new ARP entry is received after the faulty interface is powered on again, the new ARP entry is stored locally and sent to the second chip so that the second chip updates the hash table according to the new ARP entry, stores the destination IP address in the new ARP entry in the first storage table, and first assigns an existing destination MAC address to the destination IP address in the new ARP entry in the second storage table, and then updates the existing destination MAC address to the destination MAC address in the new ARP entry.

2. The ARP entry processing method according to claim 1, characterized in that, The first chip also stores an index and the type of the index, the type of which includes Layer 3 unicast; the index is associated with an existing MAC address in the second storage table; the index is created when the ARP entry is synchronized to the second chip before the interface fails. The method further includes: Locate the index associated with the MAC address in all ARP entries corresponding to the deleted faulty interface on this chip, and determine whether the type of the ARP entry is Layer 3 unicast based on the type of the index.

3. The ARP entry processing method according to claim 1, characterized in that, The second chip also includes a third storage table for storing destination IP addresses in ARP entries other than Layer 3 unicast; After deleting all ARP entries corresponding to the faulty interface on this chip, the process further includes: For ARP entries that are not Layer 3 unicast, the ARP entries are synchronized to the second chip in the following way: The destination IP address and destination MAC address in the deleted ARP table entry are sent to the second chip, so that the second chip deletes the corresponding destination IP address and destination MAC address in the third storage table and the second storage table. And when a new ARP entry is received after the faulty interface is powered on again, the new ARP entry is stored locally and sent to the second chip so that the second chip updates the hash table according to the new ARP entry, stores the destination IP address in the new ARP entry in the third storage table, and creates a new entry in the second storage table and stores the destination MAC address in the new ARP entry.

4. The ARP entry processing method according to claim 1, characterized in that, Before sending the new ARP entry to the second chip, the method further includes: Store the new ARP entry in the message queue and send a notification to the faulty interface to stop the faulty interface from sending the ARP entry again. The new ARP entry is asynchronously retrieved from the message queue to send the new ARP entry to the second chip.

5. A chip suitable for switching equipment, characterized in that, The switching device further includes a second chip, which includes several interfaces for communicating with other network devices. The chip is used to obtain ARP entries sent by other network devices through the interfaces, store them locally, and synchronize the ARP entries to the second chip. The type of the ARP entries includes Layer 3 unicast. The second chip includes a hash table for storing ARP entries, a first storage table, and a second storage table. The first storage table is used to store the destination IP address in the Layer 3 unicast ARP entries, and the second storage table is used to store the destination MAC address in the ARP entries. The chip is used to delete all ARP entries corresponding to the faulty interface on its own chip when a faulty interface is detected, and to synchronize the ARP entries for Layer 3 unicast ARP entries to the second chip in the following manner: The destination IP address in the deleted ARP table entry is sent to the second chip, so that the second chip deletes the corresponding destination IP address in the first storage table; When a new ARP entry is received after the faulty interface is powered on again, the new ARP entry is stored locally and sent to the second chip. This allows the second chip to update the hash table based on the new ARP entry, store the destination IP address in the new ARP entry in the first storage table, and first allocate an existing destination MAC address to the destination IP address in the new ARP entry in the second storage table, and then update the existing destination MAC address to the destination MAC address in the new ARP entry.

6. The chip according to claim 5, characterized in that, The chip also stores an index and the type of the index, the type of which includes Layer 3 unicast; the index is associated with a MAC address already existing in the second storage table; the index is created when the ARP entry is synchronized to the second chip before the interface fails. The chip is also used to find the index associated with the MAC address in all ARP entries corresponding to the deleted faulty interface on the chip, and to determine whether the type of the ARP entry is Layer 3 unicast based on the type of the index.

7. The chip according to claim 5, characterized in that, The second chip also includes a third storage table for storing destination IP addresses in ARP entries other than Layer 3 unicast; The chip is also used to synchronize non-Layer 3 unicast ARP entries to the second chip in the following manner: The destination IP address and destination MAC address in the deleted ARP table entry are sent to the second chip, so that the second chip deletes the corresponding destination IP address and destination MAC address in the third storage table and the second storage table. When a new ARP entry is received after the faulty interface is powered on again, the new ARP entry is stored locally and sent to the second chip so that the second chip updates the hash table according to the new ARP entry, stores the destination IP address in the new ARP entry in the third storage table, and creates a new entry in the second storage table and stores the destination MAC address in the new ARP entry.

8. The chip according to claim 5, characterized in that, The chip is further configured to store the new ARP entry in a message queue before sending the new ARP entry to the second chip, and send a notification to the fault interface to cause the fault interface to stop sending the ARP entry again; and asynchronously retrieve the new ARP entry from the message queue to execute sending the new ARP entry to the second chip.

9. A switching device, characterized in that, Includes the chip as described in any one of claims 5-8 and the second chip.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by a processor, it implements the steps of the method according to any one of claims 1-4.

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