A galvanometer chip, a preparation method of the galvanometer chip and a laser radar

Abstract

This invention discloses a galvanometer chip, a method for fabricating the galvanometer chip, and a lidar. The galvanometer chip includes a chip body, leads, a coil, a reflector, and a magnet. The chip body includes a main body, a rotating part, and a connecting arm. The two ends of the connecting arm are respectively connected to the main body and the rotating part. The rotating part can rotate relative to the main body around the connecting arm. The connecting arm has embedded silicon-doped wires. The leads are disposed in the chip body and connected to one end of the silicon-doped wires. The coil is disposed in the rotating part and connected to the other end of the silicon-doped wires. The reflector is connected to the rotating part. The magnet is disposed adjacent to the chip body and configured to provide a magnetic field to the chip body, so that when the coil is energized, the rotating part and / or the reflector can rotate relative to the main body. This application uses silicon-doped wires embedded in the connecting arm to connect the leads and the coil respectively, avoiding breakage of the leads on the surface when the connecting arm is twisted, thus improving the stability of the galvanometer chip.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of optical devices, and in particular to a galvanometer chip, a method for fabricating the galvanometer chip, and a lidar. Background Technology

[0002] A galvanometer chip is a common optical MEMS (Micro-Electro-Mechanical System) device that can be applied in various industries such as lidar, projection display, and optical communication. Depending on the driving method, galvanometer chips also come in different types. For example, those using electromagnetic driving are called electromagnetic galvanometer chips.

[0003] Currently, commercially available electromagnetic galvanometer chips typically include a magnet, a chip body, a coil, leads, and a reflector. The magnet provides a magnetic field to the chip body, which includes a main body and a rotating part. The reflector is mounted on the rotating part, which is rotatably connected to the main body via a connecting arm. The coil is located on both the main body and the rotating part. When current is applied to the coil, the rotating part rotates, causing the reflector to rotate, thereby reflecting the light incident on the reflector at a controllable angle.

[0004] However, the lead wires on the connecting arm between the rotating part and the main body are at risk of breaking off from the lead wires on the main body during rotation, which is detrimental to the stability of the galvanometer chip. Summary of the Invention

[0005] The main technical problem solved by the embodiments of the present invention is to provide a galvanometer chip that can enhance stability.

[0006] To solve the above-mentioned technical problems, one technical solution adopted in this invention is: providing a galvanometer chip, including a chip body, leads, a coil, a reflector, and a magnet. The chip body includes a main body portion, a rotating portion, and a connecting arm. The two ends of the connecting arm are respectively connected to the main body portion and the rotating portion. The rotating portion can rotate relative to the main body portion around the connecting arm. A doped silicon wire is embedded in the connecting arm. The leads are disposed in the chip body and connected to one end of the doped silicon wire. The coil is disposed in the rotating portion and connected to the other end of the doped silicon wire. The reflector is connected to the rotating portion. The magnet is disposed adjacent to the chip body and is configured to provide a magnetic field to the chip body, such that when the coil is energized, the rotating portion and / or the reflector can rotate relative to the main body portion.

[0007] Optionally, the chip body is provided with a first through hole and a second through hole communicating with the doped silicon wire. The first through hole and the second through hole are spaced apart. The coil includes a first extension portion, and the lead includes a second extension portion. The first extension portion is disposed in the first through hole and connected to one end of the doped silicon wire, and the second extension portion is disposed in the second through hole and connected to the other end of the doped silicon wire.

[0008] Optionally, the coil includes a coil body, a connecting wire, and a transition portion. The connecting wire is built into the chip body, the transition portion is disposed on the rotating portion and connected to the first extension portion, one end of the connecting wire is connected to the transition portion, and the other end of the connecting wire is connected to the inner end of the coil body.

[0009] To solve the above-mentioned technical problems, another technical solution adopted in the embodiments of the present invention is to provide a laser radar, including the above-mentioned galvanometer chip.

[0010] To solve the above-mentioned technical problems, another technical solution adopted in the embodiments of the present invention is: providing a method for fabricating a galvanometer chip, the method comprising: providing a wafer; performing doping treatment on a portion of the wafer to obtain doped silicon wires; fabricating a composite layer on the wafer, the composite layer and the wafer together constituting a substrate; performing a drilling process to obtain a first through-hole and a second through-hole connecting to the doped silicon wires; fabricating a reflector, a coil, and a lead on the composite layer, wherein the coil and the lead are independently arranged, and the coil is connected to the doped silicon wires through the first through-hole, and the lead is connected to the doped silicon wires through the second through-hole; and etching the substrate to obtain a main body, a rotating part, and a connecting arm.

[0011] Optionally, the step of fabricating the reflector, coil, and lead on the composite layer includes: performing a metal deposition process on the composite layer to obtain a first metal layer, wherein the first metal layer includes a first extension and a second extension connected to the doped silicon wire; fabricating a silicon body with a preset pattern on the first metal layer; fabricating a second metal layer on the first metal layer in other areas outside the silicon body; and etching the first metal layer to obtain the reflector, coil, and lead.

[0012] Optionally, the step of preparing a silicon body with a predetermined pattern on the first metal layer includes: preparing a silicon body layer on the first metal layer; and processing the silicon body layer according to a predetermined pattern to obtain a silicon body that forms the outline of the reflector.

[0013] Optionally, the etching process of the substrate to obtain the main body, the rotating part, and the connecting arm includes: etching the substrate from the front to the silicon oxide layer of the wafer to form the upper part of the rotating part and the upper part of the connecting arm, wherein the etched area from the front includes the area between the coil and the lead, and the area between the coil and the silicon body; etching the substrate from the back to the silicon oxide layer of the wafer, wherein the etched area from the back includes the area corresponding to the upper part of the connecting arm and the area corresponding to the reflector; and etching the silicon body and the substrate after the front and back etching processes to obtain the main body, the rotating part, and the connecting arm.

[0014] Optionally, the step of fabricating the composite layer on the wafer includes: fabricating a first silicon layer on the wafer; fabricating a third metal layer on a portion of the first silicon layer; fabricating a second silicon layer on the third metal layer; wherein the first silicon layer, the third metal layer, and the second silicon layer together constitute the composite layer.

[0015] Optionally, before performing a metal deposition process on the composite layer to obtain the first metal layer, the method further includes: performing a drilling process to obtain a third through hole and a fourth through hole that connect to the third metal layer; the first metal layer further includes a third extension and a fourth extension that connect to the third metal layer; the third extension, the fourth extension, and the third metal layer together constitute a connecting line.

[0016] Optionally, the step of fabricating a second silicon layer on the third metal layer includes: fabricating a first sub-silicon layer on the third metal layer; and fabricating a second sub-silicon layer on the first sub-silicon layer, wherein the first sub-silicon layer and the second sub-silicon layer constitute the second silicon layer.

[0017] The beneficial effects of the embodiments of the present invention are as follows: The galvanometer chip provided in this application includes a chip body, leads, a coil, a reflector, and a magnet. The chip body includes a main body portion, a rotating portion, and a connecting arm. The two ends of the connecting arm are respectively connected to the main body portion and the rotating portion. The rotating portion can rotate relative to the main body portion around the connecting arm. A doped silicon wire is embedded in the connecting arm. The leads are disposed in the chip body and connected to one end of the doped silicon wire. The coil is disposed in the rotating portion and connected to the other end of the doped silicon wire. The reflector is connected to the rotating portion. The magnet is disposed adjacent to the chip body and is configured to provide a magnetic field to the chip body, so that when the coil is energized, the rotating portion and / or the reflector can rotate relative to the main body portion. Compared to the method of setting leads to connect the coil on the surface of the connecting arm, this application uses doped silicon wires embedded in the connecting arm to connect the leads on the main body portion and the coil on the rotating portion respectively, avoiding breakage of the leads on the surface of the connecting arm portion when the connecting arm is twisted, thus improving the stability of the galvanometer chip. Attached Figure Description

[0018] Figure 1 This is a top view of a galvanometer chip according to one embodiment of this application;

[0019] Figure 2 yes Figure 1 A sectional view of the structure after being cut along section line AA;

[0020] Figure 3 This is a flowchart of a method for fabricating a galvanometer chip according to another embodiment of this application;

[0021] Figure 4 yes Figure 3 A further detailed step diagram for step S23;

[0022] Figure 5 yes Figure 4 A further detailed step diagram for step S233;

[0023] Figure 6 yes Figure 3 A further detailed step diagram for step S25;

[0024] Figure 7 yes Figure 6 A further detailed step diagram for step S252;

[0025] Figure 8 yes Figure 3 A further detailed step diagram for step S26;

[0026] Figure 9a It is a cross-sectional view of the wafer;

[0027] Figure 9b yes Figure 9a Top view;

[0028] Figure 10a This is a schematic diagram of forming doped silicon wires after doping a wafer;

[0029] Figure 10b yes Figure 10a Top view;

[0030] Figure 11a Is Figure 10a The first silicon layer and the third metal layer are prepared based on this.

[0031] Figure 11b yes Figure 11a Top view;

[0032] Figure 12a This is a cross-sectional view of the base material;

[0033] Figure 12b yes Figure 12a Top view;

[0034] Figure 13a This is a schematic diagram after the first metal layer has been prepared on the substrate;

[0035] Figure 13b yes Figure 13a Top view;

[0036] Figure 14a Is Figure 13a A schematic diagram showing the silicon bulk layer fabricated on top of the existing structure.

[0037] Figure 14b yes Figure 14a Top view;

[0038] Figure 15a Is Figure 14a A schematic diagram showing the silicon body fabricated from the silicon body layer;

[0039] Figure 15b yes Figure 15a Top view;

[0040] Figure 16a Is Figure 15a A schematic diagram showing the fabrication of the second metal layer based on the above.

[0041] Figure 16b yes Figure 16a Top view;

[0042] Figure 17a Yes Figure 16a A schematic diagram of the first metal layer in the structure after etching is shown;

[0043] Figure 17b yes Figure 17a Top view;

[0044] Figure 18a Yes Figure 17a A schematic diagram of the structure after frontal etching is shown;

[0045] Figure 18b yes Figure 18a Top view;

[0046] Figure 19a Yes Figure 18a A schematic diagram of the structure after back-side etching is shown;

[0047] Figure 19b yes Figure 19a Top view;

[0048] Figure 20a Yes Figure 19a A schematic diagram of the structure after corrosion treatment is shown;

[0049] Figure 20b yes Figure 20aTop view;

[0050] In the diagram: 1. Galvanometer chip; 2. Chip body; 3. Coil; 4. Lead wire; 5. Reflector; 6. Magnet; 7. Pad;

[0051] 21. Main body; 22. Connecting arm; 23. Rotating part; 222. Doped silicon wire; 231. Cantilever beam;

[0052] 2a. First through hole; 2b. Second through hole; 2c. Third through hole; 2d. Fourth through hole;

[0053] 31. First extension; 32. Ring body; 33. Connecting line; 34. Transition section;

[0054] 41. Second extension;

[0055] 10. Wafer; 20. Composite layer; 30. Substrate; 40. First metal layer; 50. Silicon bulk layer; 51. Silicon bulk; 60. Second metal layer;

[0056] 201. First silicon layer; 202. Third metal layer; 203. Second silicon layer;

[0057] 2031, First sub-silicon layer; 2032, Second sub-silicon layer;

[0058] 301. Third extension; 302. Fourth extension. Detailed Implementation

[0059] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "vertical," "horizontal," etc., used in this specification indicate orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0060] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0061] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0062] like Figure 1-2 As shown, one embodiment of the present application provides a galvanometer chip 1, which includes a chip body 2, a coil 3, a lead wire 4, a reflector 5, and a magnet 6.

[0063] The chip body 2 includes a main body 21, a rotating part 23, and a connecting arm 22. The two ends of the connecting arm 22 are connected to the main body 21 and the rotating part 23, respectively. The rotating part 23 can rotate relative to the main body 21 around the connecting arm 22. A silicon-doped wire 222 is embedded in the connecting arm 22. A lead 4 is disposed on the chip body 2 and connected to one end of the silicon-doped wire 222. A coil 3 is disposed on the rotating part 23 and connected to the other end of the silicon-doped wire 222. A reflector 5 is connected to the rotating part 23. A magnet 6 is spaced apart from the chip body 2 and provides a magnetic field to the chip body 2, so that when the coil 3 is energized, it drives the rotating part 23 to move, thereby causing the reflector 5 to deflect and rotate.

[0064] Compared to the method of setting the lead wire 4 to connect the coil 3 on the surface of the connecting arm 22, this application connects the lead wire 4 on the main body 21 and the coil 3 on the rotating part 23 respectively through the doped silicon wire 222 built into the connecting arm 22. This is beneficial to avoid problems such as displacement, detachment or breakage of the lead wire 4 due to setting the lead wire 4 on the surface of the connecting arm 22 when the connecting arm 22 is in continuous torsional motion, which is beneficial to improving the reliability and service life of the galvanometer chip 1.

[0065] In some embodiments, the rotating part 23 includes two cantilever beams 231 connected to the reflector 5. The two cantilever beams 231 are arranged on the same straight line and located on both sides of the reflector 5, which is beneficial for the force balance of the reflector 5. Under the action of the two cantilever beams 231, the reflector 5 can rotate relative to the rotating part 23 after a drive signal is passed through the lead wire 4 and the coil 3 to adjust the deflection position of the reflector, thereby reflecting the light that shines on the reflector 5.

[0066] Understandably, a driving signal (including a fast-axis driving signal and a slow-axis driving signal) is fed into coil 3 via lead 4. This driving signal drives the galvanometer chip 1 to move around the fast axis and around the slow axis, causing the light rays incident on the reflector 5 to be reflected at different angles. The fast-axis driving signal is a sinusoidal signal, which can drive the reflector 5 to a resonant motion state in the fast-axis direction. The slow-axis driving signal is a linear signal, such as a sawtooth wave, which drives the reflector 5 to move at a uniform speed in the slow-axis direction. The fast-axis driving signal and the slow-axis driving signal are superimposed to form the driving signal for the galvanometer. To facilitate understanding how the galvanometer chip 1 achieves reflection, [further details are needed]. Figure 1 Taking the directions shown in the diagram as an example, the first direction X is the direction of the fast axis, and the second direction Y is the direction of the slow axis, which is perpendicular to the first direction X. When a drive signal is applied to the coil 3, the coil 3 will be subjected to an Ampere force, causing the reflector 5 and the rotating part 23 to twist around the first direction X with the connecting arm 22 as the axis of rotation. At the same time, the reflector 5 can rotate relative to the rotating part 23 along the second direction Y with the cantilever beam 231 as the axis of rotation, thereby changing the position of the reflector 5 to achieve two-dimensional scanning.

[0067] In some embodiments, the rotating part 23 and the main body part 21 are connected by two connecting arms 22, such as Figure 2 As shown, both connecting arms 22 can be connected to the lead wire 4 and the coil 3 by means of built-in doped silicon wires 222. This is beneficial for both sides of the rotating part 23 to be subjected to force, and for the rotating part 23 to be subjected to force balance, so that the rotating part 23 can rotate stably.

[0068] For ease of description, the following will only take one of the connecting arms 22 with built-in doped silicon conductors as an example to explain in detail how the doped silicon conductor 222 is connected to both the coil 3 and the lead 4.

[0069] In some embodiments, such as Figure 2 As shown, the chip body 2 has a first through-hole 2a and a second through-hole 2b communicating with the doped silicon wire 222. The first through-hole 2a and the second through-hole 2b are spaced apart. The coil 3 includes a first extension 31, and the lead 4 includes a second extension 41. The first extension 31 is disposed in the first through-hole 2a and connected to one end of the doped silicon wire 222, and the second extension 41 is disposed in the second through-hole 2b and connected to the other end of the doped silicon wire 222. In this way, it is not necessary to set the lead 4 on the surface of the connecting arm 22. The connection between the lead 4 and the coil 3 can be achieved directly through the doped silicon wire 222 built into the connecting arm 22. This avoids the problem of the lead 4 on its surface breaking, shifting, or falling off when the connecting arm 22 is in a continuous torsional motion during operation, reducing the risk of failure of the galvanometer chip 1 and improving the reliability and service life of the galvanometer chip 1.

[0070] It should be noted here that, as Figure 2 As shown, the chip body 2 refers to a silicon-based structure consisting of a wafer 10, a first silicon layer 201, a first sub-silicon layer 2031, and a second sub-silicon layer 2032. The first silicon layer 201 is disposed on one surface of the wafer 10, the first sub-silicon layer 2031 is disposed on the surface of the first silicon layer 201 opposite to the wafer 10, and the second sub-silicon layer 2032 is disposed on the surface of the first sub-silicon layer 2031 opposite to the first silicon layer 201.

[0071] Understandably, coil 3 is wound around rotating part 23, and both ends of coil 3 (i.e., the inner end and the outer end) need to be connected to leads 4 to receive drive signals. However, if the inner end of coil 3 directly passes through the coil body wound around rotating part 23 and connects to the silicon-doped wire 222, it will cause a short circuit. Therefore, it is necessary to offset the inner end of coil 3 from the coil body wound around rotating part 23 to avoid short circuits. One solution is as follows:

[0072] In some embodiments, such as Figure 2 As shown, the coil 3 includes a coil body 32, a connecting wire 33, and a transition portion 34. The connecting wire 33 is built into the chip body 2, and the transition portion 34 is disposed on the rotating portion 23 and connected to the first extension portion 31. One end of the connecting wire 33 is connected to the transition portion 34, and the other end of the connecting wire 33 is connected to the inner end of the coil body 32. The connecting wire 33 is located below the coil body 32 and is spaced apart. In this way, the inner end of the coil 3 can be connected to the transition portion 34 through the connecting wire 33, and the transition portion 34 is indirectly connected to the lead wire 4 through the silicon doped wire 222, thus avoiding short circuits.

[0073] Of course, the connection between coil 3 and lead wire 4 can also be other, and is not limited to the connection methods described above. For example, one end of connecting wire 33 is directly connected to the first extension 31, and the other end of connecting wire 33 is connected to the inner end of coil body 32.

[0074] In some embodiments, there are two magnets 6, which are respectively arranged around the chip body 2. The two magnets 6 provide a magnetic field to the coil of the chip body 2. The two magnets 6 can provide a magnetic field of any angle to the coil 3 and the reflector 5 on the chip body 2, as long as it can drive the coil 3 and the reflector 5 to rotate.

[0075] In some embodiments, such as Figure 1As shown, the galvanometer chip 1 also includes pads 7, which are disposed at the ends of the leads 4. The pads 7 are used to connect with external devices to input drive signals to the galvanometer chip 1. In this embodiment, the lead 4 has two ends, and the number of pads 7 is two. One end of the lead 4 is provided with a pad 7, and one end of the lead 4 is used as an input line for the drive signal, while the other end of the lead 4 is used as an output line for the drive signal.

[0076] Understandably, the aforementioned galvanometer chip 1 can be used in lidar, projection display devices, optical communication devices, etc., as long as it requires control of light reflection.

[0077] Another embodiment of this application provides a lidar including the aforementioned galvanometer chip 1. Understandably, the transmitting device in the lidar generates and emits outgoing light, which is reflected by the galvanometer chip in the scanning system and then sent to the lidar's detection area for scanning. When the outgoing light encounters an object, it is reflected back as echo light. At this time, the lidar's receiving device receives the echo light, processes it, converts it into an electrical signal, and performs signal processing, thereby completing one detection operation.

[0078] like Figure 3 As shown, another embodiment of this application provides a method for fabricating a galvanometer chip 1, the method comprising:

[0079] Step S21: Provide wafer 10, such as Figure 9a and Figure 9b As shown.

[0080] Wafer 10 refers to the silicon structure used in the fabrication of silicon semiconductor integrated circuits. In some embodiments, wafer 10 is an SOI wafer. SOI (Silicon-On-Insulator) wafers are an advanced semiconductor material characterized by the addition of an insulator layer between silicon structures. This insulator layer is typically silicon dioxide, which significantly reduces parasitic capacitance between transistors and improves integrated circuit performance. That is, in its pure state, silicon is an insulator and does not conduct electricity. By introducing appropriate amounts of impurities (such as boron or phosphorus) into the silicon crystal through doping techniques, it can be transformed into a semiconductor. These impurities can release free electrons or form holes, thereby improving the conductivity of silicon. In this embodiment, wafer 10 is a P-type doped SOI wafer or an N-type doped SOI wafer.

[0081] Step S22: Perform doping treatment on a portion of wafer 10 to obtain doped silicon wires 222.

[0082] Doping refers to the process of adding specific impurities (such as boron or phosphorus) to semiconductor materials to alter their electrical, optical, or physical properties. Common methods include N-type doping and P-type doping. The doping process typically includes photolithography, elemental ion implantation, resist removal, annealing, and oxide layer removal. In some embodiments, such as... Figure 10a and Figure 10b As shown, doping a portion of wafer 10 refers to N-type doping, resulting in doped silicon wires 222 formed by an N-type doped silicon structure, with a doping concentration greater than 10e19 cm⁻¹. -3 The doping depth is greater than 0.5 μm. Of course, in other embodiments, the doped silicon wire 222 can also be formed by P-type doping of the P-type doped silicon structure.

[0083] The aforementioned portion of wafer 10 refers to the area pre-selected for fabricating the connecting arm 22 during the fabrication of the galvanometer chip 1.

[0084] Step S23: A composite layer 20 is prepared on wafer 10. The composite layer 20 and wafer 10 together constitute the substrate 30.

[0085] In some embodiments, please refer to Figure 4 The steps for fabricating the composite layer 20 on wafer 10 include:

[0086] Step S231: Fabricate a first silicon layer 201 on wafer 10, such as... Figure 11a and Figure 11b As shown.

[0087] There are several ways to prepare the first silicon layer 201. For example, it can be prepared using chemical vapor deposition (CVD). CVD is a process that utilizes the chemical reaction of gas on a solid surface to produce solid deposition. Its basic principle is a gas-phase reaction at high temperature, such as the thermal decomposition of metal halides, organometallic compounds, hydrocarbons, etc., hydrogen reduction, or causing a chemical reaction of its mixed gas at high temperature to precipitate inorganic materials such as metals, oxides, and carbides.

[0088] Step S232: Fabricate a third metal layer 202 on a portion of the first silicon layer 201, such as... Figure 11a and Figure 11b As shown.

[0089] A portion of the first silicon layer 201 refers to the area where the predetermined connecting line 33 is located in the galvanometer chip 1.

[0090] The third metal layer 202 can be prepared through metal deposition, photolithography, metal etching, and resist stripping. Metal deposition involves depositing metal material onto the surface of a substrate (i.e., the first silicon layer 201 in this step) using electrochemical deposition or physical vapor deposition to form a thin metal film or coating. Photolithography is a precision surface processing technique that combines pattern copying and etching to create patterns on a thin film on a wafer surface. It achieves precise microchip fabrication by mapping a pattern formed by a light source through a mask onto a photoresist layer. Resin stripping refers to the process of removing the remaining photoresist and its residues from the wafer surface after etching or ion implantation.

[0091] The metal material forming the third metal layer 202 can be a Ti or Au metal film, or a semiconductor metal material such as Pt, Al, or Cr, or a combination of these metal materials.

[0092] Step S233: Prepare a second silicon layer 203 on the third metal layer 202.

[0093] In some embodiments, please refer to Figure 5 The step of fabricating the second silicon layer 203 on the third metal layer 202 includes:

[0094] Step S2331: Prepare a first sub-silicon layer 2031 on the third metal layer 202, such as... Figure 12a and Figure 12b As shown.

[0095] The first sub-silicon layer 2031 can be silicon oxide or a silicon layer formed of other insulating materials.

[0096] Step S2332: A second sub-silicon layer 2032 is fabricated on the first sub-silicon layer 2031. The first sub-silicon layer 2031 and the second sub-silicon layer 2032 constitute the second silicon layer 203. The first silicon layer 201, the third metal layer 202, and the second silicon layer 203 together constitute the composite layer 20, as shown below. Figure 12a and Figure 12b As shown.

[0097] The second sub-silicon layer 2032 can be silicon nitride or a silicon layer structure formed of other insulating materials. In this embodiment, both the first sub-silicon layer 2031 and the second sub-silicon layer 2032 can be fabricated using a CVD process.

[0098] Step S24: Perform a drilling process to obtain a first through-hole 2a and a second through-hole 2b connecting to the doped silicon wire 222, as shown below. Figure 12a and Figure 12b As shown.

[0099] The drilling process refers to the fabrication of through-holes that connect to the doped silicon wires 222 through photolithography, dielectric etching, and resist removal processes.

[0100] Die etching refers to the process in semiconductor manufacturing where physical or chemical methods are used to remove or alter specific dielectric materials (such as silicon dioxide, silicon nitride, etc.). It typically includes two types: wet etching and dry etching. Wet etching is a method that uses a chemical etchant to react with the dielectric material to remove it. Dry etching is a technique that uses physical or chemical methods to remove dielectric materials in a vacuum or low-pressure environment.

[0101] The drilling process is applied to the multilayer structure located above the doped silicon wires 222 prior to this step. In this embodiment, the drilling process applies to the first silicon layer 201 and the second silicon layer 203.

[0102] Step S25: A reflector 5, a coil 3, and a lead 4 are fabricated on the composite layer 20. The coil 3 and the lead 4 are set independently, and the coil 3 is connected to the doped silicon wire 222 through the first through hole 2a, and the lead 4 is connected to the doped silicon wire 222 through the second through hole 2b.

[0103] Please see Figure 6 The steps of fabricating the reflector 5, coil 3, and lead 4 on the composite layer 20 include:

[0104] Step S251: Perform a metal deposition process on the composite layer 20 to obtain a first metal layer 40, wherein the first metal layer 40 includes a first extension 31 and a second extension 41 connected to the doped silicon wire 222, such as... Figure 13a and Figure 13b As shown.

[0105] The metals used in metal deposition processes can be Ti or Au metal films, semiconductor metals such as Pt, Al, and Cr, or combinations of these metal materials.

[0106] Understandably, during the metal deposition process on the composite layer 20, some metal material will enter the first through hole 2a and the second through hole to form the first extension 31 and the second extension 41. Both the first extension 31 and the second extension 41 can form ohmic contact with the doped silicon wire 222 through a high-temperature annealing process.

[0107] An ohmic contact is a contact between a metal and a semiconductor, where the resistance of the contact surface is much smaller than the resistance of the semiconductor itself. In an ohmic contact, no significant potential barrier is formed between the metal and the semiconductor, allowing electrons to pass freely through the contact surface and form a good current path.

[0108] Step S252: Prepare a silicon body 51 with a preset pattern on the first metal layer 40.

[0109] Please see Figure 7 The step of fabricating a silicon body 51 with a predetermined pattern on the first metal layer 40 includes two steps:

[0110] Step S2521: Prepare a silicon bulk layer 50 on the first metal layer 40, such as... Figure 14a and Figure 14b As shown.

[0111] The silicon bulk layer 50 can be fabricated using CVD technology, or it can be fabricated using other methods.

[0112] Step S2522: Process the silicon layer 50 according to a predetermined pattern to obtain a silicon body 51 that forms the outline of the reflector 5, such as... Figure 15a and Figure 15b As shown.

[0113] The silicon body layer 50 is processed by photolithography, dielectric etching and resist removal processes to remove excess portions of the silicon body layer 50 and form a silicon body 51 with a pre-defined outline of the reflector 5.

[0114] Step S253: Fabricate a second metal layer 60 on the first metal layer 40 in areas other than the silicon bulk 51, such as... Figure 16a and Figure 16b As shown.

[0115] The areas of the first metal layer 40 other than the silicon body 51 refer to the areas of the first metal layer 40 other than the area occupied by the silicon body 51.

[0116] The second metal layer 60 is the basic structure for forming the coil 3 and the lead 4, and its shape is approximately the same as that of the coil 3 and the lead 4 of the galvanometer chip 1 in the above embodiment. The second metal layer 60 can be prepared by photolithography, electroplating gold, and resist removal processes. The thickness of the electroplated gold layer is generally 0.5 to 50 μm.

[0117] Step S254: Etch the first metal layer 40 to obtain the reflector 5, coil 3, and lead 4, as shown. Figure 17a and Figure 17b As shown.

[0118] The first metal layer 40 is etched in the area outside the second metal layer 60 and the silicon body 51, thereby exposing the composite layer 20 under these areas to separate the metal materials forming the reflector 5, coil 3 and lead 4, so that these metal materials are insulated from each other.

[0119] Etching can be performed using I-BE (Ion Beam Etching) or RIE (Reactive Ion Etching) processes, or other methods. I-BE etching is a dry etching technique that uses an ion beam to react physically or chemically with the material surface to remove material, thus achieving precise pattern transfer. RIE etching uses a high-energy ion beam to bombard the surface of the object being etched, while simultaneously introducing reactive gases. Collisions between the ion beam and gas molecules generate chemically active groups and ions. These high-energy ions and active groups react chemically with the surface of the material being etched, thereby removing unwanted material.

[0120] Step S26: Etch the substrate 30 to obtain the main body 21, the rotating part 23 and the connecting arm 22.

[0121] Please see Figure 8 The steps of etching the substrate 30 to obtain the main body 21, the rotating part 23, and the connecting arm 22 include:

[0122] Step S261: The substrate 30 is etched from the front to the silicon oxide layer of the wafer 10 to form the upper part of the rotating part 23 and the upper part of the connecting arm 22. The etched areas include the region between the coil 3 and the lead 4, and the region between the coil 3 and the silicon body 51, such as... Figure 18a and Figure 18b As shown.

[0123] Front-side etching includes front-side photolithography, dielectric etching, deep silicon etching, and resist stripping. Deep silicon etching stops at the silicon oxide layer on wafer 10.

[0124] The basic principle of front-side photolithography is to replicate the same pattern on a photomask onto a silicon wafer. Specifically, positive photoresist undergoes a photochemical reaction when exposed to light of a specific wavelength or an electron beam. The photoresist in the exposed areas becomes more soluble in the developer, thus being removed during development. Meanwhile, the unexposed photoresist beneath the photomask remains on the silicon wafer. In this way, the pattern on the photomask is precisely replicated and transferred to the silicon wafer.

[0125] Deep silicon etching works by alternating etching and passivation (deposition) steps in a plasma system. Specifically, the plasma etches the silicon substrate, while polymer passivation forms a protective film on the silicon sidewalls to prevent lateral etching.

[0126] Step S262: Back-side etching is performed on the substrate 30 down to the silicon oxide layer of the wafer 10. The back-side etched areas include the area corresponding to the upper part of the connecting arm 22 and the area corresponding to the reflector 5, such as... Figure 19a and Figure 19b As shown.

[0127] Backside etching refers to the process of flipping the wafer 10 to the back side and completing the process through photolithography, deep silicon etching, and resist removal.

[0128] Step S263: Etch the silicon body 51 and the substrate 30 after front and back etching to obtain the main body, the rotating part 23, and the connecting arm 22, as shown. Figure 20a and Figure 20b As shown.

[0129] The etching process can be carried out through silicon oxide wet etching, dry etching, or vapor phase etching.

[0130] By etching the silicon body 51 and the substrate 30 after front and back etching, the second silicon layer 203 on the surface of the reflector 5 and the partially exposed silicon oxide layer of the wafer 10 can be removed.

[0131] By using the above steps, the galvanometer chip 1 in the above embodiment can be obtained. The doped silicon wires 222 built into the connecting arm 22 are respectively connected to the lead wire 4 and the coil 3. Compared with the method of directly setting the lead wire 4 to connect the coil 3 on the surface of the connecting arm 22, the situation of the lead wire 4 on the surface of the connecting arm 22 breaking and falling off when the connecting arm 22 rotates is avoided, which is beneficial to improving the stability of the galvanometer chip 1.

[0132] Another embodiment of this application provides a method for fabricating the galvanometer chip 1, which differs from the above embodiment in that it further includes the following steps before step S251 in step 25:

[0133] Step S250: Perform a drilling process to obtain a third through hole 2c and a fourth through hole 2d that connect to the third metal layer 202.

[0134] Step S251: Perform a metal deposition process on the composite layer 20 to obtain a first metal layer 40, wherein the first metal layer 40 includes a first extension 31 and a second extension 41 connected to the doped silicon wire 222, and further includes:

[0135] The first metal layer 40 also includes a third extension 301 and a fourth extension 302 that connect the third metal layer 202. The third extension 301, the fourth extension 302 and the third metal layer 202 together form a connecting line 33.

[0136] The third extension 301 is connected to the third metal layer 202 by being disposed in the third through hole 2c, and the fourth extension 302 is connected to the third metal layer 202 by being disposed in the fourth through hole 2d.

[0137] The connecting line 33 obtained by the above steps is located below the coil body 32 of the coil 3 and is spaced apart. This allows the inner end of the coil 3 to be connected to the doped silicon wire 222 through the connecting line 33, avoiding the short circuit caused by the inner end of the coil 3 crossing the coil body 32, which is beneficial to improving the stability of the galvanometer chip 1.

[0138] Another embodiment of this application provides a method for fabricating the galvanometer chip 1, which differs from the above embodiment in that it further includes the following steps:

[0139] Step S27: Cut the etched substrate 30 to obtain the galvanometer chip 1 of the required size.

[0140] The above description is merely an embodiment of the present invention and does not limit the scope of protection of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of protection of the present invention.

Claims

1. A galvanometer chip, characterized by, include: The chip body includes a main body, a rotating part, and a connecting arm. The two ends of the connecting arm are respectively connected to the main body and the rotating part. The rotating part can rotate relative to the main body around the connecting arm. The connecting arm has a single doped silicon wire embedded in it. A lead is disposed on the chip body and connected to one end of the doped silicon wire; A coil is disposed in the rotating part and connected to the other end of the doped silicon wire; The reflector is connected to the rotating part; A magnet is disposed adjacent to the chip body and is configured to provide a magnetic field to the chip body, such that the rotating portion and / or the reflector can rotate relative to the main body when the coil is energized; The chip body has a first through hole communicating with the doped silicon wire. The coil includes a first extension, a coil body, a connecting wire, and a transition portion. The first extension is disposed in the first through hole and connected to one end of the doped silicon wire. The connecting wire is embedded in the chip body. The transition portion is disposed on the rotating portion and connected to the first extension. One end of the connecting wire is connected to the transition portion, and the other end of the connecting wire is connected to the inner end of the coil body.

2. The galvanometer chip according to claim 1, characterized in that, The chip body is provided with a second through hole communicating with the doped silicon wire. The first through hole and the second through hole are spaced apart. The lead includes a second extension, which is disposed in the second through hole and connected to the other end of the doped silicon wire.

3. A lidar, characterized in that, Includes the galvanometer chip as described in any one of claims 1-2.

4. A method for preparing a galvanometer chip as described in claim 1 or 2, characterized in that, The method includes: Provide wafers; A portion of the wafer is doped to obtain doped silicon wires; A composite layer is fabricated on the wafer, and the composite layer and the wafer together constitute a substrate; A drilling process is performed to obtain a first through-hole and a second through-hole that connect to the doped silicon wire; A reflector, a coil, and a lead are fabricated on the composite layer, wherein the coil and the lead are independently disposed, and the coil is connected to the doped silicon wire through the first through-hole, and the lead is connected to the doped silicon wire through the second through-hole; The substrate is etched to obtain the main body, the rotating part, and the connecting arm.

5. The method according to claim 4, characterized in that, The step of fabricating the reflector, coil, and lead on the composite layer includes: A metal deposition process is performed on the composite layer to obtain a first metal layer, wherein the first metal layer includes a first extension and a second extension connected to the doped silicon wire; A silicon body with a predetermined pattern is fabricated on the first metal layer; A second metal layer is formed on a region other than the silicon bulk where the first metal layer is located; The first metal layer is etched to obtain the reflector, coil, and leads.

6. The method according to claim 5, characterized in that, The step of fabricating a silicon body with a predetermined pattern on the first metal layer includes: A silicon bulk layer is fabricated on the first metal layer; The silicon body layer is processed according to a predetermined pattern to obtain a silicon body that forms the outline of the reflector.

7. The method according to claim 5, characterized in that, The etching process on the substrate to obtain the main body, the rotating part, and the connecting arm includes: The substrate is etched from the front to the silicon oxide layer of the wafer to form the upper part of the rotating part and the upper part of the connecting arm, wherein the etched area includes the area between the coil and the lead and the area between the coil and the silicon body; The substrate is back-etched to the silicon oxide layer of the wafer, wherein the back-etched area includes the area corresponding to the upper part of the connecting arm and the area corresponding to the reflector; The silicon body and the substrate after front and back etching are etched to obtain the main body, the rotating part, and the connecting arm.

8. The method according to any one of claims 5-7, characterized in that, The fabrication of the composite layer on the wafer includes: A first silicon layer is fabricated on the wafer; A third metal layer is fabricated on a portion of the first silicon layer; A second silicon layer is prepared on the third metal layer; The first silicon layer, the third metal layer, and the second silicon layer together constitute the composite layer.

9. The method according to claim 8, characterized in that, Before performing a metal deposition process on the composite layer to obtain the first metal layer, the method further includes: A drilling process is performed to obtain a third through hole and a fourth through hole that connect to the third metal layer; The first metal layer further includes a third extension and a fourth extension that connect the third metal layer; the third extension, the fourth extension, and the third metal layer together form a connecting line.

10. The method according to claim 9, characterized in that, The fabrication of the second silicon layer on the third metal layer includes: A first sub-silicon layer is prepared on the third metal layer; A second sub-silicon layer is prepared on the first sub-silicon layer, and the first sub-silicon layer and the second sub-silicon layer constitute the second silicon layer.

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