Physical register allocation method and apparatus

Abstract

The application provides a physical register allocation method and device, the method comprises the following steps: an instruction distribution unit determines the required number of physical registers according to microinstructions; when the number of tokens of idle complete physical registers is greater than or equal to the required number, the corresponding tokens are reduced, and the instruction renaming unit is triggered to allocate the physical registers; when the number of tokens is less than the required number, the physical register allocation is not performed; the instruction renaming unit selects complete or single physical registers that meet the required data size in turn during the physical register allocation, and allocates the corresponding microinstructions; wherein, the single physical register is preferentially selected; when the single physical register is selected, the instruction distribution unit returns the corresponding number of tokens of idle complete physical registers; the register renaming is performed, and the register mapping relationship is updated; and the application can also dynamically adjust the number of complete or single physical registers through a dynamic adjustment mechanism.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more particularly to a method and apparatus for allocating physical registers. Background Technology

[0002] During the microinstruction dispatch phase, the system determines whether the current microinstruction's register requirements are met by splitting idle complete physical registers (pair registers) or merging single physical registers (single registers). During the renaming phase, based on the required data size of the microinstruction, complete physical registers are split or single physical registers are merged in real-time at each clock cycle to satisfy the register requirements. This overall process increases the overhead of decision-making logic, complicates processing logic, and leads to frequent register splitting or merging, resulting in wasted system resources, significant timing pressure, and hindering engineering implementation. Summary of the Invention

[0003] To address the problems existing in the prior art, this invention proposes a physical register allocation method and apparatus. This invention simplifies the token management mechanism by maintaining tokens for idle, complete physical registers, which is beneficial for engineering implementation. When allocating physical registers, the method achieves reasonable allocation based on the required data size and order of microinstructions and the availability of idle physical registers, eliminating the need for real-time splitting and merging of different physical registers. This improves the effective utilization rate of physical registers while meeting the operational needs of different programs, thereby enhancing CPU performance.

[0004] In a first aspect of the present invention, a physical register allocation method is proposed, the method comprising:

[0005] The instruction dispatch unit determines the required number of physical registers based on the microinstructions;

[0006] When the number of tokens for idle complete physical registers is greater than or equal to the required number, the number of tokens for idle complete physical registers corresponding to the required number is reduced, triggering the instruction renaming unit to distribute physical registers;

[0007] When distributing physical registers, the instruction renaming unit selects, according to the required data size and order of the microinstruction, either a complete physical register or a single physical register that meets the required data size from the available complete physical registers and assigns it to the corresponding microinstruction. The bit width of the complete physical register is a preset multiple of the bit width of the single physical register, with single physical registers being preferred. When selecting a single physical register, the instruction distribution unit returns a corresponding number of tokens for available complete physical registers.

[0008] The registers are renamed and the register mapping is updated according to the physical registers allocated by the microinstructions.

[0009] In a second aspect of the present invention, a physical register allocation apparatus is provided, the apparatus comprising: an instruction dispatch unit and an instruction renaming unit;

[0010] The instruction dispatch unit is used to determine the required number of physical registers based on the microinstructions;

[0011] When the number of tokens for idle complete physical registers is greater than or equal to the required number, the number of tokens for idle complete physical registers corresponding to the required number is reduced, triggering the instruction renaming unit to distribute physical registers; when the number of tokens for idle complete physical registers is less than the required number, no physical register distribution is performed.

[0012] The instruction renaming unit is used to, when distributing physical registers, select, from available complete physical registers and single physical registers, a complete physical register or a single physical register that meets the required data size and order of the microinstruction, and allocate it to the corresponding microinstruction; wherein, the bit width of the complete physical register is a preset multiple of the bit width of the single physical register, and single physical registers are preferred; when selecting a single physical register, a corresponding number of tokens for available complete physical registers are added;

[0013] The registers are renamed and the register mapping is updated according to the physical registers allocated by the microinstructions.

[0014] In a third aspect of the present invention, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a physical register allocation method when executing the computer program.

[0015] In a fourth aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing a computer program that, when executed by a processor, implements a physical register allocation method.

[0016] In a fifth aspect of the present invention, a computer program product is provided, the computer program product comprising a computer program that, when executed by a processor, implements a physical register allocation method.

[0017] The physical register allocation method and apparatus proposed in this invention determine the required number of physical registers based on microinstructions through an instruction dispatch unit. When the number of tokens for idle complete physical registers is greater than or equal to the required number, the number of tokens for idle complete physical registers corresponding to the required number is reduced, triggering an instruction renaming unit to distribute physical registers. When the number of tokens for idle complete physical registers is less than the required number, no physical register distribution is performed. When distributing physical registers, the instruction renaming unit selects complete physical registers or single physical registers that meet the required data size from idle complete physical registers and single physical registers according to the required data size and order of the microinstructions, and allocates them to the corresponding microinstructions. The bit width of the complete physical register is a preset multiple of the bit width of the single physical register, with single physical registers being preferred. When selecting a single physical register, the instruction dispatch unit returns a corresponding number of tokens for idle complete physical registers. The physical registers allocated according to the microinstructions are then renamed, and the register mapping relationship is updated. This invention also employs a dynamic adjustment mechanism to dynamically adjust the number of complete physical registers and individual physical registers, making the bit width and number of physical registers more adaptable to microinstructions and meeting the actual needs of different running programs. The overall solution of this invention implements a simple and engineering-friendly physical register allocation scheme, simplifying physical register token management. It eliminates the need for splitting and merging physical registers during instruction dispatch and renaming phases, thus meeting the physical register requirements of microinstructions, saving system computing resources, and allowing for reasonable allocation of physical registers based on the size of the required data, improving the effective utilization rate of physical registers and effectively enhancing CPU performance. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic flowchart of a physical register allocation method according to an embodiment of the present invention.

[0020] Figure 2 This is a schematic diagram of the physical register allocation process according to an embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram of an idle physical register according to a specific embodiment of the present invention.

[0022] Figure 4This is a schematic diagram illustrating the allocation relationship between microinstructions and physical registers in a specific embodiment of the present invention.

[0023] Figure 5 This is a schematic diagram of register information before microinstruction renaming according to a specific embodiment of the present invention.

[0024] Figure 6 This is a schematic diagram of register information after microinstruction renaming according to a specific embodiment of the present invention.

[0025] Figure 7 This is a schematic diagram of the processing relationship after microinstruction execution according to a specific embodiment of the present invention.

[0026] Figure 8 This is a schematic diagram of the dynamic adjustment processing relationship in a specific embodiment of the present invention.

[0027] Figure 9 This is a schematic diagram of a process for dynamically adjusting the number of physical registers based on increasing demand count, according to an embodiment of the present invention.

[0028] Figure 10 This is a schematic diagram of a process for dynamically adjusting the number of physical registers based on the actual number used, according to an embodiment of the present invention.

[0029] Figure 11 This is a schematic diagram of the physical register allocation device architecture according to the first embodiment of the present invention.

[0030] Figure 12 This is a schematic diagram of the physical register allocation device architecture according to the second embodiment of the present invention.

[0031] Figure 13 This is a schematic diagram of the physical register allocation device architecture according to the third embodiment of the present invention.

[0032] Figure 14 This is a schematic diagram of a computer device structure according to an embodiment of the present invention. Detailed Implementation

[0033] The principles and spirit of the invention will now be described with reference to several exemplary embodiments. It should be understood that these embodiments are given merely to enable those skilled in the art to better understand and implement the invention, and are not intended to limit the scope of the invention in any way. Rather, these embodiments are provided to make this disclosure more thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art.

[0034] Those skilled in the art will recognize that embodiments of the present invention can be implemented as a system, apparatus, device, method, or computer program product. Therefore, this disclosure can be specifically implemented in the following forms: entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0035] According to an embodiment of the present invention, a physical register allocation method and apparatus are proposed, relating to the field of computer technology.

[0036] In the embodiments of the present invention, the following terms need to be explained:

[0037] arn: Architecture Register;

[0038] prn: Physical Register;

[0039] pair prn: Complete physical register;

[0040] single prn: a single physical register; a complete physical register can be split into multiple single physical registers;

[0041] token: In the application scenario of this invention, the token represents the free status of the complete physical register and is used to manage the resource allocation and reclamation of the complete physical register.

[0042] The principles and spirit of the present invention will be explained in detail below with reference to several representative embodiments.

[0043] Figure 1 This is a schematic flowchart of a physical register allocation method according to an embodiment of the present invention. Figure 1 As shown, the method includes:

[0044] S101, the instruction dispatch unit determines the required number of physical registers based on the microinstructions.

[0045] In this embodiment, when determining the required number of physical registers, only the total required number of physical registers is counted, without regard to whether the specific requirement is for a complete physical register (pair register) or a single physical register (single register).

[0046] For a complete physical register, its bit width is N bits, for example, 128 bits or 64 bits. A complete physical register can be split into multiple individual physical registers. For example, if a complete physical register is split into two individual physical registers, the bit width of an individual physical register is N / 2 bits. If a complete physical register can be split into four individual physical registers, the bit width of an individual physical register is N / 4 bits.

[0047] S102, compare the number of tokens in the available complete physical registers with the required number;

[0048] When the number of tokens for idle complete physical registers is greater than or equal to the required number, the number of tokens for idle complete physical registers corresponding to the required number is reduced, triggering the instruction renaming unit to distribute physical registers;

[0049] If the number of tokens for an available complete physical register is less than the required number, no physical registers will be distributed.

[0050] In this embodiment, the token management mechanism for physical registers (prn) is simplified, maintaining only the number of complete physical registers. Based on the tokens of the free complete physical registers, it is determined whether the number of free complete physical register tokens can meet the required number of physical registers determined in S101.

[0051] If the requirement is met, subtract the token of the available complete physical register corresponding to the number of requests, and continue with the subsequent steps.

[0052] If the requirement cannot be met, the system waits for the return of a token for an available complete physical register until the required number can be met. That is, if the requirement cannot be met (the number of tokens for available complete physical registers is less than the required number), the instruction renaming unit will not be triggered to distribute physical registers.

[0053] This invention simplifies the management mechanism of physical register tokens, reduces the overhead of judgment logic, and can further optimize the splitting and merging scheme of different physical registers during the renaming stage.

[0054] S103, when distributing physical registers, the instruction renaming unit selects, in sequence, a complete physical register or a single physical register that meets the required data size from the available complete physical registers and single physical registers according to the required data size and order of the microinstruction, and allocates it to the corresponding microinstruction.

[0055] The bit width of the complete physical register is a preset multiple of the bit width of a single physical register (the preset multiple corresponds to the number of single physical registers that the complete physical register can be divided into). When selecting a physical register, if the required data size is met and there are available single physical registers, a single physical register is selected first; when selecting a single physical register, the corresponding number of tokens for available complete physical registers are added.

[0056] In this embodiment, if the instruction dispatch unit finds an available full physical register token corresponding to the required number of instructions in S102, then the microinstruction requirements can be met based on the available full physical registers. To better utilize physical registers, in S103, the present invention employs a physical register selection mechanism. The instruction renaming unit selects a physical register of appropriate size from full physical registers and single physical registers according to the order of microinstructions and the required data size, thereby improving the effective utilization rate of physical registers and thus improving CPU performance.

[0057] When selecting a physical register, if there is a free single physical register that can meet the data size required by the microinstruction, the single physical register is selected first. For example, if the full physical register has a bit width of 64 bits, the single physical register has a bit width of 32 bits, and the microinstruction requires 32 bits of data, the free single physical register is selected if there is one; otherwise, the free full physical register is selected.

[0058] When a single free physical register is selected, a corresponding free full physical register is saved. Therefore, the token of the free full physical register is returned by the instruction renaming unit to the instruction dispatch unit, that is, the token of the free full physical register is added to the instruction dispatch unit.

[0059] S104, rename the registers according to the physical registers allocated by the microinstruction and update the register mapping relationship.

[0060] The physical register allocation scheme proposed in this invention simplifies the physical register token management method. It can meet the physical register requirements of microinstructions without splitting and merging physical registers during instruction dispatch and renaming stages, thus saving system computing resources. At the same time, it can reasonably allocate physical registers based on the size of the required data, improve the effective utilization rate of physical registers, and effectively improve CPU performance.

[0061] To provide a clearer explanation of the above physical register allocation method, a detailed description is provided below with reference to specific embodiments.

[0062] In one embodiment, to select physical registers more efficiently, the present invention uses a physical register free list to record idle physical registers. By updating the free list in real time, it ensures consistent information and efficient and stable operation during physical register allocation. In S103, the instruction renaming unit sequentially selects a complete physical register or a single physical register that meets the required data size and allocates it to the corresponding microinstruction, while synchronously updating the physical register free list. The physical register free list includes a complete physical register free list and a single physical register free list.

[0063] For each free full physical register allocated to a microinstruction, the corresponding free full physical register is removed from the list of free full physical registers.

[0064] For each free single physical register allocated to a microinstruction, the corresponding free single physical register is removed from the free list of said single physical registers.

[0065] In one embodiment, to improve the effective utilization of physical registers, the instruction renaming unit of this invention selects a physical register of appropriate size based on the actual data size required by the microinstruction. Taking n microinstructions in a certain cycle as an example, the microinstructions are arranged in chronological order from the first microinstruction to the nth microinstruction; n is a positive integer representing the number of microinstructions in the current cycle. (See reference...) Figure 2 This is a schematic diagram of the physical register allocation process according to an embodiment of the present invention. Figure 2 As shown, the specific processing procedure is as follows:

[0066] S201, determine whether the data size required by the first microinstruction is less than or equal to the bit width of a single physical register;

[0067] If yes (i.e., the data size required by the first microinstruction is less than or equal to the bit width of a single physical register), execute S202; if no (i.e., the data size required by the first microinstruction is greater than the bit width of a single physical register), execute S204.

[0068] S202, determine whether a single idle physical register is empty; if not empty, execute S203; if empty, execute S204.

[0069] S203, select a single physical register and assign it to the first microinstruction.

[0070] S204, Select a complete physical register and allocate it to the first microinstruction.

[0071] The above process is used to allocate physical registers for the second to nth microinstructions in sequence.

[0072] refer to Figure 3This is a schematic diagram of an idle physical register according to a specific embodiment of the present invention. Figure 3 As shown in the exemplary scenario, the instruction dispatch unit determines the required number of physical registers to be 6 based on the microinstructions. Currently, the number of tokens for available complete physical registers is greater than or equal to 6. Therefore, 6 available complete physical registers can be found through the complete physical register free list, such as... Figure 3 As shown, these are prn_1, prn_2, prn_4, prn_8, prn_10, and prn_18, respectively. Simultaneously, three free individual physical registers were found in the individual physical register free list, as shown... Figure 3 As shown, these are prn_101, prn_103, and prn_109, respectively. In response, the instruction renaming unit is triggered to distribute the physical registers.

[0073] In reality, there may be more free individual physical registers in the single physical register free list. For example, if there are 10 free individual physical registers, then at most 6 free individual physical registers corresponding to the required number can be selected to meet the micro-instruction requirements.

[0074] refer to Figure 4 This is a schematic diagram illustrating the allocation relationship between microinstructions and physical registers according to a specific embodiment of the present invention. Figure 4 As shown in the exemplary scenario, the physical register distribution and renaming process of the instruction renaming unit is as follows:

[0075] Taking a complete physical register (pair PRN) with a bit width of 64 bits and a single physical register (single PRN) with a bit width of 32 bits as an example, such as Figure 4 As shown, the six microinstructions are numbered 0 to 5 in sequence, and the required data sizes are 64 bits, 32 bits, 16 bits, 16 bits, 32 bits, and 64 bits, respectively. Physical registers that meet the required data sizes are allocated for each of the six microinstructions.

[0076] Further integration Figure 3 and Figure 4 As shown, microinstruction 0 requires 64 bits of data and selects the full physical register prn_1;

[0077] Microinstruction 1 requires 32 bits of data and selects a single physical register prn_101;

[0078] Microinstruction 2 requires 16 bits of data and selects a single physical register prn_103;

[0079] Microinstruction 3 requires 16 bits of data and selects a single physical register prn_109;

[0080] The required data size for microinstruction 4 is 32 bits. Based on the required data size, a single physical register is preferred. However, since there is no free single physical register, the complete physical register prn_2 is selected.

[0081] Microinstruction 5 requires 64 bits of data, selects a single physical register prn_4, and the allocation result is referenced. Figure 4 As shown.

[0082] The physical register selection mechanism of this invention ensures the effective utilization of physical registers without requiring complex logic such as complete physical register splitting and individual physical register assembly during the physical register selection stage, which is more conducive to engineering implementation.

[0083] When allocating physical registers to microinstructions, the architecture registers can be renamed sequentially down to the physical registers. (See reference) Figure 5 This is a schematic diagram of register information before microinstruction renaming according to a specific embodiment of the present invention. Figure 5 As shown, in the source register (src reg) and destination register (dest reg) columns, the architecture registers (arn) corresponding to microinstructions 0 to 5 are 0, 1, 2, 1, 4, and 5, respectively, while the physical register information is empty; the register mapping table records the register mapping relationship before renaming.

[0084] Further reference Figure 6 This is a schematic diagram of register information after microinstruction renaming according to a specific embodiment of the present invention. The source register information of each microinstruction can be determined according to... Figure 5 The physical register (prn) corresponding to the architecture register (arn) in the register mapping table is obtained and this information is recorded. Figure 6 In the source register corresponding to the microinstruction.

[0085] The destination register information for each microinstruction needs to be determined based on the allocation relationship between physical registers and microinstructions (see reference). Figure 4 ), record the selected physical register to Figure 6 In the destination register corresponding to the microinstruction, the physical register corresponding to the architecture register in the register mapping table is updated to the physical register allocated by the microinstruction.

[0086] For microinstruction 0, based on Figure 5 The register mapping table, in Figure 6 In the source register information, arn is 0, and the corresponding prn is prn_3;

[0087] according to Figure 4The physical register allocated by the micro-instruction has a corresponding prn value of prn_1 in the destination register information; simultaneously update Figure 6 The corresponding prn in the register mapping table is: prn_1.

[0088] For microinstruction 1, Figure 6 In the source register information, arn is 1, and the corresponding prn is prn_5;

[0089] The corresponding prn in the destination register information is: prn_101; simultaneously update Figure 6 The corresponding prn in the register mapping table is: prn_101.

[0090] For microinstruction 2, Figure 6 In the source register information, arn is 2, and the corresponding prn is prn_6;

[0091] The corresponding prn in the destination register information is: prn_103; simultaneously update Figure 6 The corresponding prn in the register mapping table is: prn_103.

[0092] For microinstruction 3, Figure 6 In the source register information, arn is 1, and the corresponding prn is prn_101 (updated to prn_101 in microinstruction 1);

[0093] The corresponding prn in the destination register information is: prn_109; simultaneously update Figure 6 The corresponding prn in the register mapping table is: prn_109.

[0094] For microinstruction 4, Figure 6 In the source register information, arn is 4 and the corresponding prn is prn_102;

[0095] The corresponding prn in the destination register information is prn_2; simultaneously update Figure 6 The corresponding prn in the register mapping table is: prn_2.

[0096] For microinstruction 5, Figure 6 In the source register information, arn is 5 and the corresponding prn is prn_104;

[0097] The corresponding prn in the destination register information is prn_4; simultaneously update Figure 6 The corresponding prn in the register mapping table is: prn_4.

[0098] Since arn 3 was not renamed, therefore, Figure 6In the register map table, the prn corresponding to arn 3 remains unchanged as prn_7.

[0099] In one embodiment, reference Figure 7 This is a schematic diagram illustrating the processing relationship after microinstruction execution in a specific embodiment of the present invention. Figure 7 As shown, in order to record available physical registers and ensure the normal execution of subsequent microinstructions, the scheduling execution unit updates the physical register free list after the (current) microinstruction has been executed. The physical register free list includes: a complete physical register free list and a single physical register free list.

[0100] Specifically, after the microinstruction is executed, the corresponding number of tokens for the free full physical registers are added to the instruction dispatch unit based on the number of full physical registers corresponding to the execution of this microinstruction; for a single physical register corresponding to the execution of this microinstruction, the token is not updated.

[0101] Add the complete physical register corresponding to the microinstruction executed to the complete physical register free list;

[0102] The single physical register corresponding to the execution of this microinstruction is added to the free list of the single physical register.

[0103] In the application scenario of physical register allocation in this application, the complete physical register free list and the single physical register free list are mainly used to record free complete physical registers and single physical registers. However, when managing physical register tokens, this invention mainly focuses on the tokens of free complete physical registers. The reduction logic for the tokens of free complete physical registers mainly adopts two methods:

[0104] 1. Based on the required number of physical registers in S102, reduce the corresponding number of free complete physical register tokens.

[0105] 2. When dynamically adjusting the number of complete physical registers, the tokens of the idle complete physical registers are adjusted accordingly; the dynamic adjustment logic involved in the second method will be explained in the following embodiments.

[0106] For tokens in idle, complete physical registers, the logic for adding them mainly employs three methods:

[0107] 1. When selecting an idle physical register (prn) in S103, for each idle single physical register selected, one idle complete physical register will not be selected. Accordingly, in the current step (i.e., the renaming phase), a token of an idle complete physical register is returned to the instruction dispatch unit, that is, a token of an idle complete physical register is added to the instruction dispatch unit.

[0108] 2. After the microinstruction is executed, add a token to the idle complete physical register that executed the microinstruction.

[0109] 3. When dynamically adjusting the number of complete physical registers, the tokens of the idle complete physical registers are adjusted accordingly; the dynamic adjustment logic involved in the third method will be explained in the following embodiments.

[0110] The token processing mechanism of this invention only maintains tokens for idle complete physical registers. Compared with processing tokens for both idle complete physical registers and tokens for idle complete physical registers at the same time, this invention does not need to maintain tokens for a single idle physical register, which greatly simplifies the token processing logic and is more conducive to engineering implementation.

[0111] In this embodiment, the number of complete physical registers and single physical registers can be set according to the CPU's architecture. In practical applications, to better execute microinstructions and allocate physical registers with more suitable bit widths, this invention employs a dynamic adjustment mechanism to dynamically adjust the number of the two types of physical registers (complete and single) to adapt to the actual needs of different running programs.

[0112] refer to Figure 8 The diagram shown illustrates the dynamic adjustment processing relationship according to a specific embodiment of the present invention. Figure 8 As shown, the number of complete physical registers and the number of individual physical registers are dynamically adjusted through the physical register quantity dynamic adjustment subunit.

[0113] The dynamic adjustment mechanism is as follows: at each interval counting cycle, based on the number of complete physical registers, the number of individual physical registers, the number of idle complete physical registers, and the number of idle individual physical registers, the number of complete physical registers and the number of idle individual physical registers are dynamically adjusted under preset conditions.

[0114] In this embodiment, the present invention uses the increase demand count results from a counter to reflect the demand of different physical registers, thereby dynamically adjusting the number of different physical registers. (Reference) Figure 9 This is a schematic diagram illustrating the process of dynamically adjusting the number of physical registers based on increasing demand counting, according to an embodiment of the present invention. Figure 9 As shown, the specific process of dynamically adjusting the number of physical registers is as follows:

[0115] S901 counts the number of idle complete physical registers and individual physical registers for each clock cycle within the counting period;

[0116] S902, if the idle complete physical register is empty and the idle single physical register is not empty, increment the demand count corresponding to the complete physical register by 1;

[0117] S903, if the free complete physical register is not empty and the free single physical register is empty, increment the demand count corresponding to the single physical register by 1;

[0118] The counting period includes a preset number of clock beats;

[0119] S904, at the end of the counting cycle, if the number of complete physical registers does not reach the preset upper limit of complete physical registers, the number of individual physical registers does not reach the preset lower limit of individual physical registers, and the increase demand count result corresponding to complete physical registers minus the increase demand count result corresponding to individual physical registers is greater than the preset counting threshold, then the number of complete physical registers is increased by the preset number of registers, and the number of individual physical registers is decreased by the preset multiple of the preset number of registers.

[0120] S905, at the end of the counting cycle, if the number of complete physical registers does not reach the preset lower limit of complete physical registers, the number of individual physical registers does not reach the preset upper limit of individual physical registers, and the increase demand count result corresponding to an individual physical register minus the increase demand count result corresponding to a complete physical register is greater than the preset counting threshold, then the number of individual physical registers is increased by a preset multiple of the preset number of registers, and the number of complete physical registers is decreased by the preset number of registers.

[0121] In practice, the preset conditions for dynamically adjusting the number of physical registers mainly take into account the usage of physical registers within the counting cycle and whether the number of physical registers has reached its corresponding upper or lower limit. At each clock tick within the counting cycle, the number of idle complete physical registers and single physical registers is counted. If one is not empty and the other is empty, the demand for the other is increased. At the end of the counting cycle, the increase demand count results for both types of physical registers (complete and single) are obtained, and the difference between the two increase demand count results is calculated.

[0122] If the difference exceeds the preset counting threshold, and the count result for the increase in the number of complete physical registers is relatively large, it indicates that the utilization rate of complete physical registers is higher, and there may be a lot of idle space in the number of individual physical registers. It is advisable to increase the number of complete physical registers and decrease the number of individual physical registers. At the same time, it is also necessary to consider whether the number of complete physical registers has reached its corresponding upper limit and whether the number of individual physical registers has reached its corresponding lower limit. If the number of complete physical registers has not reached its corresponding upper limit and the number of individual physical registers has not reached its corresponding lower limit, then the physical registers should be dynamically adjusted by increasing the number of complete physical registers by the preset number and decreasing the number of individual physical registers by a preset multiple of the preset number of registers.

[0123] Conversely, if the difference exceeds the preset counting threshold, and the increase demand for a single physical register is relatively large, it indicates that the utilization rate of a single physical register is higher, and there may be a lot of idle space in the number of complete physical registers. It is advisable to reduce the number of complete physical registers and increase the number of single physical registers. At the same time, it is also necessary to consider whether the number of single physical registers has reached its corresponding upper limit and whether the number of complete physical registers has reached its corresponding lower limit. If the number of single physical registers has not reached its corresponding upper limit and the number of complete physical registers has not reached its corresponding lower limit, then the physical registers are dynamically adjusted, increasing the number of single physical registers by a preset multiple of the preset number of registers and decreasing the number of single physical registers by the preset number of registers.

[0124] Furthermore, based on the dynamic adjustment mechanism, since the number of complete physical registers and individual physical registers changes, it is necessary to increase or decrease the corresponding number of tokens for idle complete physical registers when increasing or decreasing the preset number of complete physical registers. This corresponds to the second logic of increasing the tokens for idle complete physical registers and the third logic of decreasing the tokens for idle complete physical registers in the previous embodiment, and these two logics are explained.

[0125] Based on the dynamic adjustment mechanism, the complete physical register free list and the individual physical register free list must also be updated synchronously to ensure that the number of tokens in the physical register free list and the free complete physical registers are synchronized with the adjusted information.

[0126] In this embodiment, the number of dynamically adjusted physical registers does not exceed its corresponding upper or lower limit. The specific process is as follows:

[0127] After adding a complete physical register or a single physical register, the number of complete physical registers or the number of single physical registers shall not exceed the corresponding preset upper limit of complete physical registers or the preset upper limit of single physical registers;

[0128] After reducing the number of complete physical registers or individual physical registers, the number of complete physical registers or individual physical registers shall not be less than the corresponding preset lower limit of complete physical registers or preset lower limit of individual physical registers.

[0129] For example, the preset number of registers for dynamic adjustment is 30, and the lower limit of the number of complete physical registers is 80. If the number of complete physical registers before adjustment is 100, after the increase in demand counting in the current counting cycle, the number of complete physical registers needs to be reduced. Since 100-30=70, which is less than the lower limit of 80, the number of complete physical registers is adjusted to the lower limit (80), and the number is reduced by 20. Correspondingly, the number of individual physical registers is increased by 20 times the preset multiple.

[0130] In this embodiment, regardless of whether the number of physical registers is adjusted, the increase demand count is cleared to zero at the end of the counting cycle to ensure that the increase demand count restarts at the beginning of the next counting cycle. Specifically, at the end of the current counting cycle, the increase demand count for both the complete physical register and the individual physical register is cleared.

[0131] In this embodiment, the preset number of clock ticks within the counting cycle, the preset counting threshold used when comparing and increasing the required counting result, the preset number of physical registers used when dynamically adjusting the number of physical registers, the preset upper and lower limits of the complete physical registers, and the preset upper and lower limits of a single physical register can all be set according to different CPU architectures.

[0132] The dynamic adjustment mechanism described in the above embodiments reflects the demand for different physical registers based on the increase in the counter's demand count, thereby dynamically adjusting the number of physical registers. In practical applications, other methods can also be used to reflect the demand for different physical registers. For example, by analyzing the actual number of physical registers in use, the percentage of actual use, the number of idle registers, and the percentage of idle registers, it is possible to analyze which physical registers are in greater demand and appropriately increase the number of those physical registers, thus achieving dynamic adjustment of the number of physical registers.

[0133] The following analysis examines the actual usage of different physical registers to understand their requirements. During the counting cycle, the number of physical registers used for each clock tick is counted. At the end of the counting cycle, if a particular type of physical register is used significantly (meeting certain conditions), the number of that physical register is appropriately increased.

[0134] refer to Figure 10 This is a schematic diagram illustrating the process of dynamically adjusting the number of physical registers based on the actual number used, according to an embodiment of the present invention. Figure 10As shown, the specific process of dynamically adjusting the number of physical registers is as follows:

[0135] S1001, for each clock tick within the counting cycle, counts the number of complete physical registers and individual physical registers used respectively;

[0136] S1002, at the end of the counting cycle, if the total number of complete physical registers used for all clock ticks is greater than the first usage threshold, the total number of individual physical registers used is less than the second usage threshold, and the number of complete physical registers has not reached the preset upper limit of complete physical registers and the number of individual physical registers has not reached the preset lower limit of individual physical registers, then the number of complete physical registers is increased by the preset number of registers, and the number of individual physical registers is decreased by a preset multiple of the preset number of registers.

[0137] S1003, at the end of the counting cycle, if the total number of individual physical registers used corresponding to all clock ticks is greater than the first usage threshold, the total number of complete physical registers used is less than the second usage threshold, and the number of individual physical registers has not reached the preset upper limit of individual physical registers and the number of complete physical registers has not reached the preset lower limit of complete physical registers, then the number of individual physical registers is increased by a preset multiple of the preset number of registers, and the number of complete physical registers is decreased.

[0138] The first and second usage thresholds can be adjusted according to the actual application scenario. This dynamic adjustment mechanism mainly considers which physical registers are used extensively during the counting cycle and which are used less frequently. In this case, the number of physical registers with high usage will be appropriately increased and the number of physical registers with low usage will be reduced, so that the bit width and number of physical registers are more compatible with the microinstructions and can meet the actual needs of different programs.

[0139] When increasing or decreasing the number of physical registers, the number cannot be greater than or less than the corresponding upper or lower limit of the physical register.

[0140] In this embodiment, similar to other dynamic adjustment mechanisms, after dynamic adjustment, since the number of complete physical registers and individual physical registers changes, it is necessary to increase or decrease the corresponding number of tokens of idle complete physical registers when increasing or decreasing the number of complete physical registers of the preset number.

[0141] Based on the dynamic adjustment mechanism, the complete physical register free list and the individual physical register free list must also be updated synchronously to ensure that the number of tokens in the physical register free list and the free complete physical registers are synchronized with the adjusted information.

[0142] for Figure 10 The dynamic adjustment mechanism can also be applied to indicators such as the proportion of actual usage, the number of idle registers, and the proportion of idle registers, as indicators reflecting different physical register requirements, to dynamically adjust the number of physical registers.

[0143] This invention simplifies the management of physical register tokens (maintaining only complete physical register tokens) without increasing the physical register area. It avoids real-time splitting and merging of different physical registers during instruction dispatch and renaming phases, achieving a physical register allocation method that is beneficial for engineering implementation, improving the effective utilization of physical registers, and thus improving CPU performance. When dynamically adjusting the number of physical registers, it uniformly adjusts according to the physical register requirements based on the counting cycle, avoiding resource waste caused by frequent splitting and merging of physical registers. This application can be applied to scenarios where the number of physical registers is increased while keeping the physical register area constant, or to scenarios where the physical register area is reduced while keeping the number of registers constant.

[0144] It should be noted that although the operation of the method of the present invention has been described in a specific order in the above embodiments and figures, this does not require or imply that the operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0145] After introducing the method of exemplary embodiments of the present invention, the following references are made. Figure 11 The physical register allocation apparatus of an exemplary embodiment of the present invention will be described.

[0146] The implementation of the physical register allocation device can refer to the implementation of the method described above, and will not be repeated here. The terms "module" or "unit" used below can refer to a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0147] Based on the same inventive concept, this invention also proposes a physical register allocation device, such as... Figure 11 As shown, the device includes: an instruction distribution unit 1110 and an instruction renaming unit 1120;

[0148] The instruction dispatch unit 1110 is used to determine the required number of physical registers based on microinstructions;

[0149] When the number of tokens for idle complete physical registers is greater than or equal to the required number, the number of tokens for idle complete physical registers corresponding to the required number is reduced, triggering the instruction renaming unit 1120 to distribute physical registers; when the number of tokens for idle complete physical registers is less than the required number, no physical register distribution is performed.

[0150] The instruction renaming unit 1120 is used to, when distributing physical registers, select, according to the required data size and order of the microinstruction, a complete physical register or a single physical register that meets the required data size from idle complete physical registers and allocate it to the corresponding microinstruction; wherein, the bit width of the complete physical register is a preset multiple of the bit width of the single physical register, and single physical registers are preferred; when selecting a single physical register, a corresponding number of tokens for idle complete physical registers are added;

[0151] The registers are renamed and the register mapping is updated according to the physical registers allocated by the microinstructions.

[0152] refer to Figure 12 This is a schematic diagram of the physical register allocation device architecture according to the second embodiment of the present invention. Figure 12 As shown, the device also includes: a scheduling execution unit 1130;

[0153] The scheduling execution unit 1130 is used to update the physical register free list after the microinstruction is executed.

[0154] The physical register free list includes: the complete physical register free list and a single physical register free list.

[0155] Specifically, after the microinstruction is executed, the corresponding number of tokens for the free full physical registers are added to the instruction dispatch unit based on the number of full physical registers corresponding to the execution of this microinstruction; for a single physical register corresponding to the execution of this microinstruction, the token is not updated.

[0156] Add the complete physical register corresponding to the microinstruction executed to the complete physical register free list;

[0157] The single physical register corresponding to the execution of this microinstruction is added to the free list of the single physical register.

[0158] refer to Figure 13 This is a schematic diagram of the physical register allocation device architecture according to the third embodiment of the present invention. Figure 12 As shown, the instruction renaming unit 1120 also includes: a physical register number dynamic adjustment subunit 1121;

[0159] The physical register quantity dynamic adjustment subunit 1121 is used to dynamically adjust the number of complete physical registers and the number of individual physical registers each time interval counting cycle, based on the number of complete physical registers, the number of individual physical registers, the number of idle complete physical registers, and the number of idle individual physical registers, under the condition that preset conditions are met.

[0160] The specific method for dynamically adjusting the number of physical registers by the physical register quantity dynamic adjustment subunit 1121 can be found in the description of the aforementioned method section, and will not be repeated here.

[0161] It should be noted that although several modules of the physical register allocation device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more modules described above can be embodied in one module. Conversely, the features and functions of one module described above can be further divided and embodied by multiple modules.

[0162] Based on the aforementioned inventive concept, such as Figure 14 As shown, the present invention also proposes a computer device 1400, including a memory 1410, a processor 1420, and a computer program 1430 stored in the memory 1410 and executable on the processor 1420. When the processor 1420 executes the computer program 1430, it implements the aforementioned physical register allocation method.

[0163] Based on the aforementioned inventive concept, the present invention proposes a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the aforementioned physical register allocation method.

[0164] Based on the aforementioned inventive concept, the present invention proposes a computer program product, which includes a computer program that, when executed by a processor, implements a physical register allocation method.

[0165] The physical register allocation method and apparatus proposed in this invention determine the required number of physical registers based on microinstructions through an instruction dispatch unit. When the number of tokens for idle complete physical registers is greater than or equal to the required number, the number of tokens for idle complete physical registers corresponding to the required number is reduced, triggering an instruction renaming unit to distribute physical registers. When the number of tokens for idle complete physical registers is less than the required number, no physical register distribution is performed. When distributing physical registers, the instruction renaming unit selects complete physical registers or single physical registers that meet the required data size from idle complete physical registers and single physical registers according to the required data size and order of the microinstructions, and allocates them to the corresponding microinstructions. The bit width of the complete physical register is a preset multiple of the bit width of the single physical register, with single physical registers being preferred. When selecting a single physical register, the instruction dispatch unit returns a corresponding number of tokens for idle complete physical registers. The physical registers allocated according to the microinstructions are then renamed, and the register mapping relationship is updated. This invention also employs a dynamic adjustment mechanism to dynamically adjust the number of complete physical registers and individual physical registers, making the bit width and number of physical registers more adaptable to microinstructions and meeting the actual needs of different running programs. The overall solution of this invention implements a simple and engineering-friendly physical register allocation scheme, simplifying physical register token management. It eliminates the need for splitting and merging physical registers during instruction dispatch and renaming phases, thus meeting the physical register requirements of microinstructions, saving system computing resources, and allowing for reasonable allocation of physical registers based on the size of the required data, improving the effective utilization rate of physical registers and effectively enhancing CPU performance.

[0166] This application employs a dynamic adjustment mechanism to uniformly split and merge physical registers, reducing the number of splits and merges and saving system resources. By setting a period (i.e., the counting period in the embodiment) to analyze the demand for physical registers, the number of physical registers is dynamically adjusted to meet the physical register requirements of different programs.

[0167] The acquisition, storage, use, and processing of data in this application comply with relevant laws and regulations.

[0168] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0169] This invention is described with reference to flowchart illustrations and / or block diagrams of methods and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0170] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0171] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0172] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A physical register allocation method, characterized in that, The method includes: The instruction dispatch unit determines the required number of physical registers based on the microinstructions; When the number of tokens for idle complete physical registers is greater than or equal to the required number, the number of tokens for idle complete physical registers corresponding to the required number is reduced, triggering the instruction renaming unit to distribute physical registers; When distributing physical registers, the instruction renaming unit selects, according to the required data size and order of the microinstruction, either a complete physical register or a single physical register that meets the required data size from the available complete physical registers and assigns it to the corresponding microinstruction. The bit width of the complete physical register is a preset multiple of the bit width of the single physical register, with single physical registers being preferred. When selecting a single physical register, the instruction distribution unit returns a corresponding number of tokens for available complete physical registers. The registers are renamed and the register mapping is updated according to the physical registers allocated by the microinstructions.

2. The method according to claim 1, characterized in that, The method also includes: For the instruction renaming unit, when sequentially selecting a complete physical register or a single physical register that meets the required data size and allocating it to the corresponding microinstruction, the complete physical register free list and the single physical register free list are updated synchronously.

3. The method according to claim 2, characterized in that, The method also includes: For each free full physical register allocated to a microinstruction, the corresponding free full physical register is removed from the list of free full physical registers. For each free single physical register allocated to a microinstruction, the corresponding free single physical register is removed from the free list of said single physical registers.

4. The method according to claim 1, characterized in that, When distributing physical registers, the instruction renaming unit, based on the required data size and order of the microinstruction, sequentially selects a complete physical register or a single physical register that meets the required data size from among the available complete physical registers and single physical registers, and allocates it to the corresponding microinstruction, including: Determine whether the data size required by the first microinstruction is less than or equal to the bit width of a single physical register; where the microinstructions are in the order of their sequence, from the first microinstruction to the nth microinstruction; n is a positive integer representing the number of microinstructions in the current batch; If the data size required by the first microinstruction is less than or equal to the bit width of a single physical register, then determine whether the available single physical register is empty. If it is not empty, select a single physical register and allocate it to the first microinstruction; if it is empty, select a complete physical register and allocate it to the first microinstruction. If the data size required by the first microinstruction is greater than the bit width of a single physical register, select a complete physical register and allocate it to the first microinstruction; The above process is used to allocate physical registers for the second to nth microinstructions in sequence.

5. The method according to claim 1, characterized in that, The method also includes: After the microinstruction is executed, the scheduling execution unit updates the complete physical register free list and the individual physical register free list.

6. The method according to claim 5, characterized in that, The method also includes: After the microinstruction is executed, the corresponding number of tokens for the free full physical registers are added to the instruction dispatch unit according to the number of full physical registers corresponding to the execution of this microinstruction; for a single physical register corresponding to the execution of this microinstruction, the token is not updated. Add the complete physical register corresponding to the microinstruction executed to the complete physical register free list; The single physical register corresponding to the execution of this microinstruction is added to the free list of the single physical register.

7. The method according to claim 1, characterized in that, The method also includes: The physical register quantity dynamic adjustment sub-unit dynamically adjusts the number of complete physical registers and the number of individual physical registers every counting cycle based on the number of complete physical registers, the number of individual physical registers, the number of idle complete physical registers, and the number of idle individual physical registers, provided that preset conditions are met.

8. The method according to claim 7, characterized in that, The physical register quantity dynamic adjustment subunit dynamically adjusts the number of complete physical registers and the number of individual physical registers every counting cycle based on the number of complete physical registers, the number of individual physical registers, the number of idle complete physical registers, and the number of idle individual physical registers, under preset conditions, including: For each clock tick within the counting period, the number of idle complete physical registers and the number of idle single physical registers are counted respectively; if the idle complete physical register is empty and the idle single physical register is not empty, the increase demand count corresponding to the complete physical register is incremented by 1; if the idle complete physical register is not empty and the idle single physical register is empty, the increase demand count corresponding to the single physical register is incremented by 1; wherein, the counting period includes a preset number of clock ticks. At the end of the counting cycle, if the number of complete physical registers does not reach the preset upper limit of complete physical registers, the number of individual physical registers does not reach the preset lower limit of individual physical registers, and the increase demand count result corresponding to complete physical registers minus the increase demand count result corresponding to individual physical registers is greater than the preset counting threshold, then the number of complete physical registers is increased by the preset number, and the number of individual physical registers is decreased by the preset multiple of the preset number. At the end of the counting cycle, if the number of complete physical registers does not reach the preset lower limit of complete physical registers, the number of individual physical registers does not reach the preset upper limit of individual physical registers, and the increase demand count result corresponding to an individual physical register minus the increase demand count result corresponding to a complete physical register is greater than the preset counting threshold, then the number of individual physical registers is increased by a preset multiple of the preset number of registers, and the number of complete physical registers is decreased by the preset number of registers.

9. The method according to claim 8, characterized in that, The method also includes: At the end of the current counting cycle, clear the count results of the complete physical register and the increase in demand corresponding to the individual physical register.

10. The method according to claim 7, characterized in that, The physical register quantity dynamic adjustment subunit dynamically adjusts the number of complete physical registers and the number of individual physical registers every counting cycle based on the number of complete physical registers, the number of individual physical registers, the number of idle complete physical registers, and the number of idle individual physical registers, under preset conditions, including: For each clock tick within the counting cycle, count the number of complete physical registers and individual physical registers used respectively; At the end of the counting cycle, if the total number of complete physical registers used for all clock ticks is greater than the first usage threshold, the total number of individual physical registers used is less than the second usage threshold, and the number of complete physical registers has not reached the preset upper limit of complete physical registers and the number of individual physical registers has not reached the preset lower limit of individual physical registers, then the number of complete physical registers is increased by the preset number, and the number of individual physical registers is decreased by a preset multiple of the preset number. At the end of the counting cycle, if the total number of individual physical registers used for all clock ticks is greater than the first usage threshold, the total number of complete physical registers used is less than the second usage threshold, and the number of individual physical registers has not reached the preset upper limit for individual physical registers and the number of complete physical registers has not reached the preset lower limit for complete physical registers, then the number of individual physical registers is increased by a preset multiple of the preset number of registers, and the number of complete physical registers is decreased by the preset number of registers.

11. The method according to claim 8 or 10, characterized in that, The method also includes: When increasing or decreasing a preset number of complete physical registers, the instruction dispatch unit increases or decreases the corresponding number of tokens for idle complete physical registers. Synchronously update the complete physical register free list and the individual physical register free list.

12. The method according to claim 8 or 10, characterized in that, After adding a complete physical register or a single physical register, the number of complete physical registers or the number of single physical registers shall not exceed the corresponding preset upper limit of complete physical registers or the preset upper limit of single physical registers; After reducing the number of complete physical registers or individual physical registers, the number of complete physical registers or individual physical registers shall not be less than the corresponding preset lower limit of complete physical registers or preset lower limit of individual physical registers.

13. A physical register allocation device, characterized in that, The device includes: an instruction distribution unit and an instruction renaming unit; The instruction dispatch unit is used to determine the required number of physical registers based on the microinstructions; When the number of tokens for idle complete physical registers is greater than or equal to the required number, the number of tokens for idle complete physical registers corresponding to the required number is reduced, triggering the instruction renaming unit to distribute physical registers; when the number of tokens for idle complete physical registers is less than the required number, no physical register distribution is performed. The instruction renaming unit is used to, when distributing physical registers, select, from available complete physical registers and single physical registers, a complete physical register or a single physical register that meets the required data size and order of the microinstruction, and allocate it to the corresponding microinstruction; wherein, the bit width of the complete physical register is a preset multiple of the bit width of the single physical register, and single physical registers are preferred; when selecting a single physical register, a corresponding number of tokens for available complete physical registers are added; The registers are renamed and the register mapping is updated according to the physical registers allocated by the microinstructions.

14. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method of any one of claims 1 to 12.

16. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method of any one of claims 1 to 12.

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