一种电路、数据处理方法、设备、介质及程序产品
By introducing a heterogeneous computing layer, shared cache layer, control layer, and interface layer into the 3D circuit, and by optimizing the data transmission path using through-silicon via direct connection channels and controllers, the problems of hierarchical communication delay and computing power adaptation in the 3D circuit are solved, achieving efficient data transmission and diversified computing power support.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INSPUR SUZHOU INTELLIGENT TECH CO LTD
- Filing Date
- 2025-11-28
- Publication Date
- 2026-07-17
AI Technical Summary
In three-dimensional circuits, the communication delay between different levels of the computing layer and the cache layer is large, the data transmission efficiency is low, and the deployment of computing nodes is limited, making it unable to adapt to diverse computing power requirements.
The system adopts a three-dimensional heterogeneous computing layer, a shared cache layer, a control layer, and an interface layer. Each layer is connected through a through-silicon via (TSV) direct connection channel. The first and second channel controllers are used to realize the direct connection of physical channels. The data transmission path is optimized by combining the cache consistency of the shared cache layer and the high-efficiency communication module of the interface layer.
It improves data transmission efficiency between different levels, reduces communication latency, meets the needs of high-bandwidth application scenarios, and provides redundancy and fault tolerance capabilities to adapt to diverse computing power requirements.
Smart Images
Figure CN121233494B_ABST
Abstract
Citation Information
Patent Citations
Heterogeneous computing system, cache consistency maintenance method and device, equipment and medium
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