Fpga processor for gf(2) matrix rank and implementation method thereof

Abstract

The application discloses an FPGA processor for GF(2) matrix rank and an implementation method thereof, and belongs to the technical field of integrated circuits and digital signal processing; wherein, a bus interface unit is used for receiving matrix data to be calculated and outputting a finally calculated matrix rank; a control state machine is used for scheduling three-stage pipeline operations of a core calculation unit, and is used for controlling the process of internal iteration calculation; a data storage register array is used for storing matrix data currently being processed; the core calculation unit adopts a three-stage pipeline structure, and sequentially executes three-stage pipeline operations of priority encoding and row exchange, parallel elimination, column displacement and state updating. The FPGA processor for GF(2) matrix rank and the implementation method thereof have the advantages of hardware acceleration solution of matrix rank on a GF(2) field, determined calculation delay, high processing throughput and less occupied hardware resources.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit and digital signal processing technology, specifically relating to an FPGA processor for rank calculation of a GF(2) matrix and its implementation method. Background Technology

[0002] In fields such as cryptography, communication coding (e.g., BCJH codes, RS codes), and randomness detection (e.g., NIST tests), there is a need for high-speed processing of the rank calculation of massive small to medium-sized binary matrices (within 128 orders).

[0003] High-speed computation of the rank of a matrix over a GF(2) field (a binary finite field) is a crucial fundamental operation. For example, solving the LPN problem and performing encoding and decoding of BCH and RS codes require frequent determination of the rank of small to medium-sized matrices. A typical application scenario is the "matrix rank detection" in the NIST standard randomness test suite. Faced with massive amounts of random bit data (Gb level), the computation of the rank of each matrix must be completed in a short time. Otherwise, the influx of subsequent data will consume a large amount of on-chip storage resources as a buffer, greatly increasing cost and power consumption, and becoming a performance bottleneck in the entire testing process.

[0004] It has been proven that Gaussian elimination is the optimal method for solving matrix rank or systems of linear equations on FPGAs. The time complexity of traditional Gaussian elimination is O(n log n). When applied to scenarios involving the processing of a large number of small to medium-sized matrices, the throughput of software implementations often falls short of requirements. In 2006, A. Bogdanov et al. improved upon traditional Gaussian elimination by employing a fine-grained processing element (PE) array architecture, supplemented by cyclic shifting and parallel computation. While this achieved a higher clock frequency, it still suffered from the following technical shortcomings: 1. Uncertain computational latency: Traditional Gaussian computation latency is strongly correlated with the elements in the matrix, and when the data distribution is uneven, the latency is much greater than the average latency. The system design has uncertainties, which makes external scheduling difficult; 2. Low hardware resource efficiency: Its hardware resource consumption is quadratically related to the matrix order (space complexity) This architecture performs well on ASICs, but its resource utilization is low when implemented on FPGAs, which can severely limit the actual size of matrices that can be processed.

[0005] 3. Poor scalability: Changing the matrix order means that the size and interconnection of the PE array need to be redesigned. Summary of the Invention

[0006] To address the technical shortcomings of the existing technologies, such as uncertain computational latency, insufficient software throughput, high hardware resource consumption, and poor scalability, this application proposes an FPGA processor and its implementation method for calculating the rank of a GF(2) matrix. This method achieves deterministic latency and high throughput through a three-stage pipeline architecture, making it particularly suitable for scenarios requiring high-frequency, low-latency, and high-throughput processing of the rank of small and medium-sized binary matrices, such as cryptography, communication, and randomness detection.

[0007] The technical solution is as follows: On the one hand, an FPGA processor for rank calculation of a GF(2) matrix is ​​provided, including: The bus interface unit connects the external system to the data storage register array, and is used to receive the matrix data to be calculated and output the final calculated matrix rank; The control state machine is connected to the core computing unit through registers. It is used to schedule the three-stage pipeline operation of the core computing unit and to control the internal iterative calculation process. The data storage register array connects the bus interface unit and the core computing unit, and is used to store the matrix data currently being processed; The core computing unit connects the data storage register array and registers, and adopts a three-stage pipeline structure to sequentially execute three-stage pipeline operations: priority encoding and row swapping, parallel elimination, and column shifting and state updating.

[0008] Preferably, the core computing unit includes: The priority encoding and row swapping module is connected to the data storage register array. It is used to check the first column element of the currently active row and control the row swapping circuit to swap the first row with the first column set to 1 to the current operation position to become the main row. The parallel elimination module, connected to the data storage register array, is used to perform a bitwise XOR operation on the current main row and all active rows whose first column is 1. The column shift and state update module is connected to the data storage register array and the control state machine. It is used to shift the matrix data after elimination to the left by one column and logically discard the completed column. It also updates the rank counter according to whether the priority encoding and row exchange module and the parallel elimination module have found the pivot.

[0009] Preferably, the priority encoding and line exchange module includes: A priority encoder is used to find the first row whose first column is not zero. Crossbar network, used to perform row switching operations.

[0010] Preferably, the priority encoding and row exchange module adopts a dynamic window MUX tree to implement the pipeline function of this level of priority encoding and row exchange module.

[0011] Preferably, the parallel elimination module includes n- One independent processing unit, each unit containing a bit width of n An XOR gate array and a control AND gate for determining whether to perform an elimination operation.

[0012] Preferably, the control state machine internally includes an iterative counter, the upper limit of which is the order of the matrix. n This is used to control the total number of iterations.

[0013] Preferably, the FPGA processor... n The number of clock cycles required for a rank-finding operation of an rank-1 matrix is ​​fixed at 3. n One clock cycle, of which n Let be the order of the square matrix.

[0014] Preferably, the data storage register array is n × n A bit register array used to store the matrix data currently being processed.

[0015] Preferably, the bus interface unit adopts the AXI4-Lite standard on-chip bus protocol.

[0016] On the other hand, a high-speed FPGA processor implementation method for rank calculation of a GF(2) matrix is ​​provided, comprising the following steps: Matrix data is received through the bus interface unit and stored in the data storage register array; Initialize the rank counter by controlling the state machine; The three-stage pipeline operation is executed iteratively using the core computing unit: First-level pipeline operation: Priority encoding and row swapping, check the first column element of the currently active row, and swap the first row with the first column of 1 to the current operation position through the priority encoder and cross switch network; Second-level pipeline operation: Parallel elimination, which performs a bitwise XOR operation between the current pivot row and all active rows whose first column is 1; The third-level pipeline operation is column shifting and state update, which shifts the matrix data to the left by one column and updates the rank counter based on whether the pivot element is found. When the iteration is complete, the matrix rank is output through the bus interface unit.

[0017] The technical solution includes at least the following technical effects: 1. Deterministic latency: The processor adopts a fixed three-stage pipeline iterative structure, which outputs the result within a clock cycle for any order matrix, eliminating the worst-case latency and greatly facilitating the scheduling of external systems or the design of external buffers. 2. High throughput: Compared to the original algorithm's implementation on FPGA, this technology shortens the critical path, enabling the processor to run at a higher clock frequency, while the deterministic latency ensures stable high throughput. 3. High hardware efficiency: Resource consumption is quadratically related to the order of the matrix. Accelerated solution of 128-order matrices can be achieved on medium-sized FPGAs, with high resource utilization. 4. Simple integration: The processor, as an independent acceleration IP, interacts with the outside world through a standard bus interface, and can be easily integrated into various SoC systems or FPGA projects that require matrix rank calculation; 5. Functional correctness guarantee: The hardware logic is implemented using mathematical principles such as "elementary transformations do not change the rank of a matrix" and operations on the rank of a block matrix, ensuring functional correctness.

[0018] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] Figure 1 A hardware architecture diagram of an FPGA processor for rank finding of a GF(2) matrix is ​​provided as a preferred embodiment; Figure 2 A flowchart of the core computing unit provided in a preferred embodiment; Figure 3 A flowchart illustrating the rank-finding process of a 3rd-order binary matrix is ​​provided as a preferred embodiment. Detailed Implementation

[0021] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0022] Glossary: Gaussian elimination is a method that uses elementary transformations to transform a general matrix into a row echelon form or a simplified form. It is generally used to obtain information about a matrix (such as its rank) and to solve systems of linear equations.

[0023] GF(2) is a binary Galois field, also known as a binary finite field. GF(2) is a mathematical system containing only two elements, 0 and 1. Its addition is equivalent to the XOR operation, and its multiplication is equivalent to the AND operation. Here, GF is an abbreviation for Galois Field; it is a finite field, that is, a mathematical system containing a finite number of elements. In this system, we can perform addition, subtraction, multiplication, and division (except division by 0), and the result of the operation is still within this finite set; (2) indicates that there are only 2 elements in this field.

[0024] Status / Result Register: Used to store various states during processing, including which column needs to be logically discarded, whether the rank counter needs to be updated, etc.

[0025] Register array (D flip-flops): n × n A bit register array is implemented using D flip-flops.

[0026] Dynamic Window (MUX Tree): Implemented using a multi-way selection tree to determine the active row. As can be seen from the rank-finding operation of elementary matrix transformations, the row used for elimination has its information utilized after the first column is eliminated through the third type of elementary row operations. Therefore, in this algorithm, it will be removed from the active row, and the window will move down one row. The next operation only needs to examine the data within the window.

[0027] Priority codec: Used to determine the main row within the window. It searches downwards from the first row in the window and finds the first row whose first element is 1. In implementation, it directly outputs the data of the main row.

[0028] Cross switch (MUX): Implemented using a multiplexer, it is used to swap the principal row found by the priority codec with the first row in the window, making the first row the principal row.

[0029] n XOR: n The bitwise XOR calculation unit is used because there are 10 bits per row. n This is an element, so it is used to perform a bitwise XOR operation on the current first row (i.e., the current first row that has been moved by the cross switch) with other rows whose first element is 1, forming a parallel elimination.

[0030] n Bit barrel shift: n A bucket shift register for bits, used to move the first column after an XOR operation to the last column, and the remaining columns (2, 3, ...)... n Each column moves forward one column, and the final data is sent back. n × n The register array completed the data update on the matrix elements.

[0031] like Figure 1 As shown, an FPGA processor mainly includes the following components: The bus interface unit is responsible for communicating with external systems (such as CPUs or SoCs) and connecting internal data paths. It receives matrix data to be calculated and outputs the final calculated matrix rank. Matrix data is received through the bus interface unit and stored in the data storage register array. In a preferred embodiment, the bus interface unit adopts the AMBA AXI4-Lite standard on-chip bus protocol.

[0032] Finite-State Machine (FSM): The global controller, connected to the core computing unit, is used to schedule the entire computing process (such as the three-level pipeline operation of the core computing unit) and manage the iterative process. The rank counter is initialized through the control state machine.

[0033] The control state machine contains an iterative counter, the upper limit of which is the order of the matrix. n This is used to control the total number of iterations.

[0034] The data storage register array, connecting the bus interface unit and the core computing unit, is used to store the matrix data currently being processed. In this embodiment, the data storage register array adopts... n × n A bit register array is implemented using D flip-flops.

[0035] Core computing unit: Connects the data storage register array and registers, adopts a three-stage pipeline structure, and sequentially performs priority encoding and row swapping (first type of elementary transformation), parallel elimination (third type of elementary transformation), column left shift (first type of elementary transformation), and state update operations.

[0036] The core computing units include: a priority encoding and row swapping module, a parallel elimination module, and a column shifting and state update module.

[0037] The priority encoding and row swapping module, connected to the data storage register array, is used to check the first column element of the currently active row and control the row swapping circuit to swap the first row with a first column of 1 to the current operation position to become the pivot row. The priority encoder and row swapping module includes: a priority encoder for finding the first row with a non-zero first column; and a crossbar switch network for performing the row swapping operation. In a preferred embodiment, the priority encoder and row swapping module uses a dynamic window MUX tree to implement the pipelined functionality of this stage.

[0038] A parallel elimination module, connected to the data storage register array, is used to perform a bitwise XOR operation on the current pivot row and all active rows whose first column is 1. The parallel elimination module includes... n- One independent processing unit, each unit containing a bit width of n The array consists of an XOR gate array and a control AND gate for determining whether to perform an elimination operation. n Let be the order of the square matrix.

[0039] The column shift and state update module is connected to the data storage register array and the control state machine. It is used to shift the matrix data after elimination to the left by one column (the completed column is logically discarded) and update the rank counter according to whether the priority encoding and row exchange module and the parallel elimination module have found the pivot.

[0040] In one embodiment, the FPGA processor... n The number of clock cycles required for a rank-finding operation of an rank-1 matrix is ​​fixed at 3. n One clock cycle.

[0041] The core computing unit employs a three-stage pipeline architecture. This architecture dynamically defines the active row window that needs to be processed through a rank counter (rank). In each iteration, the row from the physical address rank row in the register array is defined as the active row and participates in the lookup and computation of this iteration. As the rank value increases, this window gradually shrinks from the top of the matrix, and the priority encoder, crossbar switch, and parallel elimination logic operate only within this window.

[0042] like Figure 2 As shown, the core computing unit's workflow involves performing the following operations in sequence: The first-level pipelined operation, priority encoding and row swapping, examines the first column element of all currently active rows (defined by a rank counter). A priority encoder locates the first row containing a 1. This row is swapped with the current row (rank + 1) using a crossbar switch network. If the first column element of all active rows is 0, the swap operation is skipped, and the process proceeds to the next level.

[0043] The second-level pipelined operation, parallel elimination: If the first column of the current rank + 1 row is 1 (i.e., a pivot exists), then that row is treated as the pivot row. In parallel, for all other active rows (rank + 2 to the next row), if their first column is 1, then the data in that row is XORed with the data in the pivot row, and the result is written back to that row.

[0044] The third-level pipelined operation, column left shift and state update, shifts all data in the register array to the left by one column, filling the rightmost empty column with 0s. This operation is equivalent to logically discarding the leftmost column that has already been processed. Simultaneously, if elimination (i.e., finding the pivot) is successfully performed in the second-level pipeline, the control state machine increments the rank counter by 1.

[0045] The control state machine schedules the above three-stage pipeline to execute cyclically until the rank counter equals the order of the matrix. n Or determine that the rank of the matrix is ​​less than n (That is, if the principal element cannot be found in a certain iteration and all columns have been processed), the final value rank is output and sent out through the bus interface unit.

[0046] based on Figure 1 The processor architecture diagram and the FPGA processor implementation method for calculating the rank of a GF(2) matrix in this application include the following steps: The matrix data is received through the bus interface unit and stored in the data storage register array. When the iteration is complete, the matrix rank is output through the bus interface unit. Initialize the rank counter by controlling the state machine; Specifically, via the AXI4-Lite bus interface n × n The binary matrix data is loaded into a register array consisting of D flip-flops, while the control state machine initializes the rank counter to 0 and sets the dynamic window MUX tree to the full matrix range; then the core iterative calculation phase begins.

[0047] The three-stage pipeline operation is executed iteratively using the core computing unit: First-level pipeline operation: Priority encoding and row swapping, check the first column element of the currently active row, and swap the first row with the first column of 1 to the current operation position through the priority encoder and cross switch network; Second-level pipeline operation: Parallel elimination, which performs a bitwise XOR operation between the current pivot row and all active rows whose first column is 1; The third-level pipeline operation is column shifting and state updating. The matrix data is shifted to the left by one column, and the rank counter is updated based on whether the pivot element is found.

[0048] Specifically, this stage is strictly implemented according to a three-level assembly line. n The loop iterates through, with each iteration consuming a fixed 3 clock cycles. n Let be the order of the square matrix.

[0049] In the first cycle of each iteration, the priority encoding and row swapping module begins to work: the dynamic window (MUX tree) defines the range of active rows based on the current rank counter value, the priority encoder scans the first column element of these rows to find the first "1", decodes it through the decoder, and swaps the corresponding row to the top of the window to become the master row through the cross-switching MUX network.

[0050] In the second cycle, the parallel elimination module starts operating: n -1 processing unit simultaneously checks the state of the first column of its assigned row. When the first column of a row is 1, its corresponding control AND gate is enabled. n A bitwise XOR gate array is used to perform a bitwise XOR operation between the row and the pivot row, achieving parallel elimination. n XOR arrays can complete multi-row parallel elimination in a single cycle.

[0051] The third cycle has been completed and is nearing completion. n Barrel-shaped shifter ( n The bit barrel shift shifts the entire register array data one column to the left, filling the rightmost column with zeros, which is equivalent to discarding the processed columns. The control state machine updates the rank counter based on whether the pivot was successfully found in the previous two cycles. If the pivot was found, the rank counter is incremented by 1, and the dynamic window shrinks accordingly.

[0052] go through n After one complete iteration, the processor enters the termination output stage. At this point, the value of the rank counter is the final rank result of the matrix, which is returned to the external system through the bus interface. The entire processing flow has strictly deterministic latency characteristics, consuming exactly 3 units of latency regardless of the characteristics of the input matrix. n This well-organized pipeline design, operating within a few clock cycles, ensures high throughput and stable performance.

[0053] It should be noted that the text mentions n Let be the order of the square matrix. n It is a positive integer, generally starting from n If the rank is ≥2, then the rank needs to be calculated.

[0054] This application aims to address the problems of uncertain computational latency, insufficient software throughput, high hardware resource consumption, and poor scalability in existing GF(2) domain matrix rank-finding techniques. A three-stage pipelined hardware architecture based on Gaussian elimination is adopted, including priority encoding and row swapping, parallel elimination, column left shift, and state update operations. This architecture ensures efficient computation by scheduling iterative calculations through a control state machine. n The order matrix is ​​fixed at 3 nThe rank result is output within one clock cycle, achieving deterministic latency, high throughput, and low resource consumption. The FPGA processor is integrated as a standalone IP through the AXI4-Lite standard bus interface, facilitating deployment in SoC systems. It is particularly suitable for scenarios involving massive binary matrix processing, such as randomness detection and error correction coding.

[0055] The core of the FPGA processor in this application is to implement, pipeline, and deterministically optimize the Gaussian elimination method in hardware; through a fixed three-stage pipeline structure, the rank calculation of the binary matrix is ​​completed within a defined clock cycle.

[0056] To illustrate the working process of this FPGA processor in more detail, the following explanation uses the process of finding the rank of a 3rd-order binary matrix as an example.

[0057] like Figure 3 As shown, in a specific embodiment: let the matrix to be calculated be: Following the steps, set rank = 0. When clk = 1, first check the first column of the active row; the first column element is... Since the first element is already non-zero, the first row is the pivot row, and no row swap is needed at this point.

[0058] Upon reaching clk = 2, we notice that the first element of the second and third rows is 1, so we perform XOR elimination to obtain the result.

[0059] When we reach clk = 3, we shift all columns of the entire matrix to the left, discard the first column, and leave a blank column on the right. We fill this blank column with the zero vector (logically, we discard it directly) and increment the rank value by 1.

[0060] Upon reaching clk = 4, examine the active rows (rows 2-3), meaning we only need to consider a 2×3 matrix. Its first column element is , which requires row swapping. Therefore, within the same clock cycle, the second and third rows are swapped.

[0061] When we reach clk = 5, since the first column except for the pivot is all 0, no XOR operation is needed.

[0062] When clk = 6 is reached, the matrix is ​​shifted to the left and filled with 0s, and the value of rank is incremented by 1.

[0063] Upon reaching clk = 7, we only need to examine the active row. Its first row and first column are already 1, so we cannot perform any more row swaps and therefore do nothing.

[0064] Upon reaching clk = 8, no further action is taken as there are no lines below.

[0065] When clk = 9, shift left and fill with 0s. The resulting matrix is ​​a zero matrix. Then increment rank by 1 to get 3.

[0066] After three stages and a total of nine clock cycles, the processor outputs the rank of the matrix, completing the calculation. This example demonstrates that even in the worst-case scenario (where row swapping is required), the number of cycles is strictly predictable. This can be verified using general binary elementary transformations: The result is clearly correct.

[0067] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0068] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0069] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0070] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0071] The structures, proportions, and sizes illustrated in the accompanying drawings are solely for illustrative purposes and to aid those skilled in the art in understanding and reading the content disclosed herein. They are not intended to limit the scope of this application and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, provided they do not affect the effectiveness or purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms "left," "right," "first," and "second," etc., used in this specification are merely for clarity and not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0072] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

Claims

1. An FPGA processor for rank calculation of a GF(2) matrix, characterized in that, include: The bus interface unit connects the external system to the data storage register array, and is used to receive the matrix data to be calculated and output the final calculated matrix rank; A status / result register is used to store the processing status, including whether the rank counter needs to be updated. The control state machine is connected to the core computing unit through the state / result register. It is used to schedule the three-level pipeline operation of the core computing unit and to control the internal iterative calculation process. The data storage register array connects the bus interface unit and the core computing unit, and is used to store the matrix data currently being processed; The core computing unit, connected to the data storage register array and the status / result register, adopts a three-stage pipeline structure, sequentially executing three-stage pipeline operations: priority encoding and row swapping, parallel elimination, and column shifting and status updating. The FPGA processor includes a rank counter, rank, whose count value represents the number of identified principal components. The control state machine initializes the rank counter rank to 0 and increments it by 1 when a principal component is found in the current iteration. The three-stage pipeline structure of the core computing unit dynamically defines the active row window to be processed based on the current count value of the rank counter rank. When the rows of the matrix are numbered from row 1 to row n, the active row window consists of rows rank+1 to n, and gradually shrinks from the top of the matrix as the count value of the rank counter rank increases.

2. The FPGA processor for rank finding of a GF(2) matrix according to claim 1, characterized in that, The core computing unit includes: The priority encoding and row swapping module is connected to the data storage register array. It is used to check the first column element of the current active row and control the row swapping circuit to swap the first row with the first column set to 1 to the first row of the current active row to become the main row. The parallel elimination module, connected to the data storage register array, is used to perform a bitwise XOR operation with the current principal row when the priority encoding and row exchange module finds the principal row, and performs bitwise XOR operation with the other active rows whose first column is 1, except for the principal row itself. The column shift and state update module is connected to the data storage register array and the control state machine. It is used to shift the matrix data after elimination to the left by one column and update the rank counter.

3. The FPGA processor for rank finding of a GF(2) matrix according to claim 2, characterized in that, The priority encoding and line exchange module includes: A priority encoder is used to find the first row whose first column is not zero. Crossbar network, used to perform row switching operations.

4. The FPGA processor for rank finding of a GF(2) matrix according to claim 3, characterized in that, The priority encoding and row swapping module uses a dynamic window MUX tree to limit the range of active rows participating in this principal element search based on the current count value of the rank counter, so that the priority encoder only performs priority judgment on the first column element of each row within the range of active rows.

5. The FPGA processor for rank finding of a GF(2) matrix according to claim 2, characterized in that, The parallel elimination module includes n - One independent processing unit, each unit containing a bit-width of n The array consists of an XOR gate array and a control AND gate for determining whether to perform an elimination operation. n Let be the order of the square matrix.

6. The FPGA processor for rank finding of a GF(2) matrix according to any one of claims 1 to 5, characterized in that, The control state machine contains an iterative counter, the upper limit of which is the order of the matrix. n This is used to control the total number of iterations.

7. The FPGA processor for rank finding of a GF(2) matrix according to any one of claims 1 to 5, characterized in that, The FPGA processor n The number of clock cycles required for a rank-finding operation of an rank-1 matrix is ​​fixed at 3. n One clock cycle.

8. The FPGA processor for rank finding of a GF(2) matrix according to any one of claims 1 to 5, characterized in that, The data storage register array is n × n A bit register array used to store the matrix data currently being processed.

9. The FPGA processor for rank finding of a GF(2) matrix according to any one of claims 1 to 5, characterized in that, The bus interface unit adopts the AXI4-Lite standard on-chip bus protocol.

10. An FPGA processor implementation method for rank finding of a GF(2) matrix, applied to the FPGA processor for rank finding of a GF(2) matrix as described in any one of claims 1-9, characterized in that, Includes the following steps: Matrix data is received through the bus interface unit and stored in the data storage register array; Initialize the rank counter by controlling the state machine; The three-stage pipeline operation is executed iteratively using the core computing unit: First-level pipeline operation: Priority encoding and row swapping, check the first column element of the current active row, and swap the first row with the first column set to 1 to the first row of the current active row through the priority encoder and cross-switch network to become the main row; Second-level pipeline operation: Parallel elimination. If the pivot is found in the first-level pipeline operation, then perform a bitwise XOR operation between the active rows other than the pivot row itself and the current pivot row, where the first column is 1. The third-level pipeline operation is column shifting and state update, which shifts the matrix data to the left by one column and updates the rank counter based on whether the pivot element is found. When the iteration is complete, the matrix rank is output through the bus interface unit.

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