An accelerator register bank management and mapping off-chip memory system and apparatus

Abstract

The application provides an accelerator register group management and mapping off-chip storage system and device, and relates to the chip design technical field.The application provides an accelerator register group management and mapping off-chip storage system, which comprises a bus, a data storage medium and a parallel accelerator device, wherein the data storage medium and the parallel accelerator device are connected through the bus; the parallel accelerator device comprises a register group module, N function processing modules and N processing state modules; the register group module comprises a version register, a merging operation register and N register groups; each register group comprises configuration related registers, state related registers, a reset register, an open function processing register and an end function processing register; the version register is used for recording version information of the register group; the merging operation register is used for marking the register group to be subjected to the merging operation; and the reset register is used for resetting the state of each register in the register group to which the reset register belongs.

Description

Technical Field

[0001] This application relates to the field of chip design technology, and in particular to an accelerator register group management and mapping off-chip memory system and device. Background Technology

[0002] With the rapid development of integrated circuit technology, System-on-Chip (SoC) has been widely used in many fields, especially in smartphones, embedded devices, the Internet of Things (IoT), and high-performance computing. SoC integrates multiple functional modules onto a single chip, achieving efficient computing and control while significantly reducing power consumption and cost. However, with the increasing demands of applications, the limitations of traditional single-core processing in terms of computing power are becoming increasingly apparent. Especially when facing large-scale data processing and high-concurrency computing tasks, single-core processors cannot effectively meet the requirements of high performance and low latency. Summary of the Invention

[0003] This application aims to at least partially address one of the technical problems in the related art.

[0004] Therefore, one objective of this application is to propose an accelerator register group management and mapping off-chip memory system, including a bus, a data storage medium, and a parallel accelerator device, wherein: the data storage medium and the parallel accelerator device are connected via the bus; the parallel accelerator device includes a register group module, N function processing modules, and N processing status modules; the register group module includes a version register, a merge operation register, and N register groups, each register group including a configuration-related register, a status-related register, a reset register, an enable function processing register, and an end function processing register; the version register is used to record the version information of the register group; the merge operation register is used to mark the register group to be merged; the reset register is used to reset the status of each register in its respective register group.

[0005] This application employs a register group management mechanism, which can improve the configuration speed and functional processing speed of parallel accelerator chips.

[0006] The data storage address and length of this application are flexibly configurable, and optimal functional processing can be performed for data of different lengths.

[0007] This application can use two mechanisms for synchronization: polling to synchronize the status or interruption notification to handle the completion status.

[0008] The second objective of this application is to propose a parallel accelerator device, comprising a register group module, N functional processing modules and N processing state modules, for use in the aforementioned accelerator register group management and mapping off-chip memory system.

[0009] The third objective of this application is to propose a task processing method.

[0010] The fourth objective of this application is to propose an alternative method for task processing.

[0011] The fifth objective of this application is to propose a host computer.

[0012] The sixth objective of this application is to propose an alternative host computer.

[0013] The seventh objective of this application is to provide an electronic device.

[0014] The eighth objective of this application is to provide a non-transitory computer-readable storage medium.

[0015] The ninth objective of this application is to provide a computer program product.

[0016] To achieve the above objectives, the first aspect of this application proposes an accelerator register group management and mapping off-chip memory system, including a bus, a data storage medium, and a parallel accelerator device, wherein: the data storage medium and the parallel accelerator device are connected via the bus; the parallel accelerator device includes a register group module, N function processing modules, and N processing status modules; the register group module includes a version register, a merge operation register, and N register groups, each register group including a configuration-related register, a status-related register, a reset register, an enable function processing register, and an end function processing register; the version register is used to record the version information of the register group; the merge operation register is used to mark the register group to be merged; the reset register is used to reset the status of each register in its respective register group.

[0017] To achieve the above objectives, a second aspect of this application provides a parallel accelerator device, including a register group module, N functional processing modules and N processing state modules, which is applied to the above-mentioned accelerator register group management and mapping off-chip memory system.

[0018] To achieve the above objectives, a third aspect of this application proposes a task processing method applied to a host computer, comprising: determining a target register group and a target function processing module corresponding to the target register group from an accelerator register group management and mapping off-chip storage system, and issuing an initialization instruction corresponding to the target task to be executed to the target register group; after detecting that the target register group has completed the parameter configuration of its configuration-related registers according to the initialization instruction, issuing a task start instruction to the enable function processing register in the target register group; controlling the target function processing module to execute the target task according to the parameters configured in the configuration-related registers, and obtaining the processing status of the target task based on the status-related registers contained in the target register group; and after determining that the target task has been completed based on the processing status, obtaining the result data corresponding to the target task.

[0019] To achieve the above objectives, a fourth aspect of this application proposes a task processing method applied to a host computer, comprising: determining a first-level subtask and a second-level merging task in a target task to be executed; determining multiple target register groups corresponding to the target task and the target function processing modules corresponding to the multiple target register groups from the accelerator register group management and mapping off-chip storage system; generating a merging operation setting instruction based on the multiple target register groups and sending it to the merging operation register in the accelerator register group management and mapping off-chip storage system to configure the merging operation register; generating an initialization instruction corresponding to the target task and sending it to the target register group; and detecting the root of the target register group. After configuring the parameters of their respective configuration-related registers according to the initialization instructions, a task start instruction is issued to the enable function processing register in the target register group; the target function processing module is controlled to execute its corresponding first-level subtask according to the parameters configured in its corresponding configuration-related registers, and the merging function processing module for the second-level merging task is determined from the target function processing modules. The merging function processing module is controlled to execute the second-level merging task based on the parameters configured in the merging operation register, and the processing status of the target task is obtained based on the status-related registers contained in the target register group; after the target task is completed based on the processing status, the result data corresponding to the target task is obtained.

[0020] To achieve the above objectives, a fifth aspect of this application proposes a host computer, comprising: an initialization module, configured to determine a target register group and a target function processing module corresponding to the target register group from the accelerator register group management and mapping off-chip memory system, and to issue an initialization instruction corresponding to the target task to be executed to the target register group; a calculation start module, configured to issue a task start instruction to the start function processing register in the target register group after detecting that the target register group has completed the parameter configuration of its configuration-related registers according to the initialization instruction, and control the target function processing module to execute the target task according to the parameters configured in the configuration-related registers; a status detection module, configured to obtain the processing status of the target task based on the status-related registers contained in the target register group; and a calculation end module, configured to obtain the result data corresponding to the target task after determining that the target task has been executed based on the processing status.

[0021] To achieve the above objectives, a sixth aspect of this application proposes a host computer, comprising: a merge operation register setting module, used to determine the first-level subtask and the second-level merge task in the target task to be executed, and to determine multiple target register groups corresponding to the target task from the accelerator register group management and mapping off-chip storage system, and to determine the target function processing modules corresponding to the multiple target register groups respectively, and to generate merge operation setting instructions based on the multiple target register groups and send them to the merge operation register in the accelerator register group management and mapping off-chip storage system to configure the merge operation register; an initialization module, used to generate initialization instructions corresponding to the target task and send them to the target register groups; and a calculation start module, used to detect the target registers and set the initialization instructions to be sent to the target register groups. After configuring the parameters of their respective configuration-related registers according to the initialization instructions, each group sends a task start instruction to the enable function processing register in the target register group. This instruction controls the target function processing module to execute its corresponding first-level subtask according to the parameters configured in its corresponding configuration-related register. The group also determines the merging function processing module from the target function processing modules to perform the second-level merging task and controls it to execute the second-level merging task based on the parameters configured in the merging operation register. A status detection module is used to obtain the processing status of the target task based on the status-related registers in the target register group. Finally, a calculation completion module is used to obtain the result data corresponding to the target task after determining that the target task has finished executing based on the processing status.

[0022] To achieve the above objectives, a seventh aspect of this application provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to implement the task processing method as described in the third or fourth aspect of this application.

[0023] To achieve the above objectives, an eighth aspect of this application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to implement the task processing method as described in the third or fourth aspect of this application.

[0024] To achieve the above objectives, a ninth aspect of this application provides a computer program product, including a computer program that, when executed by a processor, implements the task processing method as described in the third or fourth aspect of this application. Attached Figure Description

[0025] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0026] Figure 1 This is a schematic diagram of a parallel accelerator device shown in this application.

[0027] Figure 2 This is a detailed schematic diagram of a register group shown in one embodiment of this application.

[0028] Figure 3 This is a schematic diagram of an accelerator register group management and mapping off-chip memory system shown in this application.

[0029] Figure 4 This is a schematic diagram illustrating an exemplary implementation of a task processing method according to one embodiment of this application.

[0030] Figure 5 This is a framework diagram illustrating a task processing method according to one embodiment of this application.

[0031] Figure 6 This is a schematic diagram illustrating an exemplary implementation of another task processing method according to one embodiment of this application.

[0032] Figure 7 This is a framework diagram illustrating another task processing method according to one embodiment of this application.

[0033] Figure 8 This is a schematic diagram of a host computer shown in one embodiment of this application.

[0034] Figure 9 This is a schematic diagram of another host computer shown in one embodiment of this application.

[0035] Figure 10 This is a schematic diagram of an electronic device according to one embodiment of this application. Detailed Implementation

[0036] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0037] Figure 1 This is a schematic diagram of a parallel accelerator device shown in this application, such as... Figure 1 As shown, the parallel accelerator device includes a register group module, N functional processing modules, and N processing status modules.

[0038] The register group module includes a version register, a merge operation register, and N register groups. Each register group has the same function and contains multiple registers. The version register and the merge operation register are shared registers among the N register groups.

[0039] in, Figure 1 The diagram uses N as an example of 8, meaning that in addition to the version register and merge operation register, the parallel accelerator device also includes 8 functional processing modules, 8 processing status modules, and 8 register groups. The parallel accelerator device refers to a device where each functional processing module can simultaneously perform its own task acceleration processing based on its corresponding register group.

[0040] Each register group corresponds one-to-one with a functional processing module. For example, register group 1 corresponds to functional processing module 1, register group 2 corresponds to functional processing module 2, and so on. The register group provides support for its corresponding functional processing module.

[0041] In this module, there is a one-to-one correspondence between the functional processing module and the processing status module. For example, functional processing module 1 corresponds to processing status module 1, functional processing module 2 corresponds to processing status module 2, and so on. The processing status module is used to indicate the processing status of its corresponding functional processing module.

[0042] The version register is used to record the version information of each register group.

[0043] The merge operation register is used to mark the register groups to be merged. For example, if function processing modules 1 to 8 perform their respective calculations based on their corresponding register groups 1 to 8, and the values ​​obtained from their calculations need to be subjected to the same continuous operations, such as consecutive addition or subtraction, then "8" is written into the merge operation register (in this application, the counting can start from register group 1 by default; that is, if "8" is written into the merge operation register, it means that the register groups to be merged are marked as register groups 1 to 8). This indicates that the corresponding output data needs to be extracted from the data storage medium based on the output data related parameters stored in the eight register groups 1 to 8 for subsequent continuous operations, such as consecutive addition or subtraction.

[0044] To further elaborate on the register set within the parallel accelerator device proposed in this application Figure 2 This is a detailed schematic diagram of a register group shown in this application, such as... Figure 2 As shown, this register group includes 12 registers, which can be divided into the following categories: configuration-related registers, status-related registers, reset registers, enable function processing registers, and end function processing registers.

[0045] The configuration-related registers include the input data start address register, the input data length register, the output data start address register, the output data length register, the function processing mode selection register, the data format selection register, and the function processing timeout configuration register. Each configuration-related register will be described in detail below.

[0046] The input data start address register is used to configure the starting address for storing the input data.

[0047] The input data length register is used to configure the length of the input data. During the calculation by the function processing module, the input data to be calculated can be obtained from the data storage medium according to the configuration parameters of both the input data start address register and the input data length register included in the register group corresponding to the function processing module.

[0048] The output data start address register is used to configure the starting address for storing the output data.

[0049] The output data length register is used to configure the length of the output data. After the function processing module completes its calculation, the output data obtained after the calculation is completed can be stored in the data storage medium according to the configuration parameters of the output data start address register and the output data length register included in the register group corresponding to the function processing module.

[0050] The function processing mode selection register is used to select the function processing mode. The available function processing modes include single-ended mode and normal mode.

[0051] The data format selection register is used to select the data format. Available data processing formats include flat and compressed formats.

[0052] The function processing timeout configuration register is used to configure timeout-related parameters, that is, to configure the allowed timeout duration for task processing. This register is optional; if not configured, it will be processed according to its default parameters.

[0053] Both input and output data are stored in the data storage medium.

[0054] Among them, the status-related registers include the real-time status register for function processing and the interrupt notification register. Each type of status-related register will be described in detail below.

[0055] The real-time status register for function processing records the processing status of the function processing module. For example, if the return value of the real-time status register for function processing is 0, it means that function processing has not started, has ended normally, or the register status has been reset; if the return value of the real-time status register for function processing is 1, it means that there is a hardware failure; if the return value of the real-time status register for function processing is 2, it means that function processing is in progress; if the return value of the real-time status register for function processing is 3, it means that function processing has timed out.

[0056] The interrupt notification register is used to select the mode in which the host computer obtains the processing status of the function processing module. This mode includes polling mode and interrupt notification mode. For example, if the interrupt notification register is written with "0", it indicates that polling mode is selected, and the host computer needs to continuously poll the status return value of the function processing real-time status register to obtain the processing status of the function processing module. If the interrupt notification register is written with "1", it indicates that interrupt notification mode is selected. If a task is interrupted or completed while the function processing module is processing a task, the interrupt notification register will proactively send the corresponding status information to the host computer, without requiring the host computer to poll.

[0057] The reset register is used to reset the state of each register in its register group. For example, writing "1" to the reset register will reset the state of each register in its register group.

[0058] The Enable Function Processing Register indicates whether function processing is enabled. For example, writing "1" to the Enable Function Processing Register means that this function processing is enabled.

[0059] The End Function Processing Register indicates the end of function processing. For example, writing "1" to the End Function Processing Register means ending the current function processing.

[0060] This application adopts a register group management mechanism, which can improve the configuration speed and function processing speed of parallel accelerator chips.

[0061] The data storage address and length of this application are flexibly configurable, and optimal functional processing can be performed for data of different lengths.

[0062] This application can use two mechanisms for synchronization: polling to synchronize the status or interruption notification to handle the completion status.

[0063] The above describes each register. Table 1 below provides an explanation of each register for reference.

[0064] Table 1 Register Description Table

[0065]

[0066]

[0067]

[0068] Figure 3 This application illustrates a schematic diagram of an accelerator register group management and mapping off-chip memory system, as shown below. Figure 3 As shown, the accelerator register group manages and maps the off-chip memory system, including a bus, data storage media, and parallel accelerator devices.

[0069] The data storage medium and the parallel accelerator device are connected via a bus.

[0070] The bus is used for data transmission. For example, it is used to retrieve the input data required by the parallel accelerator device from the data storage medium, or to store the output data calculated by the parallel accelerator device in the data storage medium.

[0071] The data storage medium is used to store relevant data during task processing, including at least input data for calculation and output data after task processing is completed.

[0072] Figure 4 This is a schematic diagram illustrating an exemplary implementation of a task processing method shown in this application, such as... Figure 4 As shown, this task processing method is applied to the host computer and specifically includes the following steps:

[0073] S401 determines the target register group and the target function processing module corresponding to the target register group from the accelerator register group management and mapping off-chip memory system, and issues the initialization instruction corresponding to the target task to be executed to the target register group.

[0074] Figure 5 This is a framework diagram of a task processing method shown in this application. The following will combine... Figure 5 right Figure 4 The implementation methods of the embodiments will be described in detail.

[0075] The accelerator register group management and mapping off-chip memory system adopts the accelerator register group management and mapping off-chip memory system described above.

[0076] First, the target task to be executed is determined. Then, one idle register group is selected from the N register groups of the accelerator register group management and mapping off-chip memory system as the target register group. Next, the corresponding functional processing module on the accelerator register group management and mapping off-chip memory system is selected as the target functional processing module. For example, register group 1 can be selected as the target register group, and correspondingly, functional processing module 1 can be selected as the target functional processing module.

[0077] The initialization module on the host computer generates the initialization instructions corresponding to the target task and sends these instructions to the target register group for configuring relevant parameters. It is easy to understand that, referring to the above description of accelerator register group management and mapping of off-chip memory systems, the target register group belongs to the register group module in the parallel accelerator device.

[0078] S402, after detecting that the target register group has completed the parameter configuration of its configuration-related registers according to the initialization instruction, issues a task start instruction to the enable function processing register in the target register group.

[0079] Among them, such as Figure 5 As shown, the configuration-related registers included in the target register group include at least the input data start address register, input data length register, output data start address register, output data length register, function processing mode selection register, and data format selection register. In addition, the function processing timeout configuration register is an optional configurable register. If the initialization instruction does not include configuration parameters for the function processing timeout configuration register, the default timeout parameters will be used.

[0080] The detailed description of the configuration of the relevant registers has already been provided in the section on accelerator register group management and mapping of off-chip memory systems, and will not be repeated here.

[0081] like Figure 5 As shown, after detecting that the target register group has completed the parameter configuration of its configuration-related registers according to the initialization instruction, the calculation activation module based on the host computer issues a task start instruction to the activation function processing register in the target register group. Issuing the task start instruction to the activation function processing register in the target register group can also be understood as writing a "1" to the value of the activation function processing register in the target register group to indicate that the current function processing has been started.

[0082] In some implementations, if the host computer selects the interrupt notification mode when obtaining the task processing status of the target function processing module, the initialization instruction also needs to carry parameters to configure the interrupt notification register, that is, write "1" to the interrupt notification register to indicate that the interrupt notification mode is selected to obtain the task processing status of the target function processing module.

[0083] S403, the target function processing module executes the target task according to the parameters configured in the configuration-related registers, and obtains the processing status of the target task based on the status-related registers contained in the target register group.

[0084] After the task start instruction is issued to the enable function processing register in the target register group, the target function processing module executes the target task according to the parameters configured in the relevant registers.

[0085] The target function processing module obtains input data from the data storage medium of the accelerator register group management and mapping off-chip storage system according to the parameters configured in the input data start address register and input data length register. It then processes the task by combining the function processing mode configured in the function processing mode selection register, the data format configured in the data format selection register, and the timeout parameters configured in the function processing timeout configuration register. After task processing is completed, the module stores the final output data in the corresponding location in the data storage medium of the accelerator register group management and mapping off-chip storage system according to the parameters configured in the output data start address register and output data length register.

[0086] Among them, such as Figure 5 As shown, during the task processing of the target function processing module, the target processing status module corresponding to the target function processing module, located in the accelerator register group management and mapping off-chip storage system, obtains the task processing status in real time. The status-related registers in the target register group can know the task processing status based on the target processing status module. Thus, the status detection module of the host computer can obtain the task processing status based on the status-related registers in the target register group.

[0087] The target register group includes status-related registers such as a real-time status register for function processing and an interrupt notification register. The processing status of the target task is obtained based on the status-related registers contained in the target register group, including: determining whether the host computer has started the interrupt notification mechanism; if the host computer has started the interrupt notification mechanism, receiving the task interrupt notification sent by the interrupt notification register in the target register group when the execution of the target task is interrupted, or receiving the task completion notification sent by the interrupt notification register in the target register group when the execution of the target task is completed; if the host computer has not started the interrupt notification mechanism, during the execution of the target task, the processing status of the target task is obtained by polling the real-time status register for function processing in the target register group.

[0088] Taking register group 1 as the target register group and function processing module 1 as the target function processing module as an example, after register group 1 completes the parameter configuration of its configuration-related registers, the host computer writes "1" to the value of the enable function processing register in register group 1 to indicate that the current function processing is enabled. Then, function processing module 1 executes the target task and stores the output data according to the parameters configured in the configuration-related registers in register group 1. During the task processing of function processing module 1, its corresponding processing status module 1 obtains the task processing status in real time. The status-related registers in register group 1 can know the task processing status based on the processing status module 1. Therefore, the status detection module of the host computer can obtain the task processing status based on the status-related registers in register group 1.

[0089] S404: After determining that the target task has been completed based on the processing status, obtain the result data corresponding to the target task.

[0090] Among them, such as Figure 5 As shown, when the end function processing register in the target register group learns from the real-time status register of the function processing that the task processing has ended, the end function processing register will write "1" to indicate that the current function processing has ended, and notify the host computer's calculation end module that the task processing has ended.

[0091] As described above, after task processing is completed, the target function processing module stores the final output data in the corresponding location of the data storage medium of the accelerator register group management and mapping off-chip storage system according to the parameters configured in the output data start address register and the output data length register. In this application, the host computer can obtain the output data configuration parameters carried by the initialization instruction. The output data configuration parameters include the configuration parameters corresponding to the output data start address register and the output data length register in the configuration-related registers, respectively; then, based on the output data configuration parameters, it obtains the result data corresponding to the target task from the data storage medium of the accelerator register group management and mapping off-chip storage system.

[0092] Continuing with the example of selecting register group 1 as the target register group and function processing module 1 as the target function processing module, function processing module 1 stores the final output data in the corresponding location of the data storage medium of the accelerator register group management and mapping off-chip storage system according to the parameters configured in the output data start address register and output data length register in register group 1. The host computer then obtains the result data corresponding to the target task from the data storage medium of the accelerator register group management and mapping off-chip storage system according to the parameters configured in the output data start address register and output data length register in register group 1.

[0093] This application embodiment enables parallel processing of multiple tasks by allocating task processing to idle register groups and function processing modules, thereby improving the overall task processing efficiency. It provides two task status monitoring methods: interrupt notification and polling mode, making task status acquisition more flexible and efficient. In particular, in interrupt notification mode, the host computer can promptly obtain the interruption or completion status of the task, thereby effectively monitoring the task process without having to poll constantly.

[0094] Figure 6 This is a schematic diagram illustrating an exemplary implementation of a task processing method shown in this application, such as... Figure 6 As shown, this task processing method is applied to the host computer and specifically includes the following steps:

[0095] S601, determine the first-level subtask and second-level merging task in the target task to be executed, and determine multiple target register groups corresponding to the target task and the target function processing modules corresponding to the multiple target register groups from the accelerator register group management and mapping off-chip storage system. Based on the multiple target register groups, generate merging operation setting instructions and send them to the merging operation register in the accelerator register group management and mapping off-chip storage system to configure the merging operation register.

[0096] Figure 7 This is a framework diagram of a task processing method shown in this application. The following will combine... Figure 7 right Figure 6 The implementation methods of the embodiments will be described in detail.

[0097] The accelerator register group management and mapping off-chip memory system adopts the accelerator register group management and mapping off-chip memory system described above.

[0098] In this embodiment of the application, the target task to be executed is divided into a first-level sub-task and a second-level merged task.

[0099] Each first-level subtask corresponds to a target function processing module and a target register group. The second-level merging task can be processed based on one of the function processing modules within the target function processing module. The second-level merging task refers to merging the result data corresponding to each first-level subtask (for example, merging operations such as consecutive addition or subtraction of the result data corresponding to each first-level subtask).

[0100] In this application, the number of first-level subtasks corresponding to the target task to be executed is first determined, and multiple target register groups are determined from the accelerator register group management and mapping off-chip memory system based on the number of first-level subtasks. For example, if the target task is to first perform the calculation of 5 first-level subtasks and then add the calculation results of these 5 first-level subtasks together, then 5 target register groups are determined from the accelerator register group management and mapping off-chip memory system, and the target function processing modules corresponding to these 5 target register groups are determined respectively. A merge operation setting instruction is generated and sent to the merge operation register in the accelerator register group management and mapping off-chip memory system to configure the merge operation register. In other words, the merging operation register setting module of the host computer can write "5" into the merging operation register to represent that register group 1 to register group 5 are the target register groups (the default counting starts from register group 1, that is, writing "5" into the merging operation register means that register group 1 to register group 5 are hit). It also means that after performing the calculation of 5 first-level sub-tasks based on register group 1 to register group 5 respectively, the calculation results of these 5 first-level sub-tasks need to be merged. Correspondingly, since the register groups and function processing modules correspond one-to-one, it also means that function processing modules 1 to 5 are the target function processing modules.

[0101] S602 generates the initialization instructions corresponding to the target task and sends them to the target register group.

[0102] After the target register group is determined as described above, the host computer's initialization module generates initialization instructions and sends them to the target register group. These initialization instructions carry the parameters required to configure the relevant registers within the target register group.

[0103] Taking the target register groups as register groups 1 to 5 as an example, the initialization instructions carry the configuration parameters corresponding to register groups 1 to 5 respectively.

[0104] S603, after detecting that the target register group has completed the parameter configuration of its respective configuration-related registers according to the initialization instruction, issues a task start instruction to the enable function processing register in the target register group.

[0105] Taking the target register groups as register groups 1 to 5 as an example, after detecting that each of register groups 1 to 5 has completed the parameter configuration of its contained configuration-related registers, the host computer's calculation activation module issues a task start instruction to the activation function processing register contained in each of register groups 1 to 5. That is, it can be understood as writing "1" to the activation function processing register contained in each of register groups 1 to 5 to represent the activation function processing.

[0106] The target register group includes at least the following configuration-related registers: input data start address register, input data length register, output data start address register, output data length register, function processing mode selection register, and data format selection register. In addition, the function processing timeout configuration register is an optional configurable register. If the initialization instruction does not include configuration parameters for the function processing timeout configuration register, the default timeout parameters will be used.

[0107] In some implementations, if the host computer selects the interrupt notification mode when obtaining the task processing status of the target function processing module, the initialization instruction at this time also needs to carry the parameter for configuring the interrupt notification register, that is, write "1" to the interrupt notification register to indicate that the interrupt notification mode is selected to obtain the task processing status of the target function processing module.

[0108] S604, control the target function processing module to execute its corresponding first-level subtask according to the parameters configured in its corresponding configuration related register, and determine the merging function processing module for performing the second-level merging task from the target function processing module, control the merging function processing module to execute the second-level merging task based on the parameters configured in the merging operation register, and obtain the processing status of the target task based on the status related registers contained in the target register group.

[0109] In this application, for any target function processing module, the target function processing module is controlled to execute its corresponding first-level subtask according to the parameters configured in its corresponding configuration-related registers. Then, according to the parameters configured in the output data start address register and output data length register of the target function processing module, the subtask result data of the first-level subtask is stored in the data storage medium of the accelerator register group management and mapping off-chip storage system.

[0110] Continuing with the example of register groups 1 through 5 as the target register groups and function processing modules 1 through 5 as the target function processing modules, function processing module 1 processes tasks according to the parameters configured in the input data start address register, input data length register, function processing mode selection register, data format selection register, and function processing timeout configuration register within register group 1. It then combines these parameters with those configured in the output data start address register and output data length register within register group 1 to store the subtask result data of the first-level subtask 1 corresponding to function processing module 1 in the data storage medium of the accelerator register group management and mapping off-chip storage system. The processing of other first-level subtasks follows the same logic and will not be elaborated further. Finally, the subtask result data corresponding to the five first-level subtasks can be obtained.

[0111] Under normal circumstances, the merge function processing module for the secondary merge task is function processing module 1 by default.

[0112] After obtaining the subtask result data corresponding to each first-level subtask, the control merging function processing module obtains the subtask result data corresponding to the first-level subtask based on the parameters configured in the merging operation register. Specifically, after determining the value written to the merging operation register, the merging function processing module can determine which register groups' output data-related parameters need to be used to determine the storage location of the subtask result data. After the merging function processing module knows the storage location of each subtask result data, it reads the subtask result data from the data storage medium and performs a second-level merging task on all subtask result data to obtain the processing result corresponding to the target task.

[0113] Since the merging function processing module is the default function processing module 1, the processing result obtained by the above-mentioned function processing module 1 after performing a second-level merging task on all subtask result data is stored in the data storage medium. Its storage location is determined according to the parameters configured in the output data start address register and the output data length register in register group 1.

[0114] Throughout the process, functional processing module 1 first stores the subtask result data of its corresponding first-level subtask in the corresponding location according to the parameters configured in the output data start address register and output data length register in register group 1. After functional processing module 1 performs a second-level merging task on all subtask result data, it also stores the final processing result in the corresponding location according to the parameters configured in the output data start address register and output data length register in register group 1. Simply put, the subtask result data of the first-level subtask corresponding to functional processing module 1 is first stored in this corresponding location, and the final processing result after executing the second-level merging task updates the stored data in this corresponding location.

[0115] S605: After determining that the target task has been completed based on the processing status, obtain the result data corresponding to the target task.

[0116] Among them, such as Figure 7 As shown, when the end function processing register in the target register group queries the function processing real-time status register in the target register group and learns that the task processing corresponding to the target register group has ended, the end function processing register will write "1" to indicate the end of the current function processing and notify the host computer's calculation end module that the task processing corresponding to the target register group has ended.

[0117] As can be seen from the above introduction, the merge function processing module is the default function processing module 1. After the task is completed, the host computer obtains the result data corresponding to the target task from the data storage medium of the accelerator register group management and mapping off-chip storage system according to the parameters configured in the output data start address register and output data length register in register group 1.

[0118] The embodiments of this application support parallel computing, which can accelerate the computing process and meet the needs of high-performance computing even with a large workload through the collaborative work of multiple register groups and multiple functional processing modules.

[0119] Figure 8 This is a schematic diagram of a host computer shown in this application, such as... Figure 8 As shown, the host computer includes an initialization module 801, a calculation start module 802, a status detection module 803, and a calculation end module 804, wherein:

[0120] Initialization module 801 is used to determine the target register group and the target function processing module corresponding to the target register group from the accelerator register group management and mapping off-chip memory system, and to issue initialization instructions corresponding to the target task to be executed to the target register group.

[0121] The calculation start module 802 is used to send a task start instruction to the start function processing register in the target register group after detecting that the target register group has completed the parameter configuration of the configuration-related registers contained therein according to the initialization instruction, and control the target function processing module to execute the target task according to the parameters configured in the configuration-related registers.

[0122] The status detection module 803 is used to obtain the processing status of the target task based on the status-related registers contained in the target register group;

[0123] The calculation completion module 804 is used to obtain the result data corresponding to the target task after the target task has been completed based on the processing status.

[0124] The host computer proposed in this application can realize the parallel processing of multiple tasks by allocating task processing to idle register groups and function processing modules, thereby improving the overall task processing efficiency. It provides two task status monitoring methods: interrupt notification and polling mode, which makes the acquisition of task status more flexible and efficient. In particular, in interrupt notification mode, the host computer can promptly know the interruption or completion status of the task, thereby effectively monitoring the task process without having to poll constantly.

[0125] Furthermore, the calculation termination module 804 is also used to: obtain the output data configuration parameters carried by the initialization instruction, the output data configuration parameters including the configuration parameters corresponding to the output data start address register and the output data length register in the configuration related registers respectively; and obtain the result data corresponding to the target task from the data storage medium of the accelerator register group management and mapping off-chip storage system based on the output data configuration parameters.

[0126] Furthermore, the status detection module 803 is also used to: determine whether the host computer has started the interrupt notification mechanism; in response to the host computer starting the interrupt notification mechanism, receive the task interrupt notification sent by the interrupt notification register in the target register group when the interruption of the target task execution is detected, or receive the task completion notification sent by the interrupt notification register in the target register group when the interruption of the target task execution is detected; in response to the host computer not starting the interrupt notification mechanism, during the execution of the target task, poll the function processing real-time status register in the target register group to obtain the processing status of the target task in a polling mode.

[0127] Figure 9 This is a schematic diagram of a host computer shown in this application, such as... Figure 9 As shown, the host computer includes a merging operation register setting module 901, an initialization module 902, a calculation start module 903, a status detection module 904, and a calculation end module 905, wherein:

[0128] The merge operation register setting module 901 is used to determine the first-level subtask and the second-level merge task in the target task to be executed, and to determine multiple target register groups corresponding to the target task and the target function processing modules corresponding to the multiple target register groups from the accelerator register group management and mapping off-chip storage system. Based on the multiple target register groups, it generates merge operation setting instructions and sends them to the merge operation register in the accelerator register group management and mapping off-chip storage system to configure the merge operation register.

[0129] Initialization module 902 is used to generate initialization instructions corresponding to the target task and send them to the target register group;

[0130] The calculation start module 903 is used to send a task start instruction to the start function processing register in the target register group after detecting that the target register group has completed the parameter configuration of its respective configuration related registers according to the initialization instruction. It controls the target function processing module to execute its corresponding first-level subtask according to the parameters configured in its corresponding configuration related register, and determines the merging function processing module for performing the second-level merging task from the target function processing module, and controls the merging function processing module to execute the second-level merging task based on the parameters configured in the merging operation register.

[0131] The status detection module 904 is used to obtain the processing status of the target task based on the status-related registers contained in the target register group;

[0132] The calculation completion module 905 is used to obtain the result data corresponding to the target task after the target task has been completed based on the processing status.

[0133] The host computer proposed in this application can support parallel computing. Even with a large workload, it can accelerate the computing process through the collaborative work of multiple register groups and multiple functional processing modules, thus meeting the needs of high-performance computing.

[0134] Furthermore, the calculation activation module 903 is also used to: control the merging function processing module to obtain the subtask result data corresponding to the first-level subtask based on the parameters configured in the merging operation register; and control the merging function processing module to execute the second-level merging task on the subtask result data to obtain the processing result corresponding to the target task.

[0135] To implement the above embodiments, this application also proposes an electronic device 1000, such as... Figure 10 As shown, the electronic device 1000 includes a processor 1001 and a memory 1002 communicatively connected to the processor. The memory 1002 stores instructions that can be executed by at least one processor. The instructions are executed by at least one processor 1001 to implement the task processing method as shown in the above embodiment.

[0136] To implement the above embodiments, this application also proposes a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to implement the task processing method shown in the above embodiments.

[0137] To implement the above embodiments, this application also proposes a computer program product, including a computer program that, when executed by a processor, implements the task processing method shown in the above embodiments.

[0138] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0139] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0140] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0141] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. An accelerator register set management and mapping off-chip memory system, characterized in that, Includes buses, data storage media, and parallel accelerator devices, wherein: The data storage medium and the parallel accelerator device are connected via the bus; The parallel accelerator device includes a register group module, N functional processing modules, and N processing status modules; The register group module includes a version register, a merge operation register, and N register groups. Each register group includes a configuration-related register, a status-related register, a reset register, an enable function processing register, and an end function processing register. The version register is used to record the version information of the register group; The merge operation register is used to mark the register group to be merged; The reset register is used to reset the state of each register in its register group; Each functional processing module of the parallel accelerator device performs its own task acceleration processing simultaneously based on its corresponding register group. The register group corresponds one-to-one with the functional processing module and provides support for the corresponding functional processing module. The functional processing module corresponds one-to-one with the processing status module, and the processing status module is used to indicate the processing status of the corresponding functional processing module. The status-related registers include a real-time status register for function processing and an interrupt notification register; The real-time status register for the function processing is used to record the processing status of the function processing module. The interrupt notification register is used to select the mode in which the host computer obtains the processing status of the functional processing module. The modes include polling mode and interrupt notification mode.

2. The system according to claim 1, characterized in that, in: The configuration-related registers include the following registers: The input data start address register is used to configure the starting address for storing the input data. The input data length register is used to configure the length of the input data; The output data start address register is used to configure the starting address for storing the output data. Output data length register, used to configure the length of the output data; Function processing mode selection register, used to select the function processing mode; The data format selection register is used to select the data format. The function processing timeout configuration register is used to configure timeout-related parameters.

3. The system according to claim 2, characterized in that, Both the input data and the output data are stored in a data storage medium.

4. A parallel accelerator device, characterized in that, It includes a register group module, N functional processing modules and N processing status modules, and is applied to the system as described in any one of claims 1-3.

5. A task processing method, characterized in that, Applications in host computers include: The system determines the target register group and the target function processing module corresponding to the target register group from the accelerator register group management and mapping off-chip memory system, and issues the initialization instruction corresponding to the target task to be executed to the target register group; After detecting that the target register group has completed the parameter configuration of its configuration-related registers according to the initialization instruction, a task start instruction is issued to the enable function processing register in the target register group; The target function processing module is controlled to execute the target task according to the parameters configured in the configuration-related registers, and to obtain the processing status of the target task based on the status-related registers contained in the target register group; After the target task has been completed based on the processing status, obtain the result data corresponding to the target task; The accelerator register group management and mapping off-chip memory system adopts the system described in any one of claims 1-3.

6. The method according to claim 5, characterized in that, The step of obtaining the result data corresponding to the target task includes: Obtain the output data configuration parameters carried by the initialization instruction. The output data configuration parameters include the configuration parameters corresponding to the output data start address register and the output data length register in the configuration-related registers, respectively. Based on the output data configuration parameters, the result data corresponding to the target task is obtained from the data storage medium of the accelerator register group management and mapping off-chip storage system.

7. The method according to claim 5, characterized in that, The status-related registers include a real-time status register for functional processing and an interrupt notification register. Obtaining the processing status of the target task based on the status-related registers included in the target register set includes: Determine whether the host computer has started the interrupt notification mechanism; In response to the host computer starting the interrupt notification mechanism, the system receives a task interruption notification sent by the interrupt notification register in the target register group when the execution of the target task is interrupted, or receives a task completion notification sent by the interrupt notification register in the target register group when the execution of the target task is completed. In response to the host computer not starting an interrupt notification mechanism, during the execution of the target task, a polling mode is used to poll the real-time status register of the function processing in the target register group to obtain the processing status of the target task.

8. A task processing method, characterized in that, Applications in host computers include: The system identifies the first-level subtasks and second-level merging tasks in the target task to be executed, and determines multiple target register groups corresponding to the target task and the target function processing modules corresponding to the multiple target register groups from the accelerator register group management and mapping off-chip storage system. Based on the multiple target register groups, the system generates a merging operation setting instruction and sends it to the merging operation register in the accelerator register group management and mapping off-chip storage system to configure the merging operation register. The initialization instructions corresponding to the target task are generated and sent to the target register group; After detecting that the target register group has completed the parameter configuration of its respective configuration-related registers according to the initialization instruction, a task start instruction is issued to the enable function processing register in the target register group; The target function processing module is controlled to execute its corresponding first-level subtask according to the parameters configured in its corresponding configuration related register, and a merging function processing module for performing the second-level merging task is determined from the target function processing module. The merging function processing module is controlled to execute the second-level merging task based on the parameters configured in the merging operation register, and the processing status of the target task is obtained based on the status related registers contained in the target register group. After the target task has been completed based on the processing status, obtain the result data corresponding to the target task; The accelerator register group management and mapping off-chip memory system adopts the system described in any one of claims 1-3.

9. The method according to claim 8, characterized in that, The control module for the merging function to execute the secondary merging task based on the parameters configured in the merging operation register includes: The merge function processing module is controlled to obtain the subtask result data corresponding to the first-level subtask based on the parameters configured in the merge operation register; The merge function processing module is controlled to perform the secondary merge task on the subtask result data to obtain the processing result corresponding to the target task.

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