A semiconductor device and its fabrication method

Abstract

This invention discloses a semiconductor device and its fabrication method. The semiconductor device includes: a superjunction structure, wherein a first conductivity type pillar and an adjacent second conductivity type pillar form a superjunction unit; a first intrinsic layer, located on one side of the superjunction structure along a second direction; and a plurality of cell units, each corresponding to a superjunction unit. Each cell unit includes: a carrier storage region and a second conductivity type connection region, wherein the carrier storage region is configured as a first conductivity type, and along a first direction, the carrier storage region and the second conductivity type connection region are adjacent to each other on the side of the first intrinsic layer away from the superjunction unit; a second conductivity type body region, located on the side of the carrier storage region and the second conductivity type connection region away from the superjunction unit; and an active region, located on the side of the second conductivity type body region away from the superjunction unit. This invention can achieve a lower forward voltage drop while reducing the device's turn-off time and turn-off loss.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] With the development of technology, the superjunction concept has been further extended to insulated gate bipolar transistors (IGBTs), thus giving rise to superjunction IGBTs.

[0003] To effectively maintain a sufficient minority carrier concentration in the drift region of a superjunction IGBT, existing superjunction IGBTs typically employ floating P-type pillars with a high-concentration N-type layer on top of the drift region for N-type and P-type superjunction IGBTs. However, this configuration results in the inability to quickly remove the minority carriers stored in the P-type or N-type pillars during device turn-off, leading to prolonged turn-off time, increased turn-off losses, and consequently affecting the device's high-frequency performance. Summary of the Invention

[0004] This invention provides a semiconductor device and its fabrication method to solve the problems of prolonged turn-off time and increased turn-off loss in current superjunction IGBTs.

[0005] In a first aspect, the present invention provides a semiconductor device, wherein the semiconductor device comprises:

[0006] A superjunction structure, along a first direction, includes alternating first conductivity type pillars and second conductivity type pillars; a first conductivity type pillar and an adjacent second conductivity type pillar form a superjunction unit;

[0007] The first intrinsic layer, along the second direction, is located on one side of the superjunction structure; the first direction is perpendicular to the second direction.

[0008] Multiple cellular units are arranged in a one-to-one correspondence with the superjunction unit, and the cellular units are located on the side of the first intrinsic layer away from the superjunction unit;

[0009] Cellular units include:

[0010] The carrier storage region and the second conductivity type connection region are configured as the first conductivity type. Along the first direction, the carrier storage region and the second conductivity type connection region are disposed adjacent to each other on the side of the first intrinsic layer away from the superjunction unit. The vertical projection of the second conductivity type connection region on the first intrinsic layer covers at least part of the vertical projection of the second conductivity type pillar on the first intrinsic layer.

[0011] The second conductivity type body region is located on the side of the carrier storage region and the second conductivity type connection region away from the superjunction unit;

[0012] The active region is located on the side of the second conductivity type body region away from the superjunction unit;

[0013] The gate structure extends from the side of the active region away from the superjunction cell towards the direction closer to the first intrinsic layer.

[0014] Optionally, the semiconductor device further includes: at least one second intrinsic layer;

[0015] The superjunction structure includes at least two sub-superjunction structures, which are arranged along a second direction. Each sub-superjunction structure includes a first conductivity type sub-pillar and a second conductivity type sub-pillar arranged alternately along a first direction. The second intrinsic layer is located between two adjacent sub-superjunction structures.

[0016] Optionally, the thickness of the first intrinsic layer ranges from 0.5 μm to 1 μm; the thickness of the second intrinsic layer ranges from 0.5 μm to 1 μm.

[0017] Optionally, the active region includes a first active region and a second active region;

[0018] The first active region is configured with a first conductivity type, and the second active region is configured with a second conductivity type; along the first direction, the first active region is located close to the gate structure, and the second active region is located on the side of the first active region away from the gate structure.

[0019] Optionally, the gate structure includes: a gate and a gate insulating layer;

[0020] The cell unit includes a gate trench that penetrates the active region, the second conductivity type body region, and extends to the carrier storage region; the gate is located in the gate trench, and the gate insulating layer is located in the gate trench and surrounds the gate.

[0021] Optionally, the doping concentration of the carrier storage region is greater than the doping concentration of the first conductivity type pillar.

[0022] Optionally, the semiconductor device further includes: an emitter and a collector structure;

[0023] The emitter is located on the side of the cell unit away from the superjunction structure, and the emitter is in contact with the active region;

[0024] The collector structure includes a collector electrode and a second conductivity type collector region. The second conductivity type collector region is located on the side of the superjunction structure away from the first intrinsic layer, and the collector electrode is located on the side of the second conductivity type collector region away from the first intrinsic layer.

[0025] Secondly, the present invention provides a method for fabricating a semiconductor device, wherein the fabrication method includes:

[0026] A superjunction structure is provided, wherein along a first direction, the superjunction structure includes alternating first conductivity type pillars and second conductivity type pillars; a first conductivity type pillar and an adjacent second conductivity type pillar form a superjunction unit;

[0027] A first intrinsic layer is formed on one side of the superjunction structure along the second direction; the first direction is perpendicular to the second direction.

[0028] Multiple cellular units are formed on the side of the first intrinsic layer away from the superjunction structure, with each cellular unit corresponding to a superjunction unit. The formation of the cellular units includes:

[0029] A carrier storage region and a second conductivity type connection region are formed on the side of the first intrinsic layer away from the superjunction unit; the carrier storage region is configured as a first conductivity type, and along the first direction, the carrier storage region and the second conductivity type connection region are arranged adjacent to each other, and the vertical projection of the second conductivity type connection region on the first intrinsic layer covers at least part of the vertical projection of the second conductivity type pillar on the first intrinsic layer;

[0030] A second conductivity type body region is formed on the side of the carrier storage region and the second conductivity type connection region away from the superjunction unit;

[0031] An active region is formed on the side of the second conductivity type body region away from the superjunction unit;

[0032] A gate structure is formed that extends from the side of the active region away from the superjunction cell towards the direction of the first intrinsic layer.

[0033] Optionally, a carrier storage region and a second conductivity type connection region are formed on the side of the first intrinsic layer away from the superjunction unit, including:

[0034] A carrier storage region is formed on the side of the first intrinsic layer away from the superjunction unit;

[0035] Using photolithography and doping processes, a second conductivity type connection region is formed within the carrier storage region.

[0036] Optionally, prior to providing the superjunction structure, the following are also included:

[0037] Provide a substrate of the first conductivity type;

[0038] Provides superjunction structures, including:

[0039] A superjunction structure is formed on one side of a substrate of the first conductivity type;

[0040] After forming multiple cell units on the side of the first intrinsic layer away from the superjunction structure, it also includes:

[0041] An emitter is formed on the side of the cellular unit away from the superjunction structure;

[0042] The substrate of the first conductivity type is thinned.

[0043] A second conductivity type collector region is formed in a first conductivity type substrate using a doping process;

[0044] A collector electrode is formed on the side of the collector region of the second conductivity type away from the superjunction structure.

[0045] The technical solution of this invention provides a first intrinsic layer on one side of the superjunction unit, causing the second conductivity type pillar to float. A first conductivity type carrier storage region is located on the side of the second conductivity type body region closest to the first intrinsic layer. This allows the drift region to effectively retain a sufficient minority carrier concentration when the device is turned on. During device turn-off, the first intrinsic layer is depleted, and the second conductivity type pillar connects to the second conductivity type connection region. Excess carriers can be drawn away more quickly through the second conductivity type pillar and the second conductivity type connection region, resulting in a smaller tail current and lower turn-off loss. This invention achieves a lower forward voltage drop while significantly reducing the device's turn-off time and turn-off loss, and ensures high withstand voltage, thereby improving the device's high-frequency application performance.

[0046] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0049] Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0050] Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0051] Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0052] Figure 5 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0053] Figures 6-10 This is a schematic diagram of the structure corresponding to each step in the fabrication method of a semiconductor device provided in an embodiment of the present invention;

[0054] Figure 11 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0055] Figures 12-18 This is a schematic diagram of some steps in another method for fabricating a semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0056] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0057] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0058] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention, such as... Figure 1 and Figure 2As shown, the semiconductor device includes: a superjunction structure 2, along a first direction X, the superjunction structure 2 including alternating first conductivity type pillars 211 and second conductivity type pillars 212. One first conductivity type pillar 211 and an adjacent second conductivity type pillar 212 form a superjunction unit 21. A first intrinsic layer 3, along a second direction Y, is located on one side of the superjunction structure 2. The first direction X is perpendicular to the second direction Y. A plurality of cell units 4 are arranged in a one-to-one correspondence with the superjunction unit 21, the cell units 4 being located on the side of the first intrinsic layer 3 away from the superjunction unit 21. The cell unit 4 includes: a carrier storage region 41 and a second conductivity type connection region 42, the carrier storage region 41 being configured as a first conductivity type. Along the first direction X, the carrier storage region 41 and the second conductivity type connection region 42 are arranged adjacent to each other on the side of the first intrinsic layer 3 away from the superjunction unit 21, the vertical projection of the second conductivity type connection region 42 on the first intrinsic layer 3 covers at least part of the vertical projection of the second conductivity type pillar 212 on the first intrinsic layer 3. The second conductivity type body region 43 is located on the side of the carrier storage region 41 and the second conductivity type connection region 42 away from the superjunction unit 21. The active region 44 is located on the side of the second conductivity type body region 43 away from the superjunction unit 21. The gate structure 45 extends from the side of the active region 44 away from the superjunction unit 21 towards the first intrinsic layer 3.

[0059] Specifically, Figure 1 and Figure 2 An exemplary embodiment of the present invention provides a semiconductor device including a trench-type superjunction IGBT device. In some embodiments of the present invention, the semiconductor device provided by the present invention may further include a planar superjunction IGBT device. The gate structure 45 may be disposed on the side of the active region 44 away from the superjunction unit 21, and the carrier storage region 41 may pass through the second conductivity type body region 43 and the active region 44 to contact the gate structure 45.

[0060] In this embodiment of the invention, for an N-type superjunction IGBT device, the first conductivity type may include N-type, and the second conductivity type may include P-type. For a P-type superjunction IGBT device, the first conductivity type may include P-type, and the second conductivity type may include N-type.

[0061] like Figure 1 and Figure 2As shown, the superjunction IGBT device may include a superjunction structure 2. The superjunction structure 2 includes first conductivity type pillars 211 and second conductivity type pillars 212 alternately arranged along a first direction X. The number and width of the first conductivity type pillars 211 and the second conductivity type pillars 212 can be arbitrarily set according to actual needs. For example, the width of the first conductivity type pillar 211 can be greater than the width of the second conductivity type pillar 212 to reduce the specific on-resistance of the device. Along the second direction Y, a thin first intrinsic layer 3 can be formed on one side of the superjunction structure 2. The first intrinsic layer 3 is an undoped semiconductor layer, and the semiconductor material can be the same as or different from the semiconductor material of other structures of the superjunction IGBT device provided in this embodiment of the invention. For example, the semiconductor material of the superjunction IGBT device provided in this embodiment of the invention may include at least one of silicon, silicon carbide, gallium nitride, etc.

[0062] The superjunction IGBT device may also include multiple cell units 4, which can be configured one-to-one with the superjunction unit 21. The cell unit 4 configured to correspond with the superjunction unit 21 can be located on the side of the first intrinsic layer 3 away from the superjunction unit 21.

[0063] Along the first direction X, a carrier storage region 41 of a first conductivity type and a connection region 42 of a second conductivity type are arranged adjacent to each other, and along the second direction Y, they are located on the side of the first intrinsic layer 3 away from the superjunction unit 21, wherein, as Figure 2 As shown, the vertical projection of the second conductivity type connection region 42 on the first intrinsic layer 3 can lie within the vertical projection of the second conductivity type pillar 212 on the first intrinsic layer 3. In this case, the vertical projection of the first conductivity type pillar 211 on the first intrinsic layer 3 can lie within the vertical projection of the carrier storage layer 41 on the first intrinsic layer 3. Figure 1 As shown, the vertical projection of the second conductivity type connection region 42 on the first intrinsic layer 3 can coincide with the vertical projection of the second conductivity type pillar 212 on the first intrinsic layer 3. In this case, the vertical projection of the first conductivity type pillar 211 on the first intrinsic layer 3 can coincide with the vertical projection of the carrier storage layer 41 on the first intrinsic layer 3. The doping concentration of the second conductivity type connection region 42 can be the same as or different from the doping concentration of the second conductivity type pillar 212.

[0064] A second conductivity type body region 43 and an active region 44 are disposed on the side of the carrier storage region 41 and the second conductivity type connection region 42 away from the superjunction unit 21. The carrier storage region 41 and the second conductivity type connection region 42 are located between the first intrinsic layer 3 and the second conductivity type body region 43, and both are in contact with the first intrinsic layer 3 and the second conductivity type body region 43. The active region 44 may include a first active region 441 and a second active region 442. The first active region 441 may be configured as a first conductivity type, and the second active region 442 may be configured as a second conductivity type. The gate structure 45 extends from the side of the active region 44 away from the superjunction unit 21 through the first active region 441 and the second conductivity type body region 43, and extends to the carrier storage region 41. The first active region 441 may be disposed on both sides of the gate structure 45, and both sides may be in contact with the first active region 441.

[0065] like Figure 1 As mentioned above, the structure of each cell unit 4 in the superjunction IGBT device can remain completely identical, such as... Figure 2 As shown, the carrier storage region 41 and the second conductivity type connection region 42 in each cell unit 4 of the superjunction IGBT device can be slightly different, ensuring that the vertical projection of the second conductivity type connection region 42 on the first intrinsic layer 3 covers at least part of the vertical projection of the second conductivity type pillar 212 on the first intrinsic layer 3.

[0066] In this embodiment of the invention, by setting a first intrinsic layer 3, the second conductivity type pillar 212 is in a floating state, and a first conductivity type carrier storage region 41 is provided on the side of the second conductivity type body region 43 near the first intrinsic layer 3. This makes it more difficult to extract minority carriers in the drift region when the device is turned on (for N-type superjunction IGBT devices, minority carriers are holes, and for P-type superjunction IGBT devices, minority carriers are electrons). Therefore, the drift region has a higher carrier concentration, resulting in a lower forward conduction voltage drop. The doping concentration of the carrier storage region 41 can be greater than the doping concentration of the first conductivity type pillar 211. A carrier storage region 41 with a higher doping concentration can better prevent minority carriers from being extracted. The doping concentration of the carrier storage region 41 can be arbitrarily set according to actual conditions. In this embodiment of the invention, a first intrinsic layer 3 is provided between the carrier storage region 41 and the superjunction structure 2, which can effectively prevent the carrier storage region 41 from affecting the charge balance state of the first conductivity type pillar 211 and the second conductivity type pillar 212, thereby causing a decrease in the device's withstand voltage. Meanwhile, in this embodiment of the invention, a second conductive type connection region 42 is provided between the second conductive type pillar 212 and the second conductive type body region 43, and the second conductive type connection region 42 and the second conductive type pillar 212 are isolated by a thin first intrinsic layer 3. During the device turn-off process, under the extremely low voltage of the collector 11, the first intrinsic layer 3 will be depleted, and the depletion region will extend into the second conductive type pillar 212. The potential of the second conductive type pillar 212 and the second conductive type connection region 42 is close, which is equivalent to the second conductive type pillar 212 and the second conductive type connection region 42 being connected. Therefore, during the device turn-off process, the first conductive type pillar 211 and the second conductive type pillar 212 can achieve mutual depletion more quickly, and the excess charge carriers can be drawn away more quickly through the second conductive type pillar 212 and the second conductive type connection region 42, thereby obtaining a smaller tail current and lower turn-off loss.

[0067] The technical solution of this invention involves providing a first intrinsic layer 3 on one side of the superjunction unit 21, causing the second conductivity type pillar 212 to float. A first conductivity type carrier storage region 41 is provided on the side of the second conductivity type body region 43 near the first intrinsic layer 3. This allows the drift region to effectively retain a sufficient minority carrier concentration when the device is turned on. During device turn-off, the first intrinsic layer 3 is depleted, and the second conductivity type pillar 212 connects to the second conductivity type connection region 42. Excess carriers can be drawn away more quickly through the second conductivity type pillar 212 and the second conductivity type connection region 42, resulting in a smaller tail current and lower turn-off loss. This invention achieves a lower forward conduction voltage drop while significantly reducing the device's turn-off time and turn-off loss, and ensures high withstand voltage, thereby improving the device's high-frequency application performance.

[0068] like Figure 2 As shown, the vertical projection of the second conductivity type connection region 42 on the first intrinsic layer 3 is located within the vertical projection of the second conductivity type pillar 212 on the first intrinsic layer 3. The width of the second conductivity type connection region 42 is set to be narrower. At this time, the contact area between the first conductivity type carrier storage region 41 and the second conductivity type body region 43 is larger. The carrier storage region 41 can better prevent minority carriers from entering the second conductivity type body region 43 and being drawn away, so that the device has a lower forward conduction voltage drop.

[0069] Optionally, based on the above embodiments, Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention, such as... Figure 3 and Figure 4 As shown, the semiconductor device further includes at least one second intrinsic layer 6. The superjunction structure 2 includes at least two sub-superjunction structures 2A, which are arranged along a second direction Y. The sub-superjunction structure 2A includes a first conductivity type sub-pillar 211A and a second conductivity type sub-pillar 212A arranged alternately along a first direction X. The second intrinsic layer 6 is located between two adjacent sub-superjunction structures 2A.

[0070] Specifically, the superjunction IGBT device may further include at least one thinner second intrinsic layer 6, which is an undoped semiconductor layer. The semiconductor material of this second intrinsic layer may be the same as or different from the semiconductor material of other structures in the superjunction IGBT device provided in this embodiment. The second intrinsic layer 6 can divide the superjunction structure 2 into at least two sub-superjunction structures 2A, which are arranged along the second direction Y. Each sub-superjunction structure 2A includes alternating first conductivity type sub-pillars 211A and second conductivity type sub-pillars 212A along the first direction X. The first conductivity type sub-pillar 211A and an adjacent second conductivity type sub-pillar 212A constitute a sub-superjunction unit 21A. Figures 1-4 As shown, the first conductivity type sub-pillar 211A in all sub-superjunction structures 2A constitutes the first conductivity type pillar 211, the second conductivity type sub-pillar 212A in all sub-superjunction structures 2A constitutes the second conductivity type pillar 212, the sub-superjunction unit 21A in all sub-superjunction structures 2A constitutes the superjunction unit 21, and all sub-superjunction structures 2A constitute the superjunction structure 2.

[0071] Figure 3 and Figure 4 An exemplary superjunction IGBT device is shown, including a second intrinsic layer 6. In some embodiments of the present invention, the number of second intrinsic layers 6 may be greater than one, and no specific limitation is made herein. Figures 1-4As shown, the second intrinsic layer 6 blocks the connection between the upper and lower portions of the second conductivity type pillar 212, further preventing minority carriers from being extracted through the second conductivity type pillar 212, thus further increasing the carrier concentration in the drift region and further reducing the forward conduction voltage drop of the device. The second intrinsic layer 6 is relatively thin and will not affect the charge balance between the first conductivity type pillar 211 and the second conductivity type pillar 212. Furthermore, during device turn-off, the thin second intrinsic layer 6 ensures the connection of multiple second conductivity type sub-pillars 212A, without affecting the rapid depletion of minority carriers. This configuration achieves a further lower on-state voltage drop while still maintaining a low turn-off time and turn-off loss.

[0072] Optionally, based on the above embodiments, refer to... Figures 1-4 The thickness of the first intrinsic layer 3 ranges from 0.5um to 1um; the thickness of the second intrinsic layer 6 ranges from 0.5um to 1um.

[0073] Specifically, the thickness of the first intrinsic layer 3 is relatively thin, which can be set to 0.5µm-1µm. The setting of the first intrinsic layer 3 ensures the floating of the second conductivity type pillar 212, and can effectively prevent the carrier storage region 41 from affecting the charge balance state of the first conductivity type pillar 211 and the second conductivity type pillar 212, thereby preventing the device's breakdown voltage from decreasing. At the same time, during the device turn-off process, the first intrinsic layer 3 will be depleted, ensuring the connection between the second conductivity type pillar 212 and the second conductivity type connection region 42. If the thickness of the first intrinsic layer 3 is set too thin, it will not be able to effectively prevent the carrier storage region 41 from affecting the charge balance state of the first conductivity type pillar 211 and the second conductivity type pillar 212, thereby preventing the device's breakdown voltage from decreasing. If the thickness of the first intrinsic layer 3 is set too thick, it will not be depleted during the device turn-off process, and the second conductivity type pillar 212 and the second conductivity type connection region 42 will not be connected, leading to an increase in the device's turn-off time and turn-off loss.

[0074] The thickness of the second intrinsic layer 6 is relatively thin, which can be set to 0.5um-1um. If the thickness of the second intrinsic layer 6 is set too thin, it will not be able to effectively block the connection between the upper and lower parts of the second conductivity type pillar 212, and will not be able to further reduce the forward conduction voltage drop of the device. If the thickness of the second intrinsic layer 6 is set too thick, multiple second conductivity type sub-pillars 212A will not be able to connect during the device turn-off process, affecting the rapid depletion of minority carriers.

[0075] Optionally, based on the above embodiments, refer to... Figures 1-4The active region 44 includes a first active region 441 and a second active region 442. The first active region 44 is configured with a first conductivity type, and the second active region 442 is configured with a second conductivity type. Along the first direction X, the first active region 441 is disposed close to the gate structure 45, and the second active region 442 is located on the side of the first active region 441 away from the gate structure 45.

[0076] Specifically, the active region 44 may include a first active region 441 and a second active region 442. The first active region 441 may be configured as a first conductivity type, and the second active region 442 may be configured as a second conductivity type. The vertical projection of the first active region 441 onto the first intrinsic layer 3 covers at least a portion of the vertical projection of the first conductivity type pillar 211 onto the first intrinsic layer 3. The gate structure 45 extends from the side of the active region 44 away from the superjunction unit 21, passing through the first active region 441 and the second conductivity type body region 43, and extends to the carrier storage region 41. The first active region 441 may be disposed on both sides of the gate structure 45, and both sides may be in contact with the first active region 441 to ensure normal device conduction. The second active region 442 is in contact with the second conductivity type body region 43, which can provide a discharge path for minority carriers when the device is turned off.

[0077] Optionally, based on the above embodiments, refer to... Figures 1-4 The gate structure 45 includes a gate 451 and a gate insulating layer 452. The cell unit 4 includes a gate trench 46, which penetrates the active region 44, the second conductivity type body region 43, and extends to the carrier storage region 41. The gate 451 is located within the gate trench 46, and the gate insulating layer 452 is located within the gate trench 46 and surrounds the gate 451.

[0078] Specifically, the cell unit 4 may also be provided with a gate trench 46. The gate trench 46 can pass through the first active region 441 and the second conductivity type body region 43 from the side of the first active region 441 away from the superjunction unit 21, and extend into the carrier storage region 41. The gate 451 is located in the gate trench 46, and the gate insulating layer 452 is also located in the gate trench 46, and the gate insulating layer 452 surrounds the gate 451, effectively insulating the gate 451 from the emitter 5.

[0079] Optionally, based on the above embodiments, refer to... Figures 1-4 The doping concentration of the carrier storage region 41 is greater than the doping concentration of the first conductivity type pillar 211.

[0080] Specifically, a carrier storage region 41 of the first conductivity type is provided on the side of the second conductivity type body region 43 near the first intrinsic layer 3. This arrangement creates a higher energy peak in the carrier storage region 41 when the device is turned on, making it more difficult to extract minority carriers from the drift region (for N-type superjunction IGBT devices, minority carriers are holes; for P-type superjunction IGBT devices, minority carriers are electrons). Therefore, the drift region has a higher carrier concentration, resulting in a lower forward voltage drop. The doping concentration of the carrier storage region 41 can be greater than that of the first conductivity type pillar 211. A higher doping concentration in the carrier storage region 41 can better prevent minority carriers from being extracted. However, the doping concentration of the carrier storage region 41 should not be set too high to avoid affecting the electron or hole flow when the device is turned on, thus increasing the on-resistance of the device. The doping concentration of the carrier storage region 41 can be arbitrarily set according to actual conditions.

[0081] Optionally, based on the above embodiments, refer to... Figures 1-4 The semiconductor device also includes an emitter 5 and a collector structure 1. The emitter 5 is located on the side of the cell 4 away from the superjunction structure 2, and the emitter 5 is in contact with the active region 44. The collector structure 1 includes a collector 11 and a second conductivity type collector region 12. The second conductivity type collector region 12 is located on the side of the superjunction structure 2 away from the first intrinsic layer 3, and the collector 11 is located on the side of the second conductivity type collector region 12 away from the first intrinsic layer 3.

[0082] Specifically, the emitter 5 is located on the side of the active region 44 away from the superjunction structure 2. The emitter 5 can contact the first active region 441 to ensure the normal conduction of the device, and can also contact the second active region 442 to ensure the normal discharge of minority carriers when the device is turned off.

[0083] A second conductivity type collector region 12 may be provided on the side of the superjunction structure 2 away from the first intrinsic layer 3, and a collector electrode 11 may be provided on the side of the second conductivity type collector region 12 away from the first intrinsic layer 3. In some embodiments of the present invention, a first conductivity type field cutoff layer (FS layer) may also be provided between the superjunction structure 2 and the second conductivity type collector region 12.

[0084] Figure 5 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. Figures 6-10 This is a schematic diagram of the structure corresponding to each step in the fabrication method of a semiconductor device provided in an embodiment of the present invention, as shown below. Figure 5 As shown, the preparation method includes:

[0085] S100: Provides a superjunction structure, which, along a first direction, includes alternating first conductive type pillars and second conductive type pillars; a first conductive type pillar and an adjacent second conductive type pillar form a superjunction unit.

[0086] Specifically, such as Figure 6 As shown, the superjunction IGBT device may include a superjunction structure 2. The superjunction structure 2 includes a first conductive type pillar 211 and a second conductive type pillar 212 arranged alternately along the first direction X. The number and width of the first conductive type pillar 211 and the second conductive type pillar 212 can be arbitrarily set according to actual needs. For example, the width of the first conductive type pillar 211 can be greater than the width of the second conductive type pillar 212 to reduce the specific on-resistance of the device.

[0087] S110: A first intrinsic layer is formed on one side of the superjunction structure along the second direction; the first direction is perpendicular to the second direction.

[0088] Specifically, such as Figure 7 As shown, along the second direction Y, a thin first intrinsic layer 3 can be formed on one side of the superjunction structure 2 by an epitaxial process. The first intrinsic layer 3 is an undoped semiconductor layer. The semiconductor material can be the same as or different from the semiconductor material of other structures of the superjunction IGBT device provided in this embodiment of the invention. For example, the semiconductor material of the superjunction IGBT device provided in this embodiment of the invention can include at least one of silicon, silicon carbide, gallium nitride, etc.

[0089] S120: A carrier storage region and a second conductivity type connection region are formed on the side of the first intrinsic layer away from the superjunction unit; the carrier storage region is configured as a first conductivity type, and the carrier storage region and the second conductivity type connection region are arranged adjacent to each other along the first direction, and the vertical projection of the second conductivity type connection region on the first intrinsic layer covers at least part of the vertical projection of the second conductivity type pillar on the first intrinsic layer.

[0090] Specifically, such as Figure 8As shown, a carrier storage region 41 and a second conductivity type connection region 42 are formed on the side of the first intrinsic layer 3 away from the superjunction unit 21 through an epitaxial process. Along the first direction X, the carrier storage region 41 and the second conductivity type connection region 42 are arranged adjacent to each other, and along the second direction Y, they are located on the side of the first intrinsic layer 3 away from the superjunction unit 21. The vertical projection of the second conductivity type connection region 42 on the first intrinsic layer 3 can lie within the vertical projection of the second conductivity type pillar 212 on the first intrinsic layer 3. In this case, the vertical projection of the first conductivity type pillar 211 on the first intrinsic layer 3 can also lie within the vertical projection of the carrier storage layer 41 on the first intrinsic layer 3. The vertical projection of the second conductivity type connection region 42 on the first intrinsic layer 3 can coincide with the vertical projection of the second conductivity type pillar 212 on the first intrinsic layer 3. In this case, the vertical projection of the first conductivity type pillar 211 on the first intrinsic layer 3 can also coincide with the vertical projection of the carrier storage layer 41 on the first intrinsic layer 3. The doping concentration of the second conductivity type connection region 42 can be the same as or different from the doping concentration of the second conductivity type pillar 212.

[0091] S130: A second conductivity type body region is formed on the side of the carrier storage region and the second conductivity type connection region away from the superjunction unit.

[0092] Specifically, such as Figure 9 As shown, a second conductivity type body region 43 is formed by epitaxial processing on the side of the carrier storage region 41 and the second conductivity type connection region 42 away from the superjunction unit 21.

[0093] S140: An active region is formed on the side of the second conductivity type body region away from the superjunction unit.

[0094] Specifically, such as Figure 9 As shown, a first active region 441 and a second active region 442 can be formed by doping and high-temperature annealing the side of the second conductivity type body region 43 away from the superjunction unit 21. The active region 44 may include the first active region 441 and the second active region 442. The first active region 441 may be configured as a first conductivity type, and the second active region 442 may be configured as a second conductivity type.

[0095] S150: A gate structure is formed extending from the active region away from the superjunction unit towards the first intrinsic layer. The gate structure, the active region, the second conductivity type body region, the carrier storage region, and the second conductivity type connection region constitute a cell unit, and the cell units are arranged in a one-to-one correspondence with the superjunction unit.

[0096] Specifically, such as Figure 10As shown, the first active region 441 and the second conductivity type body region 43 can be etched through the side of the first active region 441 away from the superjunction unit 21 by photolithography and etching processes, and a portion of the carrier storage region 41 is etched to form a gate trench 46, in which a gate insulating layer 452 and a gate 451 are formed.

[0097] In this embodiment of the invention, by setting a first intrinsic layer 3, the second conductivity type pillar 212 is in a floating state, and a first conductivity type carrier storage region 41 is provided on the side of the second conductivity type body region 43 near the first intrinsic layer 3. This makes it more difficult to extract minority carriers in the drift region when the device is turned on (for N-type superjunction IGBT devices, minority carriers are holes, and for P-type superjunction IGBT devices, minority carriers are electrons). Therefore, the drift region has a higher carrier concentration, resulting in a lower forward conduction voltage drop. The doping concentration of the carrier storage region 41 can be greater than the doping concentration of the first conductivity type pillar 211. A carrier storage region 41 with a higher doping concentration can better prevent minority carriers from being extracted. The doping concentration of the carrier storage region 41 can be arbitrarily set according to actual conditions. In this embodiment of the invention, a first intrinsic layer 3 is provided between the carrier storage region 41 and the superjunction structure 2, which can effectively prevent the carrier storage region 41 from affecting the charge balance state of the first conductivity type pillar 211 and the second conductivity type pillar 212, thereby causing a decrease in the device's withstand voltage. Meanwhile, in this embodiment of the invention, a second conductive type connection region 42 is provided between the second conductive type pillar 212 and the second conductive type body region 43, and the second conductive type connection region 42 and the second conductive type pillar 212 are isolated by a thin first intrinsic layer 3. During the device turn-off process, under the extremely low voltage of the collector 11, the first intrinsic layer 3 will be depleted, and the depletion region will extend into the second conductive type pillar 212. The potential of the second conductive type pillar 212 and the second conductive type connection region 42 is close, which is equivalent to the second conductive type pillar 212 and the second conductive type connection region 42 being connected. Therefore, during the device turn-off process, the first conductive type pillar 211 and the second conductive type pillar 212 can achieve mutual depletion more quickly, and the excess charge carriers can be drawn away more quickly through the second conductive type pillar 212 and the second conductive type connection region 42, thereby obtaining a smaller tail current and lower turn-off loss.

[0098] Optionally, based on the above embodiments, Figure 11 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention. Figures 12-18 This is a schematic diagram of some steps in another method for fabricating a semiconductor device provided in this embodiment of the invention, as shown below. Figure 11 As shown, the preparation method includes:

[0099] S200: Provides a substrate of the first conductivity type.

[0100] Specifically, such as Figure 12 As shown, a first conductivity type substrate 7 is first provided, which can be a low-doped substrate.

[0101] S210: A superjunction structure is formed on one side of a substrate of the first conductivity type. Along the first direction, the superjunction structure includes alternating first conductivity type pillars and second conductivity type pillars; a first conductivity type pillar and an adjacent second conductivity type pillar form a superjunction unit.

[0102] Specifically, such as Figure 12 As shown, superjunction structures can be formed using trench filling or multi-step epitaxial processes.

[0103] S220: A first intrinsic layer is formed on one side of the superjunction structure along the second direction; the first direction is perpendicular to the second direction.

[0104] Specifically, such as Figure 13 As shown, a first intrinsic layer 3 is epitaxially formed on the side of the superjunction structure 2 away from the substrate 7 of the first conductivity type.

[0105] S230: A carrier storage region is formed on the side of the first intrinsic layer away from the superjunction unit; the carrier storage region is set to the first conductivity type.

[0106] Specifically, such as Figure 14 As shown, a carrier storage region 41 is formed on the side of the first intrinsic layer 3 away from the superjunction structure 2.

[0107] S240: Using photolithography and doping processes, a second conductivity type connection region is formed in the carrier storage region. Along the first direction, the carrier storage region and the second conductivity type connection region are arranged adjacent to each other. The vertical projection of the second conductivity type connection region on the superjunction structure covers at least part of the vertical projection of the second conductivity type pillar on the superjunction structure.

[0108] Specifically, such as Figure 15 As shown, a second conductivity type connection region 42 is formed in the carrier storage region 41 using processes such as photolithography and ion implantation.

[0109] S250: A second conductivity type body region is formed on the side of the carrier storage region and the second conductivity type connection region away from the superjunction unit.

[0110] Specifically, such as Figure 16 As shown, a second conductivity type body region 43 is formed by epitaxial processing on the side of the carrier storage region 41 and the second conductivity type connection region 42 away from the superjunction unit 21.

[0111] S260: An active region is formed on the side of the second conductivity type body region away from the superjunction unit.

[0112] Specifically, such as Figure 16 As shown, the first active region 441 and the second active region 442 can be formed by doping and high-temperature annealing the side of the second conductivity type body region 43 away from the superjunction unit 21.

[0113] S270: A gate structure is formed extending from the side of the active region away from the superjunction unit towards the first intrinsic layer; the gate structure, the active region, the second conductivity type body region, the carrier storage region, and the second conductivity type connection region constitute a cell unit, and the cell unit is set in a one-to-one correspondence with the superjunction unit.

[0114] Specifically, such as Figure 17 As shown, the first active region 441 and the second conductivity type body region 43 can be etched through the side of the first active region 441 away from the superjunction unit 21 by photolithography and etching processes, and a portion of the carrier storage region 41 is etched to form a gate trench 46, in which a gate insulating layer 452 and a gate 451 are formed.

[0115] S280: An emitter is formed on the side of the cell unit away from the superjunction structure.

[0116] Specifically, such as Figure 18 As shown, an emitter 5 is formed on the side of the active region 44 away from the substrate 7 of the first conductivity type.

[0117] S290: Thinning process is performed on the substrate of the first conductivity type.

[0118] Specifically, such as Figure 18 As shown, the side of the first conductivity type substrate 7 away from the emitter 5 is thinned.

[0119] S291: A second conductivity type collector region is formed in a first conductivity type substrate using a doping process.

[0120] Specifically, such as Figure 1 As shown, a second conductivity type current collector region 12 and a first conductivity type field cutoff layer (FS layer) are formed by ion implantation and laser annealing.

[0121] S292: A collector electrode is formed on the side of the collector region of the second conductivity type away from the superjunction structure.

[0122] Specifically, such as Figure 1 As shown, a collector electrode 11 is formed on the side of the second conductivity type collector region 12 away from the superjunction structure 2.

[0123] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0124] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A semiconductor device, characterized by, The application relates to a super-junction structure and a cell unit thereof. The super-junction structure comprises first conductive type columns and second conductive type columns arranged alternately along a first direction; One of the first conductive type columns and one of the second conductive type columns form a super-junction unit; A first intrinsic layer is arranged on one side of the super-junction structure along a second direction, wherein the first direction is perpendicular to the second direction; A plurality of cell units are arranged one by one corresponding to the super-junction units, and the cell units are arranged on the side of the first intrinsic layer away from the super-junction units; The cell unit comprises: A carrier storage region and a second conductive type connecting region, the carrier storage region is arranged as the first conductive type, the carrier storage region and the second conductive type connecting region are arranged adjacently on the side of the first intrinsic layer away from the super-junction units along the first direction, and the vertical projection of the second conductive type connecting region on the first intrinsic layer covers at least part of the vertical projection of the second conductive type column on the first intrinsic layer; A second conductive type body region is arranged on the side of the carrier storage region and the second conductive type connecting region away from the super-junction units; An active region is arranged on the side of the second conductive type body region away from the super-junction units; A gate structure extends from the side of the active region away from the super-junction units to the side close to the first intrinsic layer.

2. The semiconductor device according to claim 1, wherein Further comprising: At least one second intrinsic layer; The super-junction structure comprises at least two sub-super-junction structures, the at least two sub-super-junction structures are arranged along the second direction, the sub-super-junction structure comprises first conductive type sub-columns and second conductive type sub-columns arranged alternately along the first direction, and the second intrinsic layer is arranged between two adjacent sub-super-junction structures.

3. The semiconductor device of claim 2, wherein, The thickness of the first intrinsic layer ranges from 0.5um to 1um, and the thickness of the second intrinsic layer ranges from 0.5um to 1um.

4. The semiconductor device of claim 1, wherein The active region comprises a first active region and a second active region; The first active region is arranged as the first conductive type, the second active region is arranged as the second conductive type, the first active region is arranged close to the gate structure along the first direction, and the second active region is arranged on the side of the first active region away from the gate structure.

5. The semiconductor device of claim 1, wherein The gate structure comprises a gate and a gate insulating layer; The cell unit comprises a gate trench, the gate trench penetrates the active region, the second conductive type body region and extends to the carrier storage region, the gate is arranged in the gate trench, and the gate insulating layer is arranged in the gate trench and surrounds the gate.

6. The semiconductor device of claim 1, wherein The doping concentration of the carrier storage region is greater than the doping concentration of the first conductive type column.

7. The semiconductor device of claim 1, wherein Further comprising: An emitter and a collector structure; The emitter is arranged on the side of the cell unit away from the super-junction structure, and the emitter is in contact with the active region; The collector structure comprises a collector and a second conductive type collector region, the second conductive type collector region is arranged on the side of the super-junction structure away from the first intrinsic layer, and the collector is arranged on the side of the second conductive type collector region away from the first intrinsic layer.

8. A method of manufacturing a semiconductor device, characterized by, The application relates to a super-junction structure and a cell unit thereof. A super-junction structure is provided, along a first direction, the super-junction structure comprising first-conductivity-type pillars and second-conductivity-type pillars arranged alternately; one of the first-conductivity-type pillars and one of the second-conductivity-type pillars form a super-junction cell; A first intrinsic layer is formed on one side of the super-junction structure along a second direction; the first direction is perpendicular to the second direction; A plurality of cell cells are formed on a side of the first intrinsic layer away from the super-junction structure, the cell cells are arranged one-to-one corresponding to the super-junction cells; forming the cell cells comprises: A carrier storage region and a second-conductivity-type connection region are formed on a side of the first intrinsic layer away from the super-junction cells; The carrier storage region is arranged to be of the first conductivity type, along the first direction, the carrier storage region is arranged adjacent to the second-conductivity-type connection region, and a vertical projection of the second-conductivity-type connection region on the first intrinsic layer covers at least part of a vertical projection of the second-conductivity-type pillars on the first intrinsic layer; A second-conductivity-type body region is formed on a side of the carrier storage region and the second-conductivity-type connection region away from the super-junction cells; An active region is formed on a side of the second-conductivity-type body region away from the super-junction cells; A gate structure is formed extending from a side of the active region away from the super-junction cells to a direction close to the first intrinsic layer.

9. The method of producing a semiconductor device according to claim 8, wherein Forming a carrier storage region and a second-conductivity-type connection region on a side of the first intrinsic layer away from the super-junction cells comprises: Forming a carrier storage region on a side of the first intrinsic layer away from the super-junction cells; Using photolithography and doping processes, the second-conductivity-type connection region is formed in the carrier storage region.

10. The method of producing a semiconductor device according to Claim 8, wherein Before providing the super-junction structure, further comprising: Providing a first-conductivity-type substrate; Providing the super-junction structure comprises: Forming the super-junction structure on a side of the first-conductivity-type substrate; After forming a plurality of cell cells on a side of the first intrinsic layer away from the super-junction structure, further comprising: Forming an emitter on a side of the cell cells away from the super-junction structure; Thinning the first-conductivity-type substrate; Using a doping process, a second-conductivity-type collector region is formed in the first-conductivity-type substrate; Forming a collector on a side of the second-conductivity-type collector region away from the super-junction structure.

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