Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof, which comprises the following steps: providing a substrate, wherein the substrate comprises a first region and a second region, and the substrate comprises a germanium-silicon layer and a first silicon cap layer stacked from bottom to top; sequentially forming a first interface layer and a gate oxide layer on the first silicon cap layer in the first region and the second region; removing the gate oxide layer and the first interface layer on the first region; forming a second silicon cap layer on the first silicon cap layer in the first region; forming a second interface layer on the second silicon cap layer in the first region; and sequentially forming a high-K dielectric layer and a conductive layer on the second interface layer in the first region and the second region. The application can reduce internal defects in the germanium-silicon layer and the gate oxide layer, thereby improving the performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] In semiconductor device fabrication, a germanium-silicon layer is commonly used as the channel layer. The fabrication process involves forming a silicon capping layer on the germanium-silicon layer, and then directly fabricating the gate oxide layer on the silicon capping layer, for example, using in-situ steam generation (ISSG) to grow the gate oxide layer on the silicon capping layer. However, this silicon capping layer is not very effective at preventing germanium diffusion from the germanium-silicon layer. When germanium diffuses into the gate oxide layer, it forms Ge-O bonds, leading to internal defects in the gate oxide layer. Furthermore, germanium diffusion can also cause internal defects in the channel layer, thus affecting the electrical performance of the device. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and a method for fabricating the same, thereby reducing internal defects in the germanium-silicon layer and the gate oxide layer and improving the performance of the semiconductor device.

[0004] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor device, comprising:

[0005] A substrate is provided, the substrate including a first region and a second region, the substrate including a germanium-silicon layer and a first silicon capping layer stacked from bottom to top;

[0006] A first interface layer and a gate oxide layer are sequentially formed on a first silicon capping layer located in the first region and the second region;

[0007] Remove the gate oxide layer and the first interface layer on the first region;

[0008] A second silicon capping layer is formed on the first silicon capping layer in the first region;

[0009] A second interface layer is formed on the second silicon capping layer located in the first region; and

[0010] A high-k dielectric layer and a conductive layer are sequentially formed on the second interface layer in the first region and on the second region.

[0011] Optionally, the first interface layer is grown under the reaction conditions of trimethylaluminum and ammonia.

[0012] Optionally, before the step of removing the gate oxide layer and the first interface layer on the first region, the method further includes:

[0013] The gate oxide layers on the first region and the second region are nitrided to form a third interface layer on the surface of the gate oxide layers;

[0014] A patterned photoresist layer is formed to cover the second region;

[0015] Remove the third interface layer on the first region.

[0016] Optionally, a passivation process and a rapid thermal oxidation process are performed sequentially to form the second interface layer.

[0017] Optionally, after removing the gate oxide layer and the first interface layer on the first region, the first interface layer is in physical contact with the first silicon capping layer of the second region.

[0018] Optionally, the second silicon capping layer is in physical contact with the first silicon capping layer in the first region.

[0019] Optionally, the high-k dielectric layer is in physical contact with the second interface layer and the third interface layer.

[0020] The present invention also provides a semiconductor device, comprising:

[0021] The substrate includes a first region and a second region;

[0022] A germanium-silicon layer is located on the first region and the second region;

[0023] A first silicon capping layer is located on the germanium-silicon layer;

[0024] The second silicon capping layer is located on the first silicon capping layer in the first region;

[0025] The first interface layer is located on the first silicon capping layer in the second region;

[0026] A gate oxide layer is located on the first interface layer;

[0027] The second interface layer is located on the second silicon capping layer;

[0028] A high-k dielectric layer is located on the second interface layer in the first region and on the second region;

[0029] A conductive layer is located on the high-k dielectric layer.

[0030] Optionally, a third interface layer is also included, located between the gate oxide layer and the high-k dielectric layer of the second region.

[0031] Optionally, the first interface layer is in physical contact with the first silicon capping layer of the second region.

[0032] Optionally, the second silicon capping layer is in physical contact with the first silicon capping layer in the first region.

[0033] Optionally, the high-k dielectric layer is in physical contact with the second interface layer and the third interface layer.

[0034] The semiconductor device and its fabrication method provided by the present invention include: providing a substrate, the substrate comprising a first region and a second region, the substrate comprising a germanium-silicon layer and a first silicon capping layer stacked from bottom to top; sequentially forming a first interface layer and a gate oxide layer on the first silicon capping layer in the first region and the second region; removing the gate oxide layer and the first interface layer in the first region; forming a second silicon capping layer on the first silicon capping layer in the first region; forming a second interface layer on the second silicon capping layer in the first region; and sequentially forming a high-k dielectric layer and a conductive layer on the second interface layer in the first region and the second region. The present invention forms a second silicon capping layer and a second interface layer on the first silicon capping layer in the first region, and a first interface layer on the first silicon capping layer in the second region, both of which help prevent germanium diffusion in the germanium-silicon layer and reduce internal defects in the germanium-silicon layer and the gate oxide layer, thereby improving the performance of the semiconductor device. Attached Figure Description

[0035] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0036] Figures 2-9 This is a cross-sectional schematic diagram of the corresponding steps in a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0037] The attached figures are labeled as follows:

[0038] 10-Substrate; 10A-First region; 10B-Second region; 20-Germanium-silicon layer; 31-First silicon capping layer; 32-Second silicon capping layer; 41-First interface layer; 42-Third interface layer; 43-Second interface layer; 50-Gate oxide layer; 60-Patterned photoresist layer; 70-High-K dielectric layer; 80-Conductive layer. Detailed Implementation

[0039] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0040] Figure 1 This is a flowchart illustrating the fabrication method of the semiconductor device provided in this embodiment. Please refer to it. Figure 1This embodiment provides a method for fabricating a semiconductor device, including:

[0041] Step S1: Provide a substrate, the substrate including a first region and a second region, and the substrate including a germanium-silicon layer and a first silicon capping layer stacked from bottom to top;

[0042] Step S2: Sequentially form a first interface layer and a gate oxide layer on the first silicon capping layer located in the first region and the second region;

[0043] Step S3: Remove the gate oxide layer and the first interface layer on the first region;

[0044] Step S4: Form a second silicon capping layer on the first silicon capping layer located in the first region;

[0045] Step S5: Form the second interface layer on the second silicon capping layer located in the first region;

[0046] Step S6: Sequentially form a high-k dielectric layer and a conductive layer on the second interface layer in the first region and on the second region.

[0047] Figures 2-9 This is a cross-sectional schematic diagram of the corresponding steps in the fabrication method of the semiconductor device provided in this embodiment. The following is in conjunction with... Figures 2-9 The method for fabricating the semiconductor device provided in this embodiment will be described in detail.

[0048] Please refer to Figure 2 Step S1: Provide a substrate 10. The substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, or a fully depleted silicon-on-insulator substrate, and is not limited thereto. The substrate 10 includes a first region 10A and a second region 10B. The first region 10A and the second region 10B may be adjacent or non-adjacent (the first region 10A and the second region 10B are separated in the figure). The first region 10A serves as the core region of the device, and the second region 10B serves as the I / O region of the device. The substrate 10 (first region 10A and second region 10B) includes a germanium-silicon layer 20 and a first silicon capping layer 31 stacked from bottom to top. The germanium-silicon layer 20 serves as the channel layer of the device. If germanium diffuses from the germanium-silicon layer 20 to other film layers (such as the gate oxide layer), it will form internal defects in the germanium-silicon layer 20, that is, internal defects will be formed in the channel layer. Furthermore, diffusion to the gate oxide layer will easily form internal defects in the gate oxide layer. Although the first silicon capping layer 31 plays a role in blocking germanium diffusion, it is difficult for the first silicon capping layer 31 to effectively block the diffusion of germanium in the germanium-silicon layer 20.

[0049] Please refer to Figure 3 and Figure 4Step S2: A first interface layer 41 and a gate oxide layer 50 are sequentially formed on a first silicon capping layer 31 located in the first region 10A and the second region 10B. Specifically, the first interface layer 41 is grown on the first silicon capping layer 31 in the first region 10A and the second region 10B under the reaction conditions of trimethylaluminum (TMA) and ammonia (NH3), wherein trimethylaluminum is used as the aluminum source and ammonia is used as the nitrogen source. The first interface layer 41 can be one or a combination of aluminum nitride, aluminum oxynitride, or aluminum oxide. The first interface layer 41 can effectively prevent germanium diffusion in the germanium silicon layer 20. Then, the gate oxide layer 50 is formed on the first interface layer 41 using an ALD (atomic layer deposition) process. A lower temperature is used in the ALD process because germanium diffuses more easily at high temperatures. Using a lower temperature can suppress germanium diffusion during preparation. The temperature of the ALD process can be 300℃ to 600℃. The gases used in the ALD process include H2, O2, and SAM24 (ethylenediamine), but are not limited to the above-mentioned temperature and gases.

[0050] Step S3: Before the step of removing the gate oxide layer and the first interface layer on the first region, the method further includes: Please refer to Figure 5 The gate oxide layer 50 on the first region 10A and the second region 10B is nitrided to form a third interface layer 42 on the surface of the gate oxide layer 50. The third interface layer 42 is a nitriding layer and may include silicon oxynitride. The gas used for nitriding includes NH3, NO, and N2, but is not limited to the above gases.

[0051] Please refer to Figure 6 A patterned photoresist layer 60 is formed to cover the second region 10B (covering the third interface layer 42 on the second region 10B). Then, using the patterned photoresist layer 60 as a mask, the third interface layer 42 on the first region 10A is etched away; and using the patterned photoresist layer 60 as a mask, the gate oxide layer 50 and the first interface layer 41 on the first region 10A are etched away. After removing the gate oxide layer 50 and the first interface layer 41 on the first region 10A, the first interface layer 41 is only in physical contact with the first silicon capping layer 31 of the second region 10B.

[0052] Please refer to Figure 7 Step S4: Using the patterned photoresist layer 60 as a masking layer, a second silicon capping layer 32 is formed on the first silicon capping layer 31 in the first region 10A, and the second silicon capping layer 32 is in physical contact with the first silicon capping layer 31 in the first region 10A. The second silicon capping layer 32 being on the first silicon capping layer 31 can enhance the effect of blocking germanium diffusion.

[0053] Please refer to Figure 8Step S5: Using the patterned photoresist layer 60 as a masking layer, a second interface layer 43 is formed on the second silicon capping layer 32 located in the first region 10A. Specifically, a passivation process and a rapid thermal oxidation process are sequentially performed to form the second interface layer 43. First, heat treatment is performed in a gas atmosphere of H2, NH3, or N2 to passivate the surface of the second silicon capping layer 32. Heat treatment can repair film defects and improve film quality. The heat treatment temperature can be 850℃~1000℃. Then, rapid thermal oxidation is performed on the surface of the second silicon capping layer 32 to form the second interface layer 43 on the surface of the second silicon capping layer 32. The material of the second interface layer 43 can be silicon and silicon oxide or silicon and silicon oxynitride. Then, the patterned photoresist layer 60 is removed.

[0054] Please refer to Figure 9 Step S6 is executed as follows: a high-k dielectric layer 70 and a conductive layer 80 are sequentially formed on the second interface layer 43 of the first region 10A and the third interface layer 42 of the second region 10B. Specifically, the high-k dielectric layer 70 is first formed on the second interface layer 43 of the first region 10A and the third interface layer 42 of the second region 10B, and the high-k dielectric layer 70 is in physical contact with the second interface layer 43 and the third interface layer 42; then the conductive layer 80 is formed on the high-k dielectric layer 70; wherein, the material of the high-k dielectric layer 70 can be HfSiON, and the material of the conductive layer 80 can be TiN, but is not limited to the above materials.

[0055] In this embodiment, a second silicon capping layer 32 and a second interface layer 43 are formed on the first silicon capping layer 31 in the first region 10A. The second silicon capping layer 32 and the second interface layer 43 can effectively prevent germanium diffusion in the germanium-silicon layer 20 of the first region 10A and reduce internal defects in the germanium-silicon layer 20 of the first region 10A. A first interface layer 41 is formed on the first silicon capping layer 31 in the second region 10B. The first interface layer 41 can effectively prevent germanium diffusion in the germanium-silicon layer 20 of the second region 10B and prevent germanium from diffusing into the gate oxide layer 50 to form Ge-O bonds, thereby reducing internal defects in the germanium-silicon layer 20 and the gate oxide layer 50 in the second region 10B and improving the performance of the semiconductor device. Furthermore, a third interface layer 42 is formed on the gate oxide layer 50 in the second region 10B to protect the gate oxide layer 50.

[0056] Please refer to Figure 9This embodiment also provides a semiconductor device, which is fabricated using the above-described semiconductor device fabrication method, including: a substrate 10, a germanium-silicon layer 20, a first silicon capping layer 31, a second silicon capping layer 32, a first interface layer 41, a gate oxide layer 50, a second interface layer 43, a high-k dielectric layer 70, and a conductive layer 80. The substrate 10 includes a first region 10A and a second region 10B. The first region 10A and the second region 10B may be adjacent or not adjacent (the first region 10A and the second region 10B are separated in the figure). The first region 10A serves as the core region of the device, and the second region 10B serves as the I / O region of the device.

[0057] A germanium-silicon layer 20 is located on the first region 10A and the second region 10B, serving as the channel layer of the device. A first silicon capping layer 31 is located on the germanium-silicon layer 20, and is in physical contact with the germanium-silicon layer 20. A second silicon capping layer 32 is located on the first silicon capping layer 31 in the first region 10A, and is in physical contact with the first silicon capping layer 31 in the first region 10A. A first interface layer 41 is located on the first silicon capping layer 31 in the second region 10B, and is in physical contact with the first silicon capping layer 31 in the second region 10B. A gate oxide layer 50 is located on the first interface layer 41; a second interface layer 43 is located on the second silicon capping layer 32, and is in physical contact with the second silicon capping layer 32. A high-k dielectric layer 70 is located on the second interface layer 43 in the first region 10A and the second region 10B, and a conductive layer 80 is located on the high-k dielectric layer 70.

[0058] Furthermore, the semiconductor device also includes a third interface layer 42, which is located between the gate oxide layer 50 and the high-k dielectric layer 70 of the second region 10B. The high-k dielectric layer 70 is in physical contact with the second interface layer 43 and the third interface layer 42; the materials of the aforementioned partial films are as previously described.

[0059] In summary, the semiconductor device and its fabrication method provided by this invention include: providing a substrate, the substrate comprising a first region and a second region, the substrate comprising a germanium-silicon layer and a first silicon capping layer stacked from bottom to top; sequentially forming a first interface layer and a gate oxide layer on the first silicon capping layer in the first region and the second region; removing the gate oxide layer and the first interface layer in the first region; forming a second silicon capping layer on the first silicon capping layer in the first region; forming a second interface layer on the second silicon capping layer in the first region; and sequentially forming a high-k dielectric layer and a conductive layer on the second interface layer in the first region and the second region. The present invention forms a second silicon capping layer and a second interface layer on the first silicon capping layer in the first region, and a first interface layer on the first silicon capping layer in the second region, both of which are beneficial for preventing germanium diffusion in the germanium-silicon layer and reducing internal defects in the germanium-silicon layer and the gate oxide layer, thereby improving the performance of the semiconductor device.

[0060] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a first region and a second region, the substrate including a germanium-silicon layer and a first silicon capping layer stacked from bottom to top; A first interface layer and a gate oxide layer are sequentially formed on a first silicon capping layer located in the first region and the second region; Remove the gate oxide layer and the first interface layer on the first region; A second silicon capping layer is formed on the first silicon capping layer in the first region; A second interface layer is formed on the second silicon capping layer located in the first region; as well as, A high-k dielectric layer and a conductive layer are sequentially formed on the second interface layer in the first region and on the second region.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The first interface layer is formed under the reaction conditions of trimethylaluminum and ammonia.

3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, Prior to the step of removing the gate oxide layer and the first interface layer on the first region, the method further includes: The gate oxide layers on the first region and the second region are nitrided to form a third interface layer on the surface of the gate oxide layers; A patterned photoresist layer is formed to cover the second region; Remove the third interface layer on the first region.

4. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The second interface layer is formed by sequentially performing a passivation process and a rapid thermal oxidation process.

5. The method for fabricating a semiconductor device as described in claim 1, characterized in that, After removing the gate oxide layer and the first interface layer on the first region, the first interface layer is in physical contact with the first silicon capping layer of the second region.

6. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The second silicon capping layer is in physical contact with the first silicon capping layer in the first region.

7. The method for fabricating a semiconductor device as described in claim 3, characterized in that, The high-K dielectric layer is in physical contact with the second interface layer and the third interface layer.

8. A semiconductor device, characterized in that, include: The substrate includes a first region and a second region; A germanium-silicon layer is located on the first region and the second region; A first silicon capping layer is located on the germanium-silicon layer; The second silicon capping layer is located on the first silicon capping layer in the first region; The first interface layer is located on the first silicon capping layer in the second region; A gate oxide layer is located on the first interface layer; The second interface layer is located on the second silicon capping layer; A high-k dielectric layer is located on the second interface layer in the first region and on the second region; A conductive layer is located on the high-k dielectric layer.

9. The semiconductor device as claimed in claim 8, characterized in that, It also includes a third interface layer located between the gate oxide layer and the high-k dielectric layer of the second region.

10. The semiconductor device as claimed in claim 8, characterized in that, The first interface layer is in physical contact with the first silicon capping layer of the second region.

11. The semiconductor device as claimed in claim 8, characterized in that, The second silicon capping layer is in physical contact with the first silicon capping layer in the first region.

12. The semiconductor device as claimed in claim 9, characterized in that, The high-K dielectric layer is in physical contact with the second interface layer and the third interface layer.

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