A semiconductor device and its manufacturing method

Abstract

This disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes an epitaxial layer formed on a semiconductor substrate, a junction field-effect transistor (JFET), and a switching transistor. The JFET is disposed in the epitaxial layer and includes a first source region, a first gate region, a first drain region, and a shielding region. The shielding region is disposed in the epitaxial layer and located between the first gate region and the semiconductor substrate. The switching transistor is disposed in the epitaxial layer and includes a second source region, a second drain region, and a second gate region. The shielding region is electrically connected to the second drain region, and the second source region is electrically connected to the first source region. The first gate region and the second gate region are configured to be controlled by the same gate signal.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Wide-bandgap semiconductor materials such as silicon carbide (SiC) are widely used in the manufacture of high-voltage, high-temperature, and high-frequency power devices due to their excellent physical properties, such as high breakdown field strength, high thermal conductivity, and high saturated electron drift velocity. Among them, the silicon carbide junction field-effect transistor (SiC JFET), as an important power switching device, has advantages such as low on-resistance and fast switching speed, and shows great application potential in electric vehicles, industrial power supplies, and renewable energy fields.

[0003] In traditional vertical SiC JFET designs, a shielding region is typically introduced below the P-type gate region to improve the device's turn-off breakdown voltage. This shielding region depletes the drift region below it when the device is in the turn-off state, thereby protecting the gate region from the effects of high drain voltage, preventing avalanche breakdown in the gate region, and effectively improving the device's breakdown voltage.

[0004] However, the introduction of this shielding region also introduces an inherent design contradiction. To achieve a strong shielding effect for high breakdown voltage, the doping concentration and size of the shielding region need to reach a certain level. But this also enhances the electric field effect of the shielding region on the JFET channel region. Even when the device is turned on, the depletion layer formed by the shielding region will compress the conductive channel to some extent, thereby increasing the on-resistance (Ron) of the device. The increase in on-resistance leads to more power loss and heat generation during device operation, reducing the energy efficiency of the system. Therefore, existing technologies have to make trade-offs and compromises between high breakdown voltage and low on-resistance, making it difficult to simultaneously optimize both performance characteristics, which limits further improvement in the overall performance of SiC JFET devices. Summary of the Invention

[0005] This disclosure provides a semiconductor device and a method for manufacturing the same, aiming to solve the technical problem that it is difficult to balance the on-resistance and breakdown voltage of JFET devices in the prior art.

[0006] The technical solution disclosed herein is implemented as follows:

[0007] In a first aspect, this disclosure provides a semiconductor device. The semiconductor device includes: an epitaxial layer formed on a semiconductor substrate; a junction field-effect transistor (JFET) disposed in the epitaxial layer, the JFET including a first source region, a first gate region, a first drain region, and a shielding region, the shielding region being disposed in the epitaxial layer and located between the first gate region and the semiconductor substrate; and a switching transistor including a second source region, a second drain region, and a second gate region. The shielding region is electrically connected to the second drain region, the second source region is electrically connected to the first source region, and the first gate region and the second gate region are configured to be controlled by the same gate signal.

[0008] In a second aspect, this disclosure provides a method for manufacturing a semiconductor device, the method comprising: forming an epitaxial layer of a first conductivity type on a semiconductor substrate of a first conductivity type; forming a first gate region of a second conductivity type and a shield region of a second conductivity type in the epitaxial layer, the shield region being located between the first gate region and the semiconductor substrate; forming a first source region of the first conductivity type in the epitaxial layer; forming a second source region of the second conductivity type and a second drain region of the second conductivity type for constituting a switching transistor in the epitaxial layer; forming a second gate region for controlling the switching transistor; and forming an electrical connection such that the shield region is electrically connected to the second drain region, the second source region is electrically connected to the first source region, and the first gate region and the second gate region can be controlled by the same gate signal.

[0009] This disclosure provides a semiconductor device and its manufacturing method. A dynamic shielding function is achieved by integrating a junction field-effect transistor (JFET) and a switching transistor (e.g., a PMOS) within the same cell and cleverly designing their internal electrical connections. Specifically, the potential of the shielding region is no longer statically fixed at the source potential, but is dynamically switched by the on / off state of the switching transistor. When a turn-off signal is applied (e.g., a negative gate voltage for a normally open JFET), the signal pinches off the JFET channel and turns on the switching transistor. The switching transistor electrically connects the shielding region to the source region, placing the shielding region at a defined source potential (e.g., zero potential). At this time, the shielding region performs at its maximum efficiency, effectively shielding the JFET gate from the high-voltage drain, reshaping the electric field distribution, and thus significantly improving the device's breakdown voltage. When a turn-on signal is applied (e.g., zero gate voltage for a normally open JFET), the signal opens the JFET channel, allowing current to flow, and turns off the switching transistor. The cutoff of the switching transistor disconnects the connection between the shielded region and the source region, placing the shielded region in an electrically floating state. The floating shielded region no longer exerts a strong squeezing effect on the conductive channel, and its potential adaptively adjusts with the surrounding electric field, thereby significantly widening the effective cross-sectional area for current flow and substantially reducing the device's on-resistance. This dynamic potential switching mechanism, achieved through the device's static structure, resolves the inherent contradiction between shielding strength and on-resistance in traditional static shielding structures. The semiconductor device disclosed herein achieves high withstand voltage characteristics due to strong shielding during turn-off, while simultaneously enjoying low on-resistance due to the lack of shielding constraints during turn-on, thus improving the overall performance of the device. Attached Figure Description

[0010] Figure 1 This is a schematic cross-sectional view of a semiconductor device provided in this disclosure.

[0011] Figure 2 This is a schematic cross-sectional view of another semiconductor device provided in this disclosure.

[0012] Figure 3 This is a schematic cross-sectional view of a semiconductor device with an added drain metal layer, as provided in this disclosure.

[0013] Figure 4 A flowchart of a method for manufacturing a semiconductor device provided in this disclosure.

[0014] Figure 5 This is a schematic diagram of a cross-sectional structure for forming an epitaxial layer, as provided in this disclosure.

[0015] Figure 6 This is a schematic diagram of a cross-sectional structure for forming a P+ region, as provided in this disclosure.

[0016] Figure 7 This is a schematic diagram of a cross-sectional structure for forming an N+ region, as provided in this disclosure.

[0017] Figure 8 This is a schematic diagram of a cross-sectional structure for forming a groove, as provided in this disclosure.

[0018] Figure 9 This is a schematic cross-sectional structure diagram of a second gate region provided in this disclosure.

[0019] Figure 10 This is a schematic cross-sectional view of a gate electrode provided in this disclosure.

[0020] Figure 11 This is a schematic diagram of a cross-sectional structure for forming a source metal layer, as provided in this disclosure.

[0021] Figure 12 A flowchart of another method for manufacturing a semiconductor device provided in this disclosure.

[0022] Figure 13 This is a schematic cross-sectional view of a planar gate semiconductor device provided in this disclosure.

[0023] Figure 14 This is a schematic cross-sectional view of another planar gate semiconductor device provided in this disclosure.

[0024] List of reference numerals in the attached diagram:

[0025] 1. Substrate; 2. Epitaxial layer; 21. Junction field-effect transistor; 211. First source region; 212. First gate region; 213. Shielding region; 214. First drain region; 215. Gate metal layer; 216. Source metal layer; 217. Drain metal layer; 22. Switching transistor; 221. Second source region; 222. Second drain region; 223. Second gate region; 224. Body region; 2231. Gate dielectric layer; 2232. Polysilicon. Detailed Implementation

[0026] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of the embodiments of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0028] The terms “having,” “comprising,” “including,” and “containing” are open-ended and indicate the presence of the stated structure, element, or feature but do not exclude the presence of additional elements or features. The quantifiers and pronouns “a,” “one,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0029] Before describing specific embodiments in detail, some basic concepts and terms used in this disclosure are first explained. The figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a lower doping concentration than the "n" doped region, while an "n+" doped region has a higher doping concentration than the "n" doped region. Doped regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doped regions can have the same or different absolute doping concentrations. Two adjacent doped regions with the same conductivity type but different dopant concentrations form a unipolar junction, for example, an n / n+ or p / p+ junction along the boundary surface between the two doped regions. At the unipolar junction, the dopant concentration profile orthogonal to the unipolar junction can show steps or inflection points, where the dopant concentration profile changes from concave to convex, or vice versa.

[0030] The main components of a layer or structure derived from a chemical compound or alloy are elements whose atoms form the chemical compound or alloy. For example, nickel and silicon are the main components of nickel silicide layers, and copper and aluminum are the main components of copper-aluminum alloys.

[0031] The embodiments of this disclosure preferably employ wide-bandgap semiconductor materials, particularly silicon carbide (SiC). Silicon carbide exists in various polytypes, such as 4H-SiC, 6H-SiC, and 3C-SiC. For vertical power devices, the 4H-SiC polytype is generally preferred due to its higher electron mobility and isotropy. Although the description in this disclosure primarily uses SiC as an example, those skilled in the art will understand that the device structures and operating principles disclosed herein can also be applied to other semiconductor material systems, such as silicon (Si), gallium nitride, and gallium oxide, and these should all be considered within the scope of this disclosure.

[0032] Semiconductor materials have their conductivity altered by incorporating specific impurity atoms (doping). Incorporating donor impurities (such as nitrogen (N) or phosphorus (P) into SiC) forms N-type semiconductors, where electrons are the majority carriers. Incorporating acceptor impurities (such as aluminum (Al) or boron (B) into SiC) forms P-type semiconductors, where holes are the majority carriers. Based on the doping concentration, doping can be categorized as heavily doped (denoted by n+ or p+) and lightly doped (denoted by n- or p-).

[0033] A PN junction is the interface between a P-type semiconductor and an N-type semiconductor. When no external bias voltage is applied, a space charge region without free charge carriers, known as the depletion region, is formed near the interface due to carrier diffusion, generating a built-in electric field and a built-in potential.

[0034] The breakdown voltage (BV) is the maximum reverse voltage that a PN junction can withstand when the reverse bias voltage increases to a certain value. This results in an extremely strong electric field within the junction, triggering an avalanche multiplication effect and causing a sharp increase in reverse current. This phenomenon is called avalanche breakdown.

[0035] In a field-effect transistor, the channel is the conductive region between the source and drain that is controlled by the gate voltage.

[0036] The pinch-off voltage is the gate-source voltage required to completely shut down (pinch off) the channel for a depletion-type (normally open) JFET.

[0037] On-resistance is the total resistance between the drain and source of a transistor when it is in the on-state, and it is a key parameter for measuring the conduction loss of a device.

[0038] A unit cell is a power semiconductor device typically composed of thousands of identical tiny device units (cells) connected in parallel to achieve high current handling capabilities. The description in this disclosure will focus primarily on the structure and operating principle of a single unit cell; it should be understood that the entire device is composed of a large number of such units arranged in repeating patterns.

[0039] With the increasing global demands for energy efficiency and power density, power electronics technology is playing an increasingly important role in key areas such as new energy vehicles, renewable energy grid connection, industrial motor drives, and data center power supplies. Traditional silicon (Si)-based power semiconductor devices, such as power MOSFETs and insulated-gate bipolar transistors (IGBTs), are gradually approaching their theoretical limits in terms of voltage withstand capability, switching speed, and high-temperature performance due to the inherent physical properties of their materials. This makes it difficult to meet the higher performance requirements of next-generation power electronic systems.

[0040] To overcome the limitations of silicon-based devices, wide-bandgap (WBG) semiconductor materials, such as silicon carbide (SiC) and gallium nitride (GaN), have emerged. Compared to silicon, silicon carbide has nearly three times the bandgap, approximately ten times the critical breakdown field strength, twice the electron saturation drift velocity, and three times the thermal conductivity. These superior physical properties enable SiC power devices to operate at higher voltages, higher frequencies, and higher temperatures, while exhibiting lower conduction and switching losses. Therefore, SiC power devices are considered a revolutionary technology in the field of power electronics.

[0041] Among various SiC power transistors, SiC JFETs, due to their unique channel structure, do not suffer from gate oxide reliability issues and can achieve extremely low specific on-resistance, demonstrating great potential in high current density applications. However, traditional SiC JFET designs face an inherent and difficult-to-reconcile contradiction: the constraint between on-resistance and breakdown voltage.

[0042] To achieve high breakdown voltage, power devices typically require a thick, lightly doped drift region to withstand high voltages. However, such a drift region significantly increases the device's on-resistance, leading to greater conduction losses. Conversely, to reduce on-resistance, the thickness of the drift region needs to be reduced or its doping concentration increased, but this sacrifices the device's breakdown voltage. Furthermore, in the off-state, the electric field concentrates in regions such as the corners of the JFET gate, forming electric field spikes. This electric field concentration effect can prematurely trigger avalanche breakdown, causing the actual breakdown voltage of the device to be far below the theoretical limit that the material itself can support.

[0043] To mitigate the electric field concentration problem at the gate corner, a shielding structure has been proposed in the prior art. This technique typically involves placing an additional shielding region below the main gate of the JFET. This shielding region is connected to a fixed reference potential, such as the source potential (ground), during device operation. When the device is turned off, this grounded shielding region effectively depletes the surrounding drift region, reshaping the electric field distribution and transferring the electric field peak from the vulnerable gate region to the inside of the device, thereby significantly improving the device's breakdown voltage.

[0044] However, while this static shielding structure performs excellently in the off state, it introduces new problems in the on state. Because the shielding region is always connected to the source, it still depletes the conductive channel of the JFFET even when the device is on, narrowing the effective conductive channel and obstructing the current path. This effect is equivalent to adding an additional resistor in series with the current path, significantly increasing the overall on-resistance of the device and weakening the inherent advantage of low on-resistance in SiC JFETs. Therefore, the shielding structures in existing technologies sacrifice conduction performance for improved breakdown voltage, leaving the contradiction between "shielding strength" and "on-resistance" unresolved, failing to fundamentally solve the core challenges in power device design.

[0045] The semiconductor device disclosed in this disclosure is a power switching device that can be widely used in various high-voltage, high-frequency power electronic systems. These systems include, but are not limited to: motor drivers, on-board chargers (OBCs), and DC-DC converters in electric vehicles; inverters in solar and wind power generation systems; high-efficiency power supplies used in data centers, communication base stations, and servers; and motor control and power modules in industrial automation equipment. The device in this disclosure can significantly improve the energy conversion efficiency, power density, and reliability of these systems.

[0046] Please see Figure 1 The diagram illustrates a cross-sectional structure of a semiconductor device cell according to an embodiment of this disclosure. In this embodiment, the semiconductor device is an N-channel normally-off or normally-on SiC JFET, but for ease of description, the following description primarily uses an N-channel device as an example. Those skilled in the art will understand that by reversing the conductivity type of each region, a P-channel device protected by this disclosure can also be constructed.

[0047] like Figure 1 As shown, the semiconductor device is constructed on a semiconductor substrate 1. In some examples, the semiconductor substrate 1 is a heavily doped silicon carbide substrate 1 of a first conductivity type (e.g., N-type), specifically a 4H-SiC or 6H-SiC single crystal substrate 1. The purpose of heavy doping (n+) is to reduce the resistivity of the substrate 1, providing a low-resistivity drain (D) contact for the device.

[0048] An epitaxial layer 2 is formed on a semiconductor substrate 1 using epitaxial growth technology. Epitaxial layer 2 is a lightly doped layer (n-) of the first conductivity type (e.g., N-type), which constitutes the drift region of the device. The thickness and doping concentration of the drift region are key parameters that determine the device's breakdown voltage and on-resistance. Its design requires trade-offs based on the target breakdown voltage level.

[0049] Within the epitaxial layer 2, the core structure of the JFET and the key control structure of this disclosure are formed. These structures are typically formed by ion implantation and subsequent high-temperature activation annealing processes. Within this cellular structure, two core transistors are integrated: a junction field-effect transistor 21 (JFET) for main switching and a switching transistor 22 for controlling the potential of the shielding region 213.

[0050] The structure of the junction field-effect transistor 21 (JFET) mainly includes a first gate region 212 and a first source region 211.

[0051] The first gate region 212 is a heavily doped region (p+) of the second conductivity type (e.g., P-type), extending downwards from the top surface of the epitaxial layer 2 to a certain depth. Multiple first gate regions 212 are typically arranged in a strip or honeycomb pattern on the device plane, and the n-epiaxial layer 2 regions between them constitute the conductive channel of the JFET. The first gate regions 212 form a PN junction with the channel, and the depletion region generated by the reverse bias of this PN junction controls the turning on and off of the channel.

[0052] The first source region 211 is a heavily doped region (n+) of the first conductivity type (e.g., N-type). It is formed on the top surface of the epitaxial layer 2 between the first gate regions 212 to form a low-resistance ohmic contact and serve as the source (S) of the JFET.

[0053] The first drain region 214 includes the semiconductor substrate 1 and a portion of the epitaxial layer 2 above it.

[0054] The shielding region 213 is a heavily doped region (p+) of a second conductivity type (e.g., P-type), which is located below the first gate region 212 and is physically and electrically isolated from it. The function of the shielding region 213 is not to directly control the channel, but to modulate the electric field of the drift region when the device is turned off.

[0055] In this embodiment, the switching transistor 22 is a PMOS transistor, which is integrated inside or near the JFET cell. The PMOS transistor includes a second source region 221, a second drain region 222, a body region 224, and a second gate region 223.

[0056] The second source region 221 and the second drain region 222 are both heavily doped regions (p+) of the second conductivity type (e.g., P-type).

[0057] Body region 224 is an injection well of a first conductivity type (e.g., N-type), and the conductive channel of the PMOS is formed on the surface of body region 224.

[0058] In this embodiment, the second gate region 223 is a trench gate structure, which includes a trench formed in the epitaxial layer 2, a gate dielectric layer (e.g., gate oxide layer) formed on the inner wall of the trench, and a conductive material (e.g., doped polysilicon 2232) filling the trench.

[0059] In some examples, the first gate region 212 and the second gate region 223 of the PMOS are interconnected through the same gate metal layer 215 above them and share the same gate drive signal. The first source region 211 and the second source region 221 are interconnected through the same source metal layer 216 above them and share the same source terminal.

[0060] Reference Figure 2 The second drain region 222 and the shielding region 213 are directly connected inside the semiconductor device, or connected through a deep p+ injection region. This allows the potential of the shielding region 213 to be controlled by the turn-on and turn-off of the PMOS. The top of the device may also include an interlayer dielectric layer for electrical isolation. (See reference...) Figure 3 A back metal layer 217 is formed on the back side of the device.

[0061] Please see Figure 4 The flowchart illustrates a semiconductor device manufacturing method provided in this disclosure. The flowchart outlines the manufacturing process... Figures 1 to 3 The main steps of the semiconductor device shown are illustrated below. Figures 5 to 11 Each step is explained in detail.

[0062] Step S401: Provide a substrate and perform epitaxial growth. For example... Figure 5 As shown, the method begins by providing a silicon carbide semiconductor substrate 1 of a first conductivity type (e.g., n+ type). Next, a lightly doped silicon carbide epitaxial layer 2 of the first conductivity type (e.g., n- type) is grown on the semiconductor substrate 1 using epitaxial growth techniques such as chemical vapor deposition (CVD). The quality, thickness uniformity, and doping concentration control of the epitaxial layer 2 are crucial to the performance of the final device.

[0063] Step S402: Form the P-type injection region. For example... Figure 6As shown, a photomask is used to define all regions where p+ type implantation is required. One or more ion implantations are performed under the protection of the photoresist as a mask. The implanted ions are p-type dopants, such as aluminum (Al) or boron (B). By controlling the implantation energy and dose, the first gate region 212, shield region 213, second drain region 222 of the switching transistor 22, and second source region 221 of the switching transistor 22 can be formed simultaneously. For example, multiple aluminum ion implantations at different energies can be used to form a "box-shaped" profile with a specific depth and doping distribution, ensuring good conductivity and junction characteristics in these regions. Integrating these regions, which would otherwise require different steps, into a single photolithography and implantation process greatly simplifies the process and reduces manufacturing costs.

[0064] Step S403: Form the N-type injection region. For example... Figure 7 As shown, a photomask is used to define the regions where n+ and n-type implantation needs to be formed. Then, ion implantation of an N-type dopant (such as nitrogen (N) or phosphorus (P)) is performed. This step can form the first source region 211 of the JFET (n+ type, for ohmic contacts) and the body region 224 of the switching transistor 22 (n-type, as the body region 224 of the PMOS). Similarly, the electrical characteristics of these regions can be optimized by controlling the implantation energy and dose.

[0065] Step S404: High-Temperature Activation Annealing. Ion implantation inserts impurity atoms into the crystal lattice, but these atoms are not in electrically activated replacement sites after implantation, and the implantation process damages the lattice. Therefore, high-temperature annealing is necessary to repair lattice damage and activate the dopant. For SiC, this can be performed at extremely high temperatures exceeding 1600°C in an inert atmosphere (such as argon). To prevent SiC surface decomposition during annealing, a protective carbon film is typically applied to both sides of the wafer. After annealing, the carbon film is removed.

[0066] Step S405: Trench etching. For example... Figure 8 As shown, a third photomask is used to define the location of the PMOS gate trench. Then, dry etching techniques such as inductively coupled plasma (ICP) or reactive ion etching (RIE) are used to etch trenches with specific depths and sidewalls in SiC.

[0067] Step S406: Form the gate dielectric layer and the polysilicon gate. (e.g.) Figure 9As shown, after trench etching is completed, a high-quality silicon dioxide (SiO2) layer is first grown on the inner wall of the trench and the device surface as a gate dielectric layer 2231 using a high-temperature thermal oxidation process. Then, a layer of doped polysilicon 2232 is deposited to fill the entire trench using methods such as low-pressure chemical vapor deposition (LPCVD). Next, the polysilicon 2232 on the wafer surface is removed using chemical mechanical polishing (CMP) or dry etching retreat processes, leaving only the portion inside the trench, thereby forming the second gate region 223 composed of conductive material.

[0068] Step S407: Interlayer dielectric deposition and contact hole formation. First, an interlayer dielectric layer is deposited across the entire wafer surface, for example, silicon dioxide or silicon nitride deposited by plasma-enhanced chemical vapor deposition (PECVD). This dielectric layer is used to isolate subsequent metal interconnects. Then, the locations of the contact holes are defined using a fourth photomask, and contact holes leading to the first source region 211, the first gate region 212, the second source region 221, and the second gate region 223 are opened in the dielectric layer by an etching process.

[0069] Step S408: Front-side metallization. (e.g.) Figure 10 and Figure 11 Metals, such as titanium / nickel (Ti / Ni) stacks or aluminum (Al), are deposited on the front side of the wafer using physical vapor deposition (PVD, such as sputtering or evaporation). Then, the metal layers are patterned using a fifth photomask to form separate source metal layers 216 and gate metal layers 215. Source metal layer 216 simultaneously connects the first source region 211 and the second source region 221. Gate metal layer 215 simultaneously connects the first gate region 212 and the second gate region 223. After metal patterning, a rapid thermal annealing (RTA) process is typically performed to create a low-resistivity ohmic contact between the metal and SiC.

[0070] Step S409: Backside processing. (e.g.) Figure 3 As shown, after the front-side process is completed, the back-side of the wafer is processed. First, the semiconductor substrate 1 is thinned to the target thickness (e.g., 100-200 micrometers) by mechanical grinding and chemical polishing to reduce the on-resistance and thermal resistance of the device. Then, a metal (e.g., nickel, Ni) is deposited on the thinned back-side and subjected to high-temperature annealing to form ohmic contacts. Finally, a layer of metal (e.g., silver, Ag) for soldering is deposited to form the final back-side metal, which serves as the drain metal layer 217 of the device.

[0071] In some examples, refer to Figure 12 The method for manufacturing a semiconductor device disclosed herein may include steps S1210 to S1260.

[0072] In step S1210, an epitaxial layer of the first conductivity type is formed on a semiconductor substrate of the first conductivity type.

[0073] In step S1220, a first gate region of a second conductivity type and a shielding region of a second conductivity type are formed in the epitaxial layer, with the shielding region located between the first gate region and the semiconductor substrate.

[0074] In step S1230, a first source region of a first conductivity type is formed in the epitaxial layer.

[0075] In step S1240, a second source region and a second drain region for constituting a second conductivity type of a switching transistor are formed in the epitaxial layer.

[0076] In step S1250, a second gate region for controlling the switching transistor is formed.

[0077] In step S1260, an electrical connection is formed.

[0078] It should be noted that the specific steps of steps S1210 to S1260 can be referred to steps S401 to S409, and will not be repeated here.

[0079] The dynamic shielding concept presented in this disclosure is not limited to the specific structure shown in one embodiment. To further broaden the scope of protection and demonstrate the flexibility of the invention, this embodiment will introduce some alternative device structures.

[0080] Please see Figure 13 and Figure 14 This embodiment illustrates a semiconductor device structure using a planar PMOS as the switching transistor 22. Unlike trench-gate PMOS, this PMOS is a laterally conductive planar device. Its second gate region 223 includes a gate dielectric layer formed on the surface of the epitaxial layer 2, and a conductive material formed on the gate dielectric layer. Its manufacturing process eliminates the need for trench etching and filling steps. The gate of the PMOS, i.e., the second gate region 223, can be polysilicon 2232 or a P+ injection gate formed simultaneously with the first gate region 212. Although the area efficiency of planar PMOS may be lower than that of trench PMOS, its simplified process advantage may be more prominent in certain applications. This embodiment demonstrates that the specific structural form of the switching transistor 22 (trench type, planar type, etc.) is not a limiting feature of this invention. Any transistor structure that can be effectively controlled by the JFET gate voltage and connect the shielding region 213 to the source falls within the protection scope of this disclosure.

[0081] It should be noted that, Figure 13 and Figure 14 Shielding area 213 in the diagram shows the shielding area of ​​the JFET and PMOS connection region. The shielding areas of other regions can be configured as follows: Figure 1 The shielding region 213 is configured so that the JFET and PMOS are connected through the shielding region while ensuring that the JFET can be turned on.

[0082] The switching PMOS is integrated within each cell that includes a JFET. This is a high-performance implementation because it ensures the shortest connection path between the shielding region 213 and the PMOS, minimizing parasitic resistance and inductance, thus enabling the fastest shielding potential switching. However, in other examples, a peripheral integration layout strategy can be used. That is, instead of fabricating a PMOS in each cell, a single switching PMOS is shared across multiple cells, creating one or more larger PMOS units. Then, the second drain region 222 of this peripheral PMOS is connected to the shielding region 213 of all cells including JFET units within the chip via a buried p+ connection layer. The advantage of this layout is that it saves active area on the chip, increases the JFET density, and thus achieves lower on-resistance within the same chip area.

[0083] Although this disclosure describes 4H-SiC as an example in detail, the method of dynamically adaptively adjusting the shielding potential using the integrated switching transistor 22 is also applicable to other semiconductor materials. For example, this structure can be applied to other SiC polymorphic materials such as 6H-SiC, as well as other wide-bandgap semiconductor materials such as gallium nitride (GaN) and diamond. Furthermore, the conductivity type of the device can be completely reversed, i.e., a complementary structure of P-channel JFETs and NMOS switching transistors can be fabricated on a P-type substrate and a p-epitaxial layer. Regarding the doping profile, in addition to simple uniform doping, other techniques can be combined, such as introducing a super-junction structure or charge compensation structure in the drift region, in conjunction with the dynamic shielding technology of this disclosure to further optimize the device performance.

[0084] This disclosure provides an innovative semiconductor device and its manufacturing method. By integrating a switching transistor 22 controlled by the same gate signal within a JFET cell, dynamic control of the potential of the under-gate shielding region 213 is achieved. This "dynamic shielding" mechanism enables the device to obtain a high breakdown voltage due to strong shielding when turned off, and to enjoy extremely low on-resistance due to the floating shielding layer when turned on, thus fundamentally solving the performance bottleneck inherent in the static shielding structure of the prior art.

[0085] Furthermore, this disclosure also provides a computer-readable storage medium having a computer program stored thereon. The computer program is configured, when executed by a processor, to control a semiconductor manufacturing apparatus (such as a lithography machine, ion implanter, etching machine, CVD equipment, etc.) to perform all or part of the steps in a semiconductor device manufacturing method. The storage medium can be any electronic, magnetic, optical, or other physical device capable of storing program code, such as a read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or optical disk.

[0086] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0087] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention applied herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not claimed herein.

[0088] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Epitaxial layer formed on semiconductor substrate; A junction field-effect transistor (JFET) is disposed in the epitaxial layer and includes a first source region, a first gate region, a first drain region, and a shielding region. The shielding region is disposed in the epitaxial layer and located between the first gate region and the semiconductor substrate. A switching transistor is disposed in the epitaxial layer, and the switching transistor includes a second source region, a second drain region, and a second gate region; The shielding region is electrically connected to the second drain region, the second source region is electrically connected to the first source region, and the first gate region and the second gate region are configured to be controlled by the same gate signal.

2. The semiconductor device according to claim 1, characterized in that, The epitaxial layer is of a first conductivity type; the first source region is of the first conductivity type; the first gate region and the shielding region are of a second conductivity type opposite to the first conductivity type.

3. The semiconductor device according to claim 2, characterized in that, The switching transistor is a P-channel metal-oxide-semiconductor field-effect transistor, with the first conductivity type being N-type and the second conductivity type being P-type.

4. The semiconductor device according to claim 3, characterized in that, The second gate region includes: a trench formed in the epitaxial layer, a gate dielectric layer formed on the inner wall of the trench, and a conductive material filling the trench.

5. The semiconductor device according to claim 3, characterized in that, The second gate region includes: a gate dielectric layer formed on the surface of the epitaxial layer, and a conductive material formed on the gate dielectric layer.

6. The semiconductor device according to claim 3, characterized in that, The switching transistor further includes a body region having a first conductivity type formed within the epitaxial layer, and the second source region and the second drain region are formed within the body region.

7. The semiconductor device according to claim 1, characterized in that, The first drain region includes the semiconductor substrate, and the junction field-effect transistor is configured to allow current to flow between the first source region and the first drain region in a direction perpendicular to the surface of the semiconductor substrate when it is in the on state.

8. The semiconductor device according to claim 1, characterized in that, There are multiple first gate regions, and the first source region is located between the multiple first gate regions.

9. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a plurality of junction field-effect transistors, and the switching transistor is located between the plurality of junction field-effect transistors.

10. A method for manufacturing a semiconductor device, characterized in that, include: An epitaxial layer of a first conductivity type is formed on a semiconductor substrate of a first conductivity type; A first gate region of a second conductivity type and a shielding region of a second conductivity type are formed in the epitaxial layer, the shielding region being located between the first gate region and the semiconductor substrate; A first source region of a first conductivity type is formed in the epitaxial layer; A second source region and a second drain region of a second conductivity type for constituting a switching transistor are formed in the epitaxial layer; A second gate region is formed for controlling the switching transistor; as well as An electrical connection is formed such that the shielding region is electrically connected to the second drain region, the second source region is electrically connected to the first source region, and the first gate region and the second gate region can be controlled by the same gate signal.

11. The method according to claim 10, characterized in that, The steps of forming the first gate region, the shielding region, the second source region, and the second drain region include: The first gate region, the shielding region, the second source region, and the second drain region are formed by ion implantation.

12. The method according to claim 11, characterized in that, The steps of forming the first gate region, the shielding region, the second source region, and the second drain region include: The first gate region, the shielding region, the second source region, and the second drain region are formed in the epitaxial layer using an ion implantation process and a mask.

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