Fast zero-crossing detection circuit and fast zero-crossing detection method
By using a fast zero-crossing detection circuit, a sampling detection circuit, a differential amplifier component, and a Schmitt trigger to achieve fast zero-crossing signal detection, the problem of switching transistor breakdown risk in DC-DC synchronous buck converter is solved, improving the circuit's safety and conversion efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHERY AUTOMOBILE CO LTD
- Filing Date
- 2025-10-31
- Publication Date
- 2026-08-04
AI Technical Summary
In the existing technology, the zero-crossing detection circuit in the DC-DC synchronous buck converter is too slow, which leads to the risk of the switching transistor being broken down, and the inductor current becomes negative, resulting in wasted capacitor energy and abnormally high inductor node voltage.
A fast zero-crossing detection circuit is adopted, including a sampling detection circuit, a differential amplifier component, a comparator component, and a Schmitt trigger. By acquiring the voltage of the switch output node and the power ground node, a high-gain differential amplifier and a fast comparator are used to realize fast zero-crossing signal detection, and the Schmitt trigger outputs the zero-crossing detection result.
This improves the response speed of zero-crossing detection, avoids the risk of the switching transistor being damaged, and enhances the safety and switching efficiency of circuit components.
Smart Images
Figure CN121253894B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of circuit technology, and in particular to a fast zero-crossing detection circuit and a fast zero-crossing detection method. Background Technology
[0002] Power management chips play a crucial role in power supply, and DC-DC buck conversion is an important component of them. Compared to asynchronous buck conversion, synchronous buck conversion is more complex to control, but it is more efficient. Therefore, synchronous buck conversion is more widely used in consumer electronics where low power consumption and high efficiency are emphasized. In related technologies, in DC-DC synchronous buck converters for power supply, under light load discontinuous mode, a zero-crossing detection circuit is often required to control the lower switch to turn off in time during freewheeling to avoid the generation of negative inductor current, which could lead to abnormally high node voltage of SW and risk of the lower switch being broken down by high voltage.
[0003] However, in the existing technology, if there is no zero-crossing detection or the zero-crossing detection is too slow, the inductor current will be negative. That is, after the inductor has released all its stored energy, the capacitor will release its stored energy in the opposite direction, which will cause the inductor to have a negative current. This not only wastes the energy stored in the capacitor, but also causes the voltage of the SW node to be charged too high, which will put the switching transistor at risk of breakdown. This problem urgently needs to be solved. Summary of the Invention
[0004] This invention provides a fast zero-crossing detection circuit and a fast zero-crossing detection method to solve the problem that the switching transistor is at risk of being damaged due to the slow detection speed of the zero-crossing detection circuit in the related technology, thereby improving the safety of circuit components and the response speed of the zero-crossing detection circuit.
[0005] To achieve the above objectives, a first aspect of the present invention provides a fast zero-crossing detection circuit, comprising: a sampling detection circuit, a differential amplifier component, a comparator component, and a Schmitt trigger, wherein the sampling detection circuit is used to acquire the voltage of a switch output node and the voltage of a power ground node; the differential amplifier component is used to amplify the voltage of the switch output node and the voltage of the power ground node respectively to obtain amplified voltages of the switch output node and the power ground node; the differential amplifier component is used to output a zero-crossing signal when the amplified voltages of the switch output node and the amplified voltages of the power ground node satisfy a preset zero-crossing condition; and the Schmitt trigger is used to output a zero-crossing detection result based on the zero-crossing signal from the comparator component.
[0006] Furthermore, in some embodiments, the sampling detection circuit includes: a first sampling switch transistor, the control terminal of which is connected to a switching node; and a second sampling switch transistor, the control terminal of which is connected to a power ground node.
[0007] Furthermore, in some embodiments, the differential amplification component includes a high-gain differential amplifier, the input of which is connected to the sampling detection circuit, and the other end of which is connected to the comparison component.
[0008] Furthermore, in some embodiments, the comparison component includes: a fast comparator, the input of which is connected to the high-gain differential amplifier, and the output of which is connected to the Schmitt trigger.
[0009] Furthermore, in some embodiments, the sampling detection circuit further includes: adjusting the width-to-length ratio of the sampling switch transistor in the sampling detection circuit.
[0010] Furthermore, in some embodiments, the differential amplifier component includes: controlling the magnitude of the voltage of the level-shifted switch output node and the voltage of the level-shifted power ground node.
[0011] Further, in some embodiments, the comparison component includes: a preamplifier, a latch comparator stage, and an output buffer stage. The preamplifier consists of differential input pairs composed of multiple pairs of high-transconductance MOSFETs, used to receive the amplified voltage of the switch output node and the amplified voltage of the power ground node, and to control the voltage difference between the voltage of the switch output node and the voltage of the power ground node. The latch comparator stage employs a cross-coupled structure to achieve rapid high-low level switching and output a latch signal. The output buffer stage is composed of multiple cascaded inverters, used to convert the latch signal into a standard logic level.
[0012] Furthermore, in some embodiments, the Schmitt trigger includes: a cross-coupled inverter pair, a voltage divider resistor network, and an output buffer, wherein the cross-coupled inverter pair is formed by two inverters cross-connected to form a positive feedback loop; the voltage divider resistor network is composed of multiple resistors and is configured with an upper threshold voltage and a lower threshold voltage; the output buffer is composed of inverters and is used to shape the output signal and output the zero-crossing detection result.
[0013] Furthermore, in some embodiments, the zero-crossing detection circuit further includes: controlling the lower switch of the synchronous buck converter to turn off when the zero-crossing detection result is high; controlling the lower switch to turn off when the zero-crossing detection result is low; and controlling the lower switch to turn on when the zero-crossing detection result is low. The fast zero-crossing detection circuit provided by the present invention includes a sampling detection circuit, a differential amplifier component, a comparator component, and a Schmitt trigger. The sampling detection circuit is used to acquire the voltage of the switch output node and the voltage of the power ground node. The differential amplifier component is used to amplify the two voltages respectively to obtain the amplified corresponding voltages. The comparator component is used to output a zero-crossing signal when the two amplified voltages meet a preset zero-crossing condition. The Schmitt trigger outputs the zero-crossing detection result according to the zero-crossing signal. This solves the problem of the risk of the switching transistor being broken down due to the slow detection of the zero-crossing detection circuit in related technologies, and improves the safety of the circuit components and the response speed of the zero-crossing detection circuit.
[0014] To achieve the above objectives, a second aspect of the present invention provides a zero-crossing detection method, employing any of the circuits described above, the method comprising the following steps: The voltage of the switch output node and the voltage of the power ground node are obtained through the sampling and detection circuit including at least two sampling switches. The response speed and accuracy of differential amplification are improved by using a differential amplification component connected to the sampling and detection circuit. The output signal is rapidly flipped when the inductor current crosses zero by a comparator connected to the differential amplifier component. The signal output by the comparison component is shaped by the Schmitt trigger to obtain the zero-crossing detection result.
[0015] The fast zero-crossing detection method provided by the present invention includes a sampling detection circuit, a differential amplifier component, a comparator component, and a Schmitt trigger. The sampling detection circuit is used to acquire the voltage of the switch output node and the voltage of the power ground node. The differential amplifier component is used to amplify the two voltages respectively to obtain the amplified corresponding voltages. The comparator component is used to output a zero-crossing signal when the two amplified voltages meet a preset zero-crossing condition. The Schmitt trigger outputs the zero-crossing detection result based on the zero-crossing signal. This method solves the problem of the risk of the switching transistor being damaged due to the slow detection of the zero-crossing detection circuit in related technologies, and improves the safety of circuit components and the response speed of the zero-crossing detection circuit.
[0016] Therefore, the present invention has the following beneficial effects: (1) The zero-crossing detection of the present invention improves the speed while ensuring accuracy.
[0017] (2) The present invention avoids the risk of power transistors being broken down due to abnormally high voltage at the SW node.
[0018] (3) The present invention avoids the negative current of the inductor consuming the energy stored in the capacitor, thus improving the conversion efficiency. Attached Figure Description
[0019] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a schematic diagram of a typical synchronous buck converter circuit. Figure 2 This is a schematic diagram of the first path structure of a synchronous buck converter circuit. Figure 3 A schematic diagram of the inductor freewheeling circuit structure for a synchronous buck converter circuit; Figure 4 The diagram shows the inductor current variation of a synchronous buck converter circuit under light-load discontinuous mode. Figure 5 This is a block diagram of a fast zero-crossing detection circuit provided according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a zero-crossing detection circuit according to a specific embodiment of the present invention; Figure 7 This is a flowchart illustrating a fast zero-crossing detection method provided according to an embodiment of the present invention. Detailed Implementation
[0020] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.
[0021] Before introducing the fast zero-crossing detection circuit of the present invention, let's briefly introduce the current synchronous buck converter circuit structure diagram.
[0022] Specifically, Figure 1 This is a schematic diagram of a typical synchronous buck converter circuit. Figure 2 This is a schematic diagram of the first path structure of a synchronous buck converter circuit. Figure 3 This is a schematic diagram of the inductor freewheeling path structure of a synchronous buck converter circuit, as shown below. Figure 1 As shown, a typical synchronous buck converter circuit includes a power supply, an upper switching transistor, a lower switching transistor, an inductor, a capacitor, and a load section. Among these components, such as... Figure 2 As shown, the first path is formed by the upper switching transistor, inductor, capacitor, and load section, as follows. Figure 3 As shown, the inductor freewheeling path is composed of the lower switching transistor, inductor, capacitor, and load.
[0023] Figure 4 The diagram shows the inductor current variation of a synchronous buck converter circuit in light-load discontinuous mode, as follows: Figure 4As shown, the broken line represents the change in inductor current with zero-crossing detection. If there is no zero-crossing detection or the zero-crossing detection is too slow, the inductor current will be negative (i.e., the dashed line). That is, after the inductor has released all its stored energy, the capacitor will release its stored energy in the opposite direction, which will cause the inductor to have a negative current. This will cause the voltage at node SW to be charged high, which will put the switching transistor at risk of breakdown. Therefore, to avoid this situation, a fast and accurate zero-crossing detection circuit is extremely necessary and essential.
[0024] The fast zero-crossing detection circuit and fast zero-crossing detection method provided according to embodiments of the present invention will be described below with reference to the accompanying drawings.
[0025] Figure 5 This is a block diagram of a fast zero-crossing detection circuit provided according to an embodiment of the present invention.
[0026] like Figure 5 As shown, the fast zero-crossing detection circuit 10 includes: a sampling detection circuit 100, a differential amplifier component 200, a comparator component 300, and a Schmitt trigger 400. The sampling and detection circuit 100 is used to acquire the voltage of the switch output node and the voltage of the power ground node; the differential amplifier component 200 is used to amplify the voltage of the switch output node and the voltage of the power ground node respectively to obtain the amplified voltage of the switch output node and the amplified voltage of the power ground node; the comparison component 300 is used to output a zero-crossing signal when the amplified voltage of the switch output node and the amplified voltage of the power ground node meet the preset zero-crossing condition; and the Schmitt trigger 400 is used to output the zero-crossing detection result based on the zero-crossing signal comparison component 300.
[0027] like Figure 6 As shown, Figure 6 The diagram below shows the structure of a zero-crossing detection circuit according to a specific embodiment of the present invention. In the zero-crossing detection circuit 20, the sampling detection circuit 100 includes: a first sampling switch transistor, the control terminal of which is connected to a switching node; and a second sampling switch transistor, the control terminal of which is connected to a power ground node.
[0028] For example, when the zero-crossing detection circuit of this invention is working, SW and power ground PGNG are sampled and level-shifted to obtain the corresponding levels MSW and MPGND. The voltage difference between the two nodes is differentially amplified by a high-gain differential amplifier to obtain the voltages RSW and RPGND. Then, a fast comparator compares the voltages of the two nodes and outputs the result. The higher value is valid. When the freewheeling circuit inductor current drops to 0, theoretically the voltage of node SW is equal to the voltage of PGND. The result of the fast comparator turns high, and the zero-crossing detection indicates zero crossing. Subsequently, the switching transistor is turned off under the control of the PG signal based on this result. Thus, one cycle of zero-crossing detection is completed.
[0029] Furthermore, in some embodiments, the differential amplifier component 200 includes a high-gain differential amplifier, the input of which is connected to the sampling detection circuit 100, and the output of which is connected to the comparison component 300.
[0030] It should be understood that without a high-gain differential amplifier, small voltage differences cannot be effectively identified, and zero-crossing detection will be delayed or misjudged, leading to incorrect turn-off timing of the next switching transistor. Therefore, a high-gain differential amplifier is needed to filter common-mode interference and retain only the true voltage difference signal to avoid interference causing false triggering of zero-crossing detection.
[0031] Specifically, the high-gain differential amplifier receives the sampled voltages of the switching node SW and the power ground node PGND, and obtains the sampled voltage MSW of the corresponding switching node SW and the sampled voltage MPGND of the corresponding power ground PGND. It calculates the difference between MSW and MPGND, and through a large amplification, converts the tiny voltage difference into a significant signal, which is then input to the subsequent comparison component.
[0032] Furthermore, in some embodiments, the comparison component 300 includes: a fast comparator, the input of which is connected to a high-gain differential amplifier, and the output of which is connected to a Schmitt trigger 400.
[0033] Specifically, the fast comparator receives signals from the high-gain differential amplifier, namely the amplified switching node voltage RSW and the amplified power ground node voltage RPGND. The fast comparator outputs a binary control signal, such as the PG signal, by comparing the magnitudes of RSW and RPGND. When RSW is greater than RPGND, it means that the SW voltage is higher than PGND, and the inductor still has a positive current (not yet zero). The comparator outputs a low level, and the lower switch remains on (i.e., freewheeling state). When RSW is close to RPGND, it means that the SW voltage is equal to PGND, and the inductor current has just reached zero. The comparator immediately outputs a high level, triggering the lower switch to turn off (i.e., blocking the negative current path) to ensure that the lower switch is turned off with zero delay.
[0034] Furthermore, in some embodiments, the sampling detection circuit 100 further includes: adjusting the width-to-length ratio of the sampling switch transistor in the sampling detection circuit 100.
[0035] The larger the width-to-length ratio of the sampling switch, the smaller the on-resistance, and the width-to-length ratio of the sampling switch also affects the turn-on and turn-off speeds.
[0036] Specifically, the voltage difference between SW and PGND may be extremely small at the zero-crossing point. If the on-resistance of the sampling switch is too large, the actual sampled voltage signal will be attenuated and cannot truly reflect the actual voltage difference between SW and PGND. Appropriately increasing the width-to-length ratio and reducing the on-resistance reduces signal loss in the sampling path, ensuring that the difference between MSW and MPGND can be accurately transmitted to the high-gain differential amplifier. At the same time, the voltage at the SW node dynamically changes with the switching on and off of the switch. If the switching speed of the sampling switch is too slow, the sampled signal will lag behind the actual SW voltage. Therefore, adjusting the width-to-length ratio of the sampling switch optimizes the front-end signal acquisition quality, ensuring that the voltage signals of SW and PGND are accurately and in real time acquired.
[0037] Furthermore, in some embodiments, the differential amplifier component 200 includes controlling the magnitude of the voltage at the level-shifted switch output node and the voltage at the level-shifted power ground node.
[0038] Furthermore, in some embodiments, the comparison component 300 includes: a preamplifier, a latch comparator stage, and an output buffer stage. The preamplifier consists of differential input pairs composed of multiple pairs of high transconductance MOSFETs, used to receive the amplified voltage of the switch output node and the amplified voltage of the power ground node, and to control the voltage difference between the voltage of the switch output node and the voltage of the power ground node. The latch comparator stage adopts a cross-coupled structure to achieve rapid switching between high and low levels and outputs a latch signal. The output buffer stage is composed of multiple cascaded inverters, used to convert the latch signal into a standard logic level.
[0039] Specifically, the preamplifier, as the first stage of signal processing, linearly amplifies the difference ΔV = RSW - RPGND between RSW and RPGND, converting the tiny difference at the zero-crossing moment into a signal that can be recognized by the subsequent latching comparator stage. At the same time, it suppresses common-mode interference (such as switching noise at the SW node) to avoid interference causing misjudgment of the difference. Finally, it outputs a stable differential signal to the latching comparator stage, providing a reliable basis for subsequent high and low level decisions.
[0040] Furthermore, the latch comparator is the core of the decision-making. The cross-coupled structure is responsible for quickly identifying the difference value and directly determines the speed of zero-crossing detection. Among them, the essence of the cross-coupled structure is a positive feedback loop. The output terminals of two MOS transistors are respectively connected to the input terminals of each other (for example, the drain of M1 is connected to the gate of M2, and the drain of M2 is connected to the gate of M1). Once there is a slight deviation in the input signal, it will be quickly amplified through positive feedback, making the output stable at a high level or a low level. If the ΔV signal output by the preamplifier changes from negative (i.e., RSW < RPGND) to positive (i.e., RSW > RPGND), the cross-coupled structure instantaneously completes the flipping of the output level through positive feedback. Once the output level flips, the positive feedback will maintain this state, and the output will not repeatedly jump even if there are slight fluctuations in the input ΔV.
[0041] Furthermore, the output buffer stage is the bridge connecting the comparison decision and the execution circuit. The output level of the latch comparator may be affected by the power supply voltage, while subsequent control circuits such as Schmitt triggers require standard logic levels. The multi-stage inverter can raise the signal level to the standard value through power supply configuration to ensure correct recognition by the subsequent circuits. And the output buffer stage can filter out the possible glitches or oscillations in the latch signal and output a rectangular wave with a steep edge, further improving the reliability of the control signal.
[0042] Furthermore, in some embodiments, the Schmitt trigger 400 includes: a cross-coupled inverter pair, a voltage-dividing resistor network, and an output buffer. Among them, the cross-coupled inverter pair forms a positive feedback loop by cross-connecting two inverters; the voltage-dividing resistor network is composed of multiple resistors and sets an upper threshold voltage and a lower threshold voltage; the output buffer is composed of an inverter and is used to shape the output signal and output the zero-crossing detection result.
[0043] Furthermore, in some embodiments, the zero-crossing detection circuit further includes: the zero-crossing detection result controls the lower switch tube of the synchronous buck converter to turn off; when the zero-crossing detection result is at a high level, it controls the lower switch tube to cut off; when the zero-crossing detection result is at a low level, it controls the lower switch tube to conduct.
[0044] Specifically, when the zero-crossing detection result is at a high level, it indicates that the inductor current has dropped to zero. At this time, it controls the lower switch tube to cut off, blocking the negative current path; when the zero-crossing detection result is at a low level, it indicates that there is still a positive current in the inductor, and the lower switch tube remains conducting to maintain continuous current, ensuring continuous energy transfer to the load, achieving precise control of turning off when the current reaches zero, protecting the switch tube and improving the conversion efficiency of the converter.
[0045] The fast zero-crossing detection circuit provided by the present invention includes a sampling detection circuit, a differential amplifier component, a comparator component, and a Schmitt trigger. The sampling detection circuit is used to acquire the voltage of the switch output node and the voltage of the power ground node. The differential amplifier component is used to amplify the two voltages respectively to obtain the amplified corresponding voltages. The comparator component is used to output a zero-crossing signal when the two amplified voltages meet a preset zero-crossing condition. The Schmitt trigger outputs the zero-crossing detection result according to the zero-crossing signal. This solves the problem of the risk of the switching transistor being broken down due to the slow detection of the zero-crossing detection circuit in related technologies, and improves the safety of the circuit components and the response speed of the zero-crossing detection circuit.
[0046] Next, a fast zero-crossing detection method according to an embodiment of the present invention will be described with reference to the accompanying drawings.
[0047] Figure 7 This is a flowchart illustrating a fast zero-crossing detection method provided according to an embodiment of the present invention.
[0048] like Figure 7 As shown, this fast zero-crossing detection method includes the following steps: In step S701, the voltage of the switch output node and the voltage of the power ground node are obtained by a sampling detection circuit including at least two sampling switches.
[0049] In step S702, the response speed and accuracy of differential amplification are improved by using a differential amplification component connected to the sampling detection circuit.
[0050] In step S703, the output signal is rapidly flipped when the inductor current crosses zero by a comparator connected to the differential amplifier component.
[0051] In step S704, the signal output by the comparator is shaped by a Schmitt trigger to obtain the zero-crossing detection result.
[0052] It should be noted that the foregoing explanation of the fast zero-crossing detection circuit embodiment also applies to the fast zero-crossing detection method of this embodiment, and will not be repeated here.
[0053] The fast zero-crossing detection method provided by the present invention includes a sampling detection circuit, a differential amplifier component, a comparator component, and a Schmitt trigger. The sampling detection circuit is used to acquire the voltage of the switch output node and the voltage of the power ground node. The differential amplifier component is used to amplify the two voltages respectively to obtain the amplified corresponding voltages. The comparator component is used to output a zero-crossing signal when the two amplified voltages meet a preset zero-crossing condition. The Schmitt trigger outputs the zero-crossing detection result based on the zero-crossing signal. This method solves the problem of the risk of the switching transistor being damaged due to the slow detection of the zero-crossing detection circuit in related technologies, and improves the safety of circuit components and the response speed of the zero-crossing detection circuit.
[0054] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0055] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0056] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
Claims
1. A fast zero-crossing detection circuit, characterized in that, include: The sampling and detection circuit consists of a differential amplifier, a comparator, and a Schmitt trigger. The sampling and detection circuit is used to obtain the voltage of the switch output node and the voltage of the power ground node; The differential amplifier component is used to amplify the voltage of the switch output node and the voltage of the power ground node respectively, to obtain the amplified voltage of the switch output node and the amplified voltage of the power ground node. The comparison component is used to output a zero-crossing signal when the amplified switch output node voltage and the amplified power ground node voltage meet a preset zero-crossing condition. The Schmitt trigger is used to shape the zero-crossing signal and output the zero-crossing detection result. The sampling and detection circuit includes: a first sampling switch transistor, the control terminal of which is connected to a switching node; and a second sampling switch transistor, the control terminal of which is connected to a power ground node. The sampling and detection circuit further includes adjusting the width-to-length ratio of the sampling switch transistor in the sampling and detection circuit.
2. The circuit according to claim 1, characterized in that, The differential amplifier component includes: A high-gain differential amplifier, wherein the input terminal of the high-gain differential amplifier is connected to the sampling and detection circuit, and the other terminal is connected to the comparison component.
3. The circuit according to claim 2, characterized in that, The comparison component includes: A fast comparator, the input of which is connected to the high-gain differential amplifier, and the output of which is connected to the Schmitt trigger.
4. The circuit according to claim 2, characterized in that, The differential amplifier component includes: The voltage of the switch output node after level shifting and the voltage of the power ground node after level shifting are controlled.
5. The circuit according to claim 3, characterized in that, The comparison component includes: The preamplifier, latch comparator stage, and output buffer stage, among which, The preamplifier consists of a differential input pair composed of multiple pairs of high transconductance MOS transistors, used to receive the amplified voltage of the switch output node and the amplified voltage of the power ground node, and to control the voltage difference between the voltage of the switch output node and the voltage of the power ground node. The latch comparator stage adopts a cross-coupled structure to achieve rapid switching of high and low levels and output a latch signal; The output buffer stage is composed of multiple cascaded inverters, used to convert the latched signal into a standard logic level.
6. The circuit according to claim 1, characterized in that, The Schmitt trigger includes: The system consists of a cross-coupled inverter pair, a voltage divider resistor network, and an output buffer. The cross-coupled inverter pair is formed by two inverters cross-connected to form a positive feedback loop; The voltage divider resistor network consists of multiple resistors and is configured with an upper threshold voltage and a lower threshold voltage. The output buffer is composed of an inverter and is used to shape the output signal and output the zero-crossing detection result.
7. The circuit according to claim 1, characterized in that, Also includes: The zero-crossing detection result controls the lower switch of the synchronous buck converter to turn off; When the zero-crossing detection result is high, the lower control switch is turned off; When the zero-crossing detection result is low, the lower control switch is turned on.
8. A fast zero-crossing detection method, characterized in that, The fast zero-crossing detection circuit as described in any one of claims 1-7 is used, wherein the method comprises: The voltage of the switch output node and the voltage of the power ground node are obtained through the sampling and detection circuit including at least two sampling switches. The response speed and accuracy of differential amplification are improved by using a differential amplification component connected to the sampling and detection circuit. The output signal is rapidly flipped when the inductor current crosses zero by a comparator connected to the differential amplifier component. The Schmitt trigger is used to shape the zero-crossing signal and output the zero-crossing detection result. The sampling and detection circuit includes: a first sampling switch transistor, the control terminal of which is connected to a switching node; and a second sampling switch transistor, the control terminal of which is connected to a power ground node. The sampling and detection circuit further includes adjusting the width-to-length ratio of the sampling switch transistor in the sampling and detection circuit.