A low-power clock management architecture for chips based on asynchronous circuits
By using an asynchronous detection circuit to completely shut down and asynchronously wake up the chip module clock, the problems of the module clock not being able to be completely shut down and the oscillator taking too long to start up in the prior art are solved, achieving the effects of low power consumption and fast wake-up.
Patent Information
- Application Number
- CN202511208051.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-27
- Publication Date
- 2026-07-31
- Estimated Expiration
- 2045-08-27
AI Technical Summary
In the low-power mode of existing chips, the clock of some modules cannot be completely turned off, resulting in excessive dynamic power consumption. At the same time, there is a problem with the oscillator taking a long time to turn off and restart.
An asynchronous detection circuit is adopted, which realizes the complete shutdown and asynchronous wake-up of the module clock through a wake-up detection circuit and an event processing circuit. The asynchronous circuit detects the wake-up signal to turn the clock on and off.
It achieves complete shutdown and asynchronous wake-up of module clock in different modes, minimizing dynamic power consumption and reducing the startup time of the chip from low-power mode to normal mode.
Smart Images
Figure CN121254974B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip clock management technology, and in particular to a low-power clock management architecture for chips based on asynchronous circuits. Background Technology
[0002] Clock signals are used for timing control in virtually all electronic systems and integrated circuits. As chip designs become increasingly complex, power consumption has become a significant factor limiting chip performance improvements.
[0003] Existing solutions for low-power modes in chips typically involve clock gating or disabling the oscillator. Clock gating methods include... Figure 1 As shown, each IP individually applies clock gating to achieve low power consumption. However, in actual circuits, not all devices can be clock-gated. This results in incomplete clock shutdown of modules when the chip enters low-power mode, with some clocks still toggling. The direct result is excessive dynamic power consumption of the chip. Furthermore, shutting down the oscillator takes time during restart. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this invention utilizes an asynchronous detection circuit to achieve the simultaneous complete shutdown of the module clock, minimizing dynamic power consumption, and the detection of a wake-up signal to turn the clock back on.
[0005] To achieve the above objectives, the present invention provides a low-power clock management architecture for chips based on asynchronous circuits, comprising two branches: a wake-up detection circuit and an event processing circuit, which are respectively used for the detection of wake-up related signals and chip modes. The output signal of the wake-up detection circuit is connected to the reset port of the gate enable generation module, and the output signal of the event processing circuit is connected to the input terminal of the gate enable generation module. The gate enable generation module generates a gate enable instruction, which is sent to the gate control module through a second signal synchronization module to obtain a gate clock signal for turning the clock on or off. The wake-up detection circuit includes a first signal synchronization module, an XOR generation and reset module, and a synchronization release module. The first signal synchronization module is used to synchronize and output wake-up-related signals. The XOR generation and reset module performs an XOR operation between the output of the first signal synchronization module and the wake-up-related signals, and outputs the result to the reset port of the synchronization release module. The synchronization release module obtains a synchronization release signal based on the output of the XOR generation and reset module, and outputs it to the reset port of the gate enable generation module. The event processing circuit includes a related event processing module and a counter. The related event processing module is used to determine the current chip mode and output a normal mode or low power mode indicator to the timer. The timer outputs a low level in normal mode and starts timing in low power mode. After timing for a set time, it outputs a high level to the gate enable generation module. The output of the gate enable generation module is connected to the timer for resetting the counter.
[0006] Furthermore, the clocks of the synchronization release module, the timer, and the second signal module are normally open and are not controlled by the gated clock signal, while the clocks of other modules are controlled by the gated clock signal.
[0007] Furthermore, when the chip is in normal mode, the counter sends a low level, and the wake-up related signal does not change. Therefore, after passing through the XOR generation reset module, a high level signal is generated, and the output of the synchronization release module is always high, so that the gate enable generation module is reset to the release state. At this time, the gate enable generation module transmits the timer output low level, which is output to the clock gate module through the second signal synchronization module, and the clock is in the open state.
[0008] Furthermore, when the chip enters low-power mode from normal mode, the clocks of all modules remain on. The event processing module outputs a low-power mode indication to the counter, which starts counting. After the set time is reached, it sends a high-level signal to the gate enable generation module. Since the wake-up related signals have not changed at this time, a high-level signal is generated after passing through the XOR reset generation module. The synchronization release module outputs a constant high signal, causing the gate enable generation module to reset to the release state. At this time, the gate enable generation module transmits a high-level signal from the timer output, which is then output to the clock gate module through the second signal synchronization module, turning off the clock and causing the chip to enter low-power mode. Simultaneously, the high-level signal output from the gate enable generation module resets the counter.
[0009] Furthermore, when the chip enters normal mode from low-power mode, the wake-up related signal jumps and generates a low-level signal after passing through the XOR reset module. The output of the synchronization release module is also low, causing the gate enable generation module to be asynchronously reset. At this time, the gate enable generation module outputs a low level, which is output to the clock gate module through the second signal synchronization module to turn on the clock, and the chip enters normal mode.
[0010] The beneficial effects of this invention are: This invention can completely shut down the clocks of different modules under different conditions according to actual needs. Even when the clock is off, the wake-up signal can be detected by the asynchronous circuit to turn the clock back on. Attached Figure Description
[0011] Figure 1 This is a schematic diagram of a common low-power implementation architecture in embodiments of the present invention.
[0012] Figure 2 This is a schematic diagram of a low-power clock management architecture for chips based on asynchronous circuits, according to an embodiment of the present invention.
[0013] Figure 3 This is a schematic diagram of a clock management architecture for low-power chips based on asynchronous circuits, as described in an embodiment of the present invention.
[0014] Figure 4 This is a timing diagram of a low-power clock management architecture for a chip based on asynchronous circuits, as described in an embodiment of the present invention. Detailed Implementation
[0015] The present invention will be further explained and described below with reference to the accompanying drawings and embodiments.
[0016] like Figures 2-4 As shown, this embodiment of the invention provides a low-power clock management architecture for chips based on asynchronous circuits, including two branches: a wake-up detection circuit and an event processing circuit, which are used to detect wake-up related signals and chip modes, respectively. The output signal of the wake-up detection circuit is connected to the reset port of the gate enable generation module, and the output signal of the event processing circuit is connected to the input terminal of the gate enable generation module. The gate enable generation module generates a gate enable instruction, which is sent to the gate control module through the second signal synchronization module to obtain a gate clock signal, and the clock is turned on or off.
[0017] The wake-up detection circuit includes a first signal synchronization module, an XOR generation and reset module, and a synchronization release module. The first signal synchronization module synchronizes and outputs wake-up-related signals. The XOR generation and reset module performs an XOR operation between the output of the first signal synchronization module and the wake-up-related signals, and outputs the result to the reset port of the synchronization release module. The synchronization release module obtains the synchronization release signal based on the output of the XOR generation and reset module, and outputs it to the reset port of the gate enable generation module.
[0018] The event processing circuit includes a related event processing module and a counter. The related event processing module is used to determine the current chip mode and output a normal mode or low power mode indicator to the timer. The timer outputs a low level in normal mode and starts counting in low power mode. After counting to the set time, it outputs a high level to the gate enable generation module. The output of the gate enable generation module is connected to the timer for resetting the counter.
[0019] The clocks of the synchronous release module, timer, and second signal module are normally open and are not controlled by the gated clock signal, while the clocks of other modules are controlled by the gated clock signal.
[0020] The working principle of this clock management architecture is as follows: When the chip is in normal mode, the counter sends a low level, and the wake-up related signal does not change. Therefore, after passing through the XOR generation reset module, a high level signal is generated, and the output of the synchronization release module is always high, so that the gate enable generation module is reset to the release state. At this time, the gate enable generation module transmits the timer output low level, which is output to the clock gate module through the second signal synchronization module, and the clock is in the open state.
[0021] When the chip enters low-power mode from normal mode, the clocks of all modules remain on. The event processing module outputs a low-power mode indicator to the counter, which starts counting. After the set time is reached, a high-level signal is sent to the gating enable generation module. Since the wake-up related signals have not changed at this time, a high-level signal is generated after passing through the XOR generation reset module. The synchronization release module outputs a constant high level, causing the gating enable generation module to reset to the release state. At this time, the gating enable generation module transmits the timer output high level, which is then output to the clock gating module through the second signal synchronization module, turning off the clock and allowing the chip to enter low-power mode.
[0022] When the chip transitions from low-power mode to normal mode, it needs to be woken up. The wake-up signal will then jump. The signal after the jump differs from the wake-up signal level previously recorded by the signal synchronization module. After passing through the XOR reset module, a low-level signal is generated. The synchronization release module also outputs a low level, causing the gating enable module to asynchronously reset. At this point, the gating enable module outputs a low level, which is then output to the clock gating module via the second signal synchronization module, turning on the clock and allowing the chip to enter normal mode. After the wake-up event is processed in the relevant event handling module, the clock shutdown operation described above is repeated. The clock is then turned off again after the timer finishes counting down.
[0023] The embodiments described herein are merely preferred embodiments and are not intended to limit the scope of the invention. Various modifications and improvements made by those skilled in the art to the technical solutions of this invention without departing from its conceptual design should fall within the protection scope of this invention, which is defined by the appended claims.
Claims
1. A clock management architecture for low-power chips based on asynchronous circuits, characterized in that, include: The circuit consists of two branches: a wake-up detection circuit and an event processing circuit. These are used to detect wake-up-related signals and chip modes, respectively. The output signal of the wake-up detection circuit is connected to the reset port of the gate enable generation module, and the output signal of the event processing circuit is connected to the input of the gate enable generation module. The gate enable generation module generates a gate enable command, which is sent to the gate control module through the second signal synchronization module to obtain the gate clock signal, and then the clock is turned on or off. The wake-up detection circuit includes a first signal synchronization module, an XOR generation and reset module, and a synchronization release module. The first signal synchronization module is used to synchronize and output wake-up-related signals. The XOR generation and reset module performs an XOR operation between the output of the first signal synchronization module and the wake-up-related signals, and outputs the result to the reset port of the synchronization release module. The synchronization release module obtains a synchronization release signal based on the output of the XOR generation and reset module, and outputs it to the reset port of the gate enable generation module. The event processing circuit includes a related event processing module and a timer. The related event processing module is used to determine the current chip mode and output a normal mode or low power mode indicator to the timer. The timer outputs a low level in normal mode and starts timing in low power mode. After timing for a set time, it outputs a high level to the gate enable generation module. The output of the gate enable generation module is connected to the timer for resetting the timer. When the chip enters low-power mode from normal mode, the clocks of all modules remain on. The event processing module outputs a low-power mode indicator to the timer, which starts counting. After the set time is reached, a high-level signal is sent to the gating enable generation module. Since the wake-up related signals have not changed at this time, a high-level signal is generated after passing through the XOR reset generation module. The synchronization release module outputs a constant high level, causing the gating enable generation module to reset to the release state. At this time, the gating enable generation module transmits the high-level output of the timer, which is then output to the gating module through the second signal synchronization module, turning off the clock and allowing the chip to enter low-power mode. When the chip enters normal mode from low-power mode, the wake-up related signal jumps and generates a low-level signal after passing through the XOR reset module. The output of the synchronization release module is also low, causing the gate enable generation module to be asynchronously reset. At this time, the gate enable generation module outputs a low level, which is output to the gate module through the second signal synchronization module to turn on the clock, and the chip enters normal mode.
2. The low-power clock management architecture for chips based on asynchronous circuits as described in claim 1, characterized in that: The clocks of the synchronization release module, the timer, and the second signal synchronization module are normally open and are not controlled by the gated clock signal, while the clocks of other modules are controlled by the gated clock signal.
3. The low-power clock management architecture for chips based on asynchronous circuits as described in claim 1, characterized in that: When the chip is in normal mode, the timer sends a low level, and the wake-up related signal does not change. Therefore, after passing through the XOR generation reset module, a high level signal is generated, and the output of the synchronization release module is always high, so that the gate enable generation module is reset to the release state. At this time, the gate enable generation module transmits the timer output low level, which is output to the gate module through the second signal synchronization module, and the clock is in the open state.
4. The low-power clock management architecture for chips based on asynchronous circuits as described in claim 1, characterized in that: When the chip enters low-power mode from normal mode, the clocks of all modules remain on. The event processing module outputs a low-power mode indication to the timer, which starts counting. After the set time is reached, a high-level signal is sent to the gate enable generation module. Since the wake-up related signals have not changed at this time, a high-level signal is generated after passing through the XOR reset generation module. The synchronization release module outputs a constant high level, resetting the gate enable generation module to the release state. At this time, the gate enable generation module transmits the high-level output of the timer, which is then output to the gate module through the second signal synchronization module, turning off the clock and putting the chip into low-power mode. Simultaneously, the high-level output of the gate enable generation module resets the timer.